1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This file implements the lowering of LLVM calls to machine code calls for
12 /// GlobalISel.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "X86CallLowering.h"
17 #include "X86CallingConv.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
27 #include "llvm/CodeGen/GlobalISel/Utils.h"
28 #include "llvm/CodeGen/LowLevelType.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/TargetInstrInfo.h"
37 #include "llvm/CodeGen/TargetSubtargetInfo.h"
38 #include "llvm/CodeGen/ValueTypes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/Value.h"
43 #include "llvm/MC/MCRegisterInfo.h"
44 #include "llvm/Support/LowLevelTypeImpl.h"
45 #include "llvm/Support/MachineValueType.h"
46 #include <cassert>
47 #include <cstdint>
48
49 using namespace llvm;
50
51 #include "X86GenCallingConv.inc"
52
X86CallLowering(const X86TargetLowering & TLI)53 X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
54 : CallLowering(&TLI) {}
55
splitToValueTypes(const ArgInfo & OrigArg,SmallVectorImpl<ArgInfo> & SplitArgs,const DataLayout & DL,MachineRegisterInfo & MRI,SplitArgTy PerformArgSplit) const56 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
57 SmallVectorImpl<ArgInfo> &SplitArgs,
58 const DataLayout &DL,
59 MachineRegisterInfo &MRI,
60 SplitArgTy PerformArgSplit) const {
61 const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
62 LLVMContext &Context = OrigArg.Ty->getContext();
63
64 SmallVector<EVT, 4> SplitVTs;
65 SmallVector<uint64_t, 4> Offsets;
66 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
67
68 if (SplitVTs.size() != 1) {
69 // TODO: support struct/array split
70 return false;
71 }
72
73 EVT VT = SplitVTs[0];
74 unsigned NumParts = TLI.getNumRegisters(Context, VT);
75
76 if (NumParts == 1) {
77 // replace the original type ( pointer -> GPR ).
78 SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context),
79 OrigArg.Flags, OrigArg.IsFixed);
80 return true;
81 }
82
83 SmallVector<unsigned, 8> SplitRegs;
84
85 EVT PartVT = TLI.getRegisterType(Context, VT);
86 Type *PartTy = PartVT.getTypeForEVT(Context);
87
88 for (unsigned i = 0; i < NumParts; ++i) {
89 ArgInfo Info =
90 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
91 PartTy, OrigArg.Flags};
92 SplitArgs.push_back(Info);
93 SplitRegs.push_back(Info.Reg);
94 }
95
96 PerformArgSplit(SplitRegs);
97 return true;
98 }
99
100 namespace {
101
102 struct OutgoingValueHandler : public CallLowering::ValueHandler {
OutgoingValueHandler__anon1c3ebffe0111::OutgoingValueHandler103 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
104 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
105 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
106 DL(MIRBuilder.getMF().getDataLayout()),
107 STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
108
getStackAddress__anon1c3ebffe0111::OutgoingValueHandler109 unsigned getStackAddress(uint64_t Size, int64_t Offset,
110 MachinePointerInfo &MPO) override {
111 LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
112 LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
113 unsigned SPReg = MRI.createGenericVirtualRegister(p0);
114 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
115
116 unsigned OffsetReg = MRI.createGenericVirtualRegister(SType);
117 MIRBuilder.buildConstant(OffsetReg, Offset);
118
119 unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
120 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
121
122 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
123 return AddrReg;
124 }
125
assignValueToReg__anon1c3ebffe0111::OutgoingValueHandler126 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
127 CCValAssign &VA) override {
128 MIB.addUse(PhysReg, RegState::Implicit);
129
130 unsigned ExtReg;
131 // If we are copying the value to a physical register with the
132 // size larger than the size of the value itself - build AnyExt
133 // to the size of the register first and only then do the copy.
134 // The example of that would be copying from s32 to xmm0, for which
135 // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
136 // we expect normal extendRegister mechanism to work.
137 unsigned PhysRegSize =
138 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
139 unsigned ValSize = VA.getValVT().getSizeInBits();
140 unsigned LocSize = VA.getLocVT().getSizeInBits();
141 if (PhysRegSize > ValSize && LocSize == ValSize) {
142 assert((PhysRegSize == 128 || PhysRegSize == 80) && "We expect that to be 128 bit");
143 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
144 ExtReg = MIB->getOperand(0).getReg();
145 } else
146 ExtReg = extendRegister(ValVReg, VA);
147
148 MIRBuilder.buildCopy(PhysReg, ExtReg);
149 }
150
assignValueToAddress__anon1c3ebffe0111::OutgoingValueHandler151 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
152 MachinePointerInfo &MPO, CCValAssign &VA) override {
153 unsigned ExtReg = extendRegister(ValVReg, VA);
154 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
155 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
156 /* Alignment */ 0);
157 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
158 }
159
assignArg__anon1c3ebffe0111::OutgoingValueHandler160 bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
161 CCValAssign::LocInfo LocInfo,
162 const CallLowering::ArgInfo &Info, CCState &State) override {
163 bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
164 StackSize = State.getNextStackOffset();
165
166 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
167 X86::XMM3, X86::XMM4, X86::XMM5,
168 X86::XMM6, X86::XMM7};
169 if (!Info.IsFixed)
170 NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
171
172 return Res;
173 }
174
getStackSize__anon1c3ebffe0111::OutgoingValueHandler175 uint64_t getStackSize() { return StackSize; }
getNumXmmRegs__anon1c3ebffe0111::OutgoingValueHandler176 uint64_t getNumXmmRegs() { return NumXMMRegs; }
177
178 protected:
179 MachineInstrBuilder &MIB;
180 uint64_t StackSize = 0;
181 const DataLayout &DL;
182 const X86Subtarget &STI;
183 unsigned NumXMMRegs = 0;
184 };
185
186 } // end anonymous namespace
187
lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,unsigned VReg) const188 bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
189 const Value *Val, unsigned VReg) const {
190 assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
191
192 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
193
194 if (VReg) {
195 MachineFunction &MF = MIRBuilder.getMF();
196 MachineRegisterInfo &MRI = MF.getRegInfo();
197 auto &DL = MF.getDataLayout();
198 const Function &F = MF.getFunction();
199
200 ArgInfo OrigArg{VReg, Val->getType()};
201 setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F);
202
203 SmallVector<ArgInfo, 8> SplitArgs;
204 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
205 [&](ArrayRef<unsigned> Regs) {
206 MIRBuilder.buildUnmerge(Regs, VReg);
207 }))
208 return false;
209
210 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
211 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
212 return false;
213 }
214
215 MIRBuilder.insertInstr(MIB);
216 return true;
217 }
218
219 namespace {
220
221 struct IncomingValueHandler : public CallLowering::ValueHandler {
IncomingValueHandler__anon1c3ebffe0311::IncomingValueHandler222 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
223 CCAssignFn *AssignFn)
224 : ValueHandler(MIRBuilder, MRI, AssignFn),
225 DL(MIRBuilder.getMF().getDataLayout()) {}
226
getStackAddress__anon1c3ebffe0311::IncomingValueHandler227 unsigned getStackAddress(uint64_t Size, int64_t Offset,
228 MachinePointerInfo &MPO) override {
229 auto &MFI = MIRBuilder.getMF().getFrameInfo();
230 int FI = MFI.CreateFixedObject(Size, Offset, true);
231 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
232
233 unsigned AddrReg = MRI.createGenericVirtualRegister(
234 LLT::pointer(0, DL.getPointerSizeInBits(0)));
235 MIRBuilder.buildFrameIndex(AddrReg, FI);
236 return AddrReg;
237 }
238
assignValueToAddress__anon1c3ebffe0311::IncomingValueHandler239 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
240 MachinePointerInfo &MPO, CCValAssign &VA) override {
241 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
242 MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
243 0);
244 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
245 }
246
assignValueToReg__anon1c3ebffe0311::IncomingValueHandler247 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
248 CCValAssign &VA) override {
249 markPhysRegUsed(PhysReg);
250
251 switch (VA.getLocInfo()) {
252 default: {
253 // If we are copying the value from a physical register with the
254 // size larger than the size of the value itself - build the copy
255 // of the phys reg first and then build the truncation of that copy.
256 // The example of that would be copying from xmm0 to s32, for which
257 // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
258 // we expect this to be handled in SExt/ZExt/AExt case.
259 unsigned PhysRegSize =
260 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
261 unsigned ValSize = VA.getValVT().getSizeInBits();
262 unsigned LocSize = VA.getLocVT().getSizeInBits();
263 if (PhysRegSize > ValSize && LocSize == ValSize) {
264 auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
265 MIRBuilder.buildTrunc(ValVReg, Copy);
266 return;
267 }
268
269 MIRBuilder.buildCopy(ValVReg, PhysReg);
270 break;
271 }
272 case CCValAssign::LocInfo::SExt:
273 case CCValAssign::LocInfo::ZExt:
274 case CCValAssign::LocInfo::AExt: {
275 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
276 MIRBuilder.buildTrunc(ValVReg, Copy);
277 break;
278 }
279 }
280 }
281
282 /// How the physical register gets marked varies between formal
283 /// parameters (it's a basic-block live-in), and a call instruction
284 /// (it's an implicit-def of the BL).
285 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
286
287 protected:
288 const DataLayout &DL;
289 };
290
291 struct FormalArgHandler : public IncomingValueHandler {
FormalArgHandler__anon1c3ebffe0311::FormalArgHandler292 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
293 CCAssignFn *AssignFn)
294 : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
295
markPhysRegUsed__anon1c3ebffe0311::FormalArgHandler296 void markPhysRegUsed(unsigned PhysReg) override {
297 MIRBuilder.getMBB().addLiveIn(PhysReg);
298 }
299 };
300
301 struct CallReturnHandler : public IncomingValueHandler {
CallReturnHandler__anon1c3ebffe0311::CallReturnHandler302 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
303 CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
304 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
305
markPhysRegUsed__anon1c3ebffe0311::CallReturnHandler306 void markPhysRegUsed(unsigned PhysReg) override {
307 MIB.addDef(PhysReg, RegState::Implicit);
308 }
309
310 protected:
311 MachineInstrBuilder &MIB;
312 };
313
314 } // end anonymous namespace
315
lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<unsigned> VRegs) const316 bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
317 const Function &F,
318 ArrayRef<unsigned> VRegs) const {
319 if (F.arg_empty())
320 return true;
321
322 // TODO: handle variadic function
323 if (F.isVarArg())
324 return false;
325
326 MachineFunction &MF = MIRBuilder.getMF();
327 MachineRegisterInfo &MRI = MF.getRegInfo();
328 auto DL = MF.getDataLayout();
329
330 SmallVector<ArgInfo, 8> SplitArgs;
331 unsigned Idx = 0;
332 for (auto &Arg : F.args()) {
333
334 // TODO: handle not simple cases.
335 if (Arg.hasAttribute(Attribute::ByVal) ||
336 Arg.hasAttribute(Attribute::InReg) ||
337 Arg.hasAttribute(Attribute::StructRet) ||
338 Arg.hasAttribute(Attribute::SwiftSelf) ||
339 Arg.hasAttribute(Attribute::SwiftError) ||
340 Arg.hasAttribute(Attribute::Nest))
341 return false;
342
343 ArgInfo OrigArg(VRegs[Idx], Arg.getType());
344 setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
345 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
346 [&](ArrayRef<unsigned> Regs) {
347 MIRBuilder.buildMerge(VRegs[Idx], Regs);
348 }))
349 return false;
350 Idx++;
351 }
352
353 MachineBasicBlock &MBB = MIRBuilder.getMBB();
354 if (!MBB.empty())
355 MIRBuilder.setInstr(*MBB.begin());
356
357 FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
358 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
359 return false;
360
361 // Move back to the end of the basic block.
362 MIRBuilder.setMBB(MBB);
363
364 return true;
365 }
366
lowerCall(MachineIRBuilder & MIRBuilder,CallingConv::ID CallConv,const MachineOperand & Callee,const ArgInfo & OrigRet,ArrayRef<ArgInfo> OrigArgs) const367 bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
368 CallingConv::ID CallConv,
369 const MachineOperand &Callee,
370 const ArgInfo &OrigRet,
371 ArrayRef<ArgInfo> OrigArgs) const {
372 MachineFunction &MF = MIRBuilder.getMF();
373 const Function &F = MF.getFunction();
374 MachineRegisterInfo &MRI = MF.getRegInfo();
375 auto &DL = F.getParent()->getDataLayout();
376 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
377 const TargetInstrInfo &TII = *STI.getInstrInfo();
378 auto TRI = STI.getRegisterInfo();
379
380 // Handle only Linux C, X86_64_SysV calling conventions for now.
381 if (!STI.isTargetLinux() ||
382 !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV))
383 return false;
384
385 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
386 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
387
388 // Create a temporarily-floating call instruction so we can add the implicit
389 // uses of arg registers.
390 bool Is64Bit = STI.is64Bit();
391 unsigned CallOpc = Callee.isReg()
392 ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
393 : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
394
395 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
396 TRI->getCallPreservedMask(MF, CallConv));
397
398 SmallVector<ArgInfo, 8> SplitArgs;
399 for (const auto &OrigArg : OrigArgs) {
400
401 // TODO: handle not simple cases.
402 if (OrigArg.Flags.isByVal())
403 return false;
404
405 if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
406 [&](ArrayRef<unsigned> Regs) {
407 MIRBuilder.buildUnmerge(Regs, OrigArg.Reg);
408 }))
409 return false;
410 }
411 // Do the actual argument marshalling.
412 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
413 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
414 return false;
415
416 bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed;
417 if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) {
418 // From AMD64 ABI document:
419 // For calls that may call functions that use varargs or stdargs
420 // (prototype-less calls or calls to functions containing ellipsis (...) in
421 // the declaration) %al is used as hidden argument to specify the number
422 // of SSE registers used. The contents of %al do not need to match exactly
423 // the number of registers, but must be an ubound on the number of SSE
424 // registers used and is in the range 0 - 8 inclusive.
425
426 MIRBuilder.buildInstr(X86::MOV8ri)
427 .addDef(X86::AL)
428 .addImm(Handler.getNumXmmRegs());
429 MIB.addUse(X86::AL, RegState::Implicit);
430 }
431
432 // Now we can add the actual call instruction to the correct basic block.
433 MIRBuilder.insertInstr(MIB);
434
435 // If Callee is a reg, since it is used by a target specific
436 // instruction, it must have a register class matching the
437 // constraint of that instruction.
438 if (Callee.isReg())
439 MIB->getOperand(0).setReg(constrainOperandRegClass(
440 MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
441 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0));
442
443 // Finally we can copy the returned value back into its virtual-register. In
444 // symmetry with the arguments, the physical register must be an
445 // implicit-define of the call instruction.
446
447 if (OrigRet.Reg) {
448 SplitArgs.clear();
449 SmallVector<unsigned, 8> NewRegs;
450
451 if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
452 [&](ArrayRef<unsigned> Regs) {
453 NewRegs.assign(Regs.begin(), Regs.end());
454 }))
455 return false;
456
457 CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
458 if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
459 return false;
460
461 if (!NewRegs.empty())
462 MIRBuilder.buildMerge(OrigRet.Reg, NewRegs);
463 }
464
465 CallSeqStart.addImm(Handler.getStackSize())
466 .addImm(0 /* see getFrameTotalSize */)
467 .addImm(0 /* see getFrameAdjustment */);
468
469 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
470 MIRBuilder.buildInstr(AdjStackUp)
471 .addImm(Handler.getStackSize())
472 .addImm(0 /* NumBytesForCalleeToPop */);
473
474 return true;
475 }
476