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1  /* SPDX-License-Identifier: GPL-2.0+ */
2  /*
3   * Copyright 2013-2014 Freescale Semiconductor, Inc.
4   *
5   * Register definitions for Freescale QSPI
6   */
7  
8  #ifndef _FSL_QSPI_H_
9  #define _FSL_QSPI_H_
10  
11  struct fsl_qspi_regs {
12  	u32 mcr;
13  	u32 rsvd0[1];
14  	u32 ipcr;
15  	u32 flshcr;
16  	u32 buf0cr;
17  	u32 buf1cr;
18  	u32 buf2cr;
19  	u32 buf3cr;
20  	u32 bfgencr;
21  	u32 soccr;
22  	u32 rsvd1[2];
23  	u32 buf0ind;
24  	u32 buf1ind;
25  	u32 buf2ind;
26  	u32 rsvd2[49];
27  	u32 sfar;
28  	u32 rsvd3[1];
29  	u32 smpr;
30  	u32 rbsr;
31  	u32 rbct;
32  	u32 rsvd4[15];
33  	u32 tbsr;
34  	u32 tbdr;
35  	u32 rsvd5[1];
36  	u32 sr;
37  	u32 fr;
38  	u32 rser;
39  	u32 spndst;
40  	u32 sptrclr;
41  	u32 rsvd6[4];
42  	u32 sfa1ad;
43  	u32 sfa2ad;
44  	u32 sfb1ad;
45  	u32 sfb2ad;
46  	u32 rsvd7[28];
47  	u32 rbdr[32];
48  	u32 rsvd8[32];
49  	u32 lutkey;
50  	u32 lckcr;
51  	u32 rsvd9[2];
52  	u32 lut[64];
53  };
54  
55  #define QSPI_IPCR_SEQID_SHIFT		24
56  #define QSPI_IPCR_SEQID_MASK		(0xf << QSPI_IPCR_SEQID_SHIFT)
57  
58  #define QSPI_MCR_END_CFD_SHIFT		2
59  #define QSPI_MCR_END_CFD_MASK		(3 << QSPI_MCR_END_CFD_SHIFT)
60  #ifdef CONFIG_SYS_FSL_QSPI_AHB
61  /* AHB needs 64bit operation */
62  #define QSPI_MCR_END_CFD_LE		(3 << QSPI_MCR_END_CFD_SHIFT)
63  #else
64  #define QSPI_MCR_END_CFD_LE		(1 << QSPI_MCR_END_CFD_SHIFT)
65  #endif
66  #define QSPI_MCR_DDR_EN_SHIFT		7
67  #define QSPI_MCR_DDR_EN_MASK		(1 << QSPI_MCR_DDR_EN_SHIFT)
68  #define QSPI_MCR_CLR_RXF_SHIFT		10
69  #define QSPI_MCR_CLR_RXF_MASK		(1 << QSPI_MCR_CLR_RXF_SHIFT)
70  #define QSPI_MCR_CLR_TXF_SHIFT		11
71  #define QSPI_MCR_CLR_TXF_MASK		(1 << QSPI_MCR_CLR_TXF_SHIFT)
72  #define QSPI_MCR_MDIS_SHIFT		14
73  #define QSPI_MCR_MDIS_MASK		(1 << QSPI_MCR_MDIS_SHIFT)
74  #define QSPI_MCR_RESERVED_SHIFT		16
75  #define QSPI_MCR_RESERVED_MASK		(0xf << QSPI_MCR_RESERVED_SHIFT)
76  #define QSPI_MCR_SWRSTHD_SHIFT		1
77  #define QSPI_MCR_SWRSTHD_MASK		(1 << QSPI_MCR_SWRSTHD_SHIFT)
78  #define QSPI_MCR_SWRSTSD_SHIFT		0
79  #define QSPI_MCR_SWRSTSD_MASK		(1 << QSPI_MCR_SWRSTSD_SHIFT)
80  
81  #define QSPI_SMPR_HSENA_SHIFT		0
82  #define QSPI_SMPR_HSENA_MASK		(1 << QSPI_SMPR_HSENA_SHIFT)
83  #define QSPI_SMPR_FSPHS_SHIFT		5
84  #define QSPI_SMPR_FSPHS_MASK		(1 << QSPI_SMPR_FSPHS_SHIFT)
85  #define QSPI_SMPR_FSDLY_SHIFT		6
86  #define QSPI_SMPR_FSDLY_MASK		(1 << QSPI_SMPR_FSDLY_SHIFT)
87  #define QSPI_SMPR_DDRSMP_SHIFT		16
88  #define QSPI_SMPR_DDRSMP_MASK		(7 << QSPI_SMPR_DDRSMP_SHIFT)
89  
90  #define QSPI_BUFXCR_INVALID_MSTRID	0xe
91  #define QSPI_BUF3CR_ALLMST_SHIFT	31
92  #define QSPI_BUF3CR_ALLMST_MASK		(1 << QSPI_BUF3CR_ALLMST_SHIFT)
93  #define QSPI_BUF3CR_ADATSZ_SHIFT	8
94  #define QSPI_BUF3CR_ADATSZ_MASK		(0xFF << QSPI_BUF3CR_ADATSZ_SHIFT)
95  
96  #define QSPI_BFGENCR_SEQID_SHIFT	12
97  #define QSPI_BFGENCR_SEQID_MASK		(0xf << QSPI_BFGENCR_SEQID_SHIFT)
98  #define QSPI_BFGENCR_PAR_EN_SHIFT	16
99  #define QSPI_BFGENCR_PAR_EN_MASK	(1 << QSPI_BFGENCR_PAR_EN_SHIFT)
100  
101  #define QSPI_RBSR_RDBFL_SHIFT		8
102  #define QSPI_RBSR_RDBFL_MASK		(0x3f << QSPI_RBSR_RDBFL_SHIFT)
103  
104  #define QSPI_RBCT_RXBRD_SHIFT		8
105  #define QSPI_RBCT_RXBRD_USEIPS		(1 << QSPI_RBCT_RXBRD_SHIFT)
106  
107  #define QSPI_SR_AHB_ACC_SHIFT		2
108  #define QSPI_SR_AHB_ACC_MASK		(1 << QSPI_SR_AHB_ACC_SHIFT)
109  #define QSPI_SR_IP_ACC_SHIFT		1
110  #define QSPI_SR_IP_ACC_MASK		(1 << QSPI_SR_IP_ACC_SHIFT)
111  #define QSPI_SR_BUSY_SHIFT		0
112  #define QSPI_SR_BUSY_MASK		(1 << QSPI_SR_BUSY_SHIFT)
113  
114  #define QSPI_LCKCR_LOCK			0x1
115  #define QSPI_LCKCR_UNLOCK		0x2
116  
117  #define LUT_KEY_VALUE			0x5af05af0
118  
119  #define OPRND0_SHIFT			0
120  #define OPRND0(x)			((x) << OPRND0_SHIFT)
121  #define PAD0_SHIFT			8
122  #define PAD0(x)				((x) << PAD0_SHIFT)
123  #define INSTR0_SHIFT			10
124  #define INSTR0(x)			((x) << INSTR0_SHIFT)
125  #define OPRND1_SHIFT			16
126  #define OPRND1(x)			((x) << OPRND1_SHIFT)
127  #define PAD1_SHIFT			24
128  #define PAD1(x)				((x) << PAD1_SHIFT)
129  #define INSTR1_SHIFT			26
130  #define INSTR1(x)			((x) << INSTR1_SHIFT)
131  
132  #define LUT_CMD				1
133  #define LUT_ADDR			2
134  #define LUT_DUMMY			3
135  #define LUT_READ			7
136  #define LUT_WRITE			8
137  
138  #define LUT_PAD1			0
139  #define LUT_PAD2			1
140  #define LUT_PAD4			2
141  
142  #define ADDR24BIT			0x18
143  #define ADDR32BIT			0x20
144  
145  #endif /* _FSL_QSPI_H_ */
146