1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
16 
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/TargetInstrInfo.h"
25 #include <array>
26 #include <cstdint>
27 
28 #define GET_INSTRINFO_HEADER
29 #include "ARMGenInstrInfo.inc"
30 
31 namespace llvm {
32 
33 class ARMBaseRegisterInfo;
34 class ARMSubtarget;
35 
36 class ARMBaseInstrInfo : public ARMGenInstrInfo {
37   const ARMSubtarget &Subtarget;
38 
39 protected:
40   // Can be only subclassed.
41   explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
42 
43   void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
44                                 unsigned LoadImmOpc, unsigned LoadOpc) const;
45 
46   /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
47   /// and \p DefIdx.
48   /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
49   /// the list is modeled as <Reg:SubReg, SubIdx>.
50   /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
51   /// two elements:
52   /// - %1:sub1, sub0
53   /// - %2<:0>, sub1
54   ///
55   /// \returns true if it is possible to build such an input sequence
56   /// with the pair \p MI, \p DefIdx. False otherwise.
57   ///
58   /// \pre MI.isRegSequenceLike().
59   bool getRegSequenceLikeInputs(
60       const MachineInstr &MI, unsigned DefIdx,
61       SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
62 
63   /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
64   /// and \p DefIdx.
65   /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
66   /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
67   /// - %1:sub1, sub0
68   ///
69   /// \returns true if it is possible to build such an input sequence
70   /// with the pair \p MI, \p DefIdx. False otherwise.
71   ///
72   /// \pre MI.isExtractSubregLike().
73   bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
74                                   RegSubRegPairAndIdx &InputReg) const override;
75 
76   /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
77   /// and \p DefIdx.
78   /// \p [out] BaseReg and \p [out] InsertedReg contain
79   /// the equivalent inputs of INSERT_SUBREG.
80   /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
81   /// - BaseReg: %0:sub0
82   /// - InsertedReg: %1:sub1, sub3
83   ///
84   /// \returns true if it is possible to build such an input sequence
85   /// with the pair \p MI, \p DefIdx. False otherwise.
86   ///
87   /// \pre MI.isInsertSubregLike().
88   bool
89   getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90                             RegSubRegPair &BaseReg,
91                             RegSubRegPairAndIdx &InsertedReg) const override;
92 
93   /// Commutes the operands in the given instruction.
94   /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
95   ///
96   /// Do not call this method for a non-commutable instruction or for
97   /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
98   /// Even though the instruction is commutable, the method may still
99   /// fail to commute the operands, null pointer is returned in such cases.
100   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
101                                        unsigned OpIdx1,
102                                        unsigned OpIdx2) const override;
103 
104 public:
105   // Return whether the target has an explicit NOP encoding.
106   bool hasNOP() const;
107 
108   // Return the non-pre/post incrementing version of 'Opc'. Return 0
109   // if there is not such an opcode.
110   virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
111 
112   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
113                                       MachineInstr &MI,
114                                       LiveVariables *LV) const override;
115 
116   virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
getSubtarget()117   const ARMSubtarget &getSubtarget() const { return Subtarget; }
118 
119   ScheduleHazardRecognizer *
120   CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
121                                const ScheduleDAG *DAG) const override;
122 
123   ScheduleHazardRecognizer *
124   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
125                                      const ScheduleDAG *DAG) const override;
126 
127   // Branch analysis.
128   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
129                      MachineBasicBlock *&FBB,
130                      SmallVectorImpl<MachineOperand> &Cond,
131                      bool AllowModify = false) const override;
132   unsigned removeBranch(MachineBasicBlock &MBB,
133                         int *BytesRemoved = nullptr) const override;
134   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
135                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
136                         const DebugLoc &DL,
137                         int *BytesAdded = nullptr) const override;
138 
139   bool
140   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
141 
142   // Predication support.
143   bool isPredicated(const MachineInstr &MI) const override;
144 
getPredicate(const MachineInstr & MI)145   ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
146     int PIdx = MI.findFirstPredOperandIdx();
147     return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
148                       : ARMCC::AL;
149   }
150 
151   bool PredicateInstruction(MachineInstr &MI,
152                             ArrayRef<MachineOperand> Pred) const override;
153 
154   bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
155                          ArrayRef<MachineOperand> Pred2) const override;
156 
157   bool DefinesPredicate(MachineInstr &MI,
158                         std::vector<MachineOperand> &Pred) const override;
159 
160   bool isPredicable(const MachineInstr &MI) const override;
161 
162   // CPSR defined in instruction
163   static bool isCPSRDefined(const MachineInstr &MI);
164   bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
165   bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
166 
167   // Load, scaled register offset
168   bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
169   // Load, scaled register offset, not plus LSL2
170   bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
171   // Minus reg for ldstso addr mode
172   bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
173   // Scaled register offset in address mode 2
174   bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
175   // Load multiple, base reg in list
176   bool isLDMBaseRegInList(const MachineInstr &MI) const;
177   // get LDM variable defs size
178   unsigned getLDMVariableDefsSize(const MachineInstr &MI) const;
179 
180   /// GetInstSize - Returns the size of the specified MachineInstr.
181   ///
182   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
183 
184   unsigned isLoadFromStackSlot(const MachineInstr &MI,
185                                int &FrameIndex) const override;
186   unsigned isStoreToStackSlot(const MachineInstr &MI,
187                               int &FrameIndex) const override;
188   unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
189                                      int &FrameIndex) const override;
190   unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
191                                     int &FrameIndex) const override;
192 
193   void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
194                   unsigned SrcReg, bool KillSrc,
195                   const ARMSubtarget &Subtarget) const;
196   void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
197                     unsigned DestReg, bool KillSrc,
198                     const ARMSubtarget &Subtarget) const;
199 
200   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
201                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
202                    bool KillSrc) const override;
203 
204   bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Src,
205                    const MachineOperand *&Dest) const override;
206 
207   void storeRegToStackSlot(MachineBasicBlock &MBB,
208                            MachineBasicBlock::iterator MBBI,
209                            unsigned SrcReg, bool isKill, int FrameIndex,
210                            const TargetRegisterClass *RC,
211                            const TargetRegisterInfo *TRI) const override;
212 
213   void loadRegFromStackSlot(MachineBasicBlock &MBB,
214                             MachineBasicBlock::iterator MBBI,
215                             unsigned DestReg, int FrameIndex,
216                             const TargetRegisterClass *RC,
217                             const TargetRegisterInfo *TRI) const override;
218 
219   bool expandPostRAPseudo(MachineInstr &MI) const override;
220 
221   bool shouldSink(const MachineInstr &MI) const override;
222 
223   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
224                      unsigned DestReg, unsigned SubIdx,
225                      const MachineInstr &Orig,
226                      const TargetRegisterInfo &TRI) const override;
227 
228   MachineInstr &
229   duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
230             const MachineInstr &Orig) const override;
231 
232   const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
233                                      unsigned SubIdx, unsigned State,
234                                      const TargetRegisterInfo *TRI) const;
235 
236   bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
237                         const MachineRegisterInfo *MRI) const override;
238 
239   /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
240   /// determine if two loads are loading from the same base address. It should
241   /// only return true if the base pointers are the same and the only
242   /// differences between the two addresses is the offset. It also returns the
243   /// offsets by reference.
244   bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
245                                int64_t &Offset2) const override;
246 
247   /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
248   /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
249   /// should be scheduled togther. On some targets if two loads are loading from
250   /// addresses in the same cache line, it's better if they are scheduled
251   /// together. This function takes two integers that represent the load offsets
252   /// from the common base address. It returns true if it decides it's desirable
253   /// to schedule the two loads together. "NumLoads" is the number of loads that
254   /// have already been scheduled after Load1.
255   bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
256                                int64_t Offset1, int64_t Offset2,
257                                unsigned NumLoads) const override;
258 
259   bool isSchedulingBoundary(const MachineInstr &MI,
260                             const MachineBasicBlock *MBB,
261                             const MachineFunction &MF) const override;
262 
263   bool isProfitableToIfCvt(MachineBasicBlock &MBB,
264                            unsigned NumCycles, unsigned ExtraPredCycles,
265                            BranchProbability Probability) const override;
266 
267   bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
268                            unsigned ExtraT, MachineBasicBlock &FMBB,
269                            unsigned NumF, unsigned ExtraF,
270                            BranchProbability Probability) const override;
271 
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,BranchProbability Probability)272   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
273                                  BranchProbability Probability) const override {
274     return NumCycles == 1;
275   }
276 
277   bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
278                                  MachineBasicBlock &FMBB) const override;
279 
280   /// analyzeCompare - For a comparison instruction, return the source registers
281   /// in SrcReg and SrcReg2 if having two register operands, and the value it
282   /// compares against in CmpValue. Return true if the comparison instruction
283   /// can be analyzed.
284   bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
285                       unsigned &SrcReg2, int &CmpMask,
286                       int &CmpValue) const override;
287 
288   /// optimizeCompareInstr - Convert the instruction to set the zero flag so
289   /// that we can remove a "comparison with zero"; Remove a redundant CMP
290   /// instruction if the flags can be updated in the same way by an earlier
291   /// instruction such as SUB.
292   bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
293                             unsigned SrcReg2, int CmpMask, int CmpValue,
294                             const MachineRegisterInfo *MRI) const override;
295 
296   bool analyzeSelect(const MachineInstr &MI,
297                      SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
298                      unsigned &FalseOp, bool &Optimizable) const override;
299 
300   MachineInstr *optimizeSelect(MachineInstr &MI,
301                                SmallPtrSetImpl<MachineInstr *> &SeenMIs,
302                                bool) const override;
303 
304   /// FoldImmediate - 'Reg' is known to be defined by a move immediate
305   /// instruction, try to fold the immediate into the use instruction.
306   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
307                      MachineRegisterInfo *MRI) const override;
308 
309   unsigned getNumMicroOps(const InstrItineraryData *ItinData,
310                           const MachineInstr &MI) const override;
311 
312   int getOperandLatency(const InstrItineraryData *ItinData,
313                         const MachineInstr &DefMI, unsigned DefIdx,
314                         const MachineInstr &UseMI,
315                         unsigned UseIdx) const override;
316   int getOperandLatency(const InstrItineraryData *ItinData,
317                         SDNode *DefNode, unsigned DefIdx,
318                         SDNode *UseNode, unsigned UseIdx) const override;
319 
320   /// VFP/NEON execution domains.
321   std::pair<uint16_t, uint16_t>
322   getExecutionDomain(const MachineInstr &MI) const override;
323   void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
324 
325   unsigned
326   getPartialRegUpdateClearance(const MachineInstr &, unsigned,
327                                const TargetRegisterInfo *) const override;
328   void breakPartialRegDependency(MachineInstr &, unsigned,
329                                  const TargetRegisterInfo *TRI) const override;
330 
331   /// Get the number of addresses by LDM or VLDM or zero for unknown.
332   unsigned getNumLDMAddresses(const MachineInstr &MI) const;
333 
334 private:
335   unsigned getInstBundleLength(const MachineInstr &MI) const;
336 
337   int getVLDMDefCycle(const InstrItineraryData *ItinData,
338                       const MCInstrDesc &DefMCID,
339                       unsigned DefClass,
340                       unsigned DefIdx, unsigned DefAlign) const;
341   int getLDMDefCycle(const InstrItineraryData *ItinData,
342                      const MCInstrDesc &DefMCID,
343                      unsigned DefClass,
344                      unsigned DefIdx, unsigned DefAlign) const;
345   int getVSTMUseCycle(const InstrItineraryData *ItinData,
346                       const MCInstrDesc &UseMCID,
347                       unsigned UseClass,
348                       unsigned UseIdx, unsigned UseAlign) const;
349   int getSTMUseCycle(const InstrItineraryData *ItinData,
350                      const MCInstrDesc &UseMCID,
351                      unsigned UseClass,
352                      unsigned UseIdx, unsigned UseAlign) const;
353   int getOperandLatency(const InstrItineraryData *ItinData,
354                         const MCInstrDesc &DefMCID,
355                         unsigned DefIdx, unsigned DefAlign,
356                         const MCInstrDesc &UseMCID,
357                         unsigned UseIdx, unsigned UseAlign) const;
358 
359   int getOperandLatencyImpl(const InstrItineraryData *ItinData,
360                             const MachineInstr &DefMI, unsigned DefIdx,
361                             const MCInstrDesc &DefMCID, unsigned DefAdj,
362                             const MachineOperand &DefMO, unsigned Reg,
363                             const MachineInstr &UseMI, unsigned UseIdx,
364                             const MCInstrDesc &UseMCID, unsigned UseAdj) const;
365 
366   unsigned getPredicationCost(const MachineInstr &MI) const override;
367 
368   unsigned getInstrLatency(const InstrItineraryData *ItinData,
369                            const MachineInstr &MI,
370                            unsigned *PredCost = nullptr) const override;
371 
372   int getInstrLatency(const InstrItineraryData *ItinData,
373                       SDNode *Node) const override;
374 
375   bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
376                              const MachineRegisterInfo *MRI,
377                              const MachineInstr &DefMI, unsigned DefIdx,
378                              const MachineInstr &UseMI,
379                              unsigned UseIdx) const override;
380   bool hasLowDefLatency(const TargetSchedModel &SchedModel,
381                         const MachineInstr &DefMI,
382                         unsigned DefIdx) const override;
383 
384   /// verifyInstruction - Perform target specific instruction verification.
385   bool verifyInstruction(const MachineInstr &MI,
386                          StringRef &ErrInfo) const override;
387 
388   virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
389 
390   void expandMEMCPY(MachineBasicBlock::iterator) const;
391 
392 private:
393   /// Modeling special VFP / NEON fp MLA / MLS hazards.
394 
395   /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
396   /// MLx table.
397   DenseMap<unsigned, unsigned> MLxEntryMap;
398 
399   /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
400   /// stalls when scheduled together with fp MLA / MLS opcodes.
401   SmallSet<unsigned, 16> MLxHazardOpcodes;
402 
403 public:
404   /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
405   /// instruction.
isFpMLxInstruction(unsigned Opcode)406   bool isFpMLxInstruction(unsigned Opcode) const {
407     return MLxEntryMap.count(Opcode);
408   }
409 
410   /// isFpMLxInstruction - This version also returns the multiply opcode and the
411   /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
412   /// the MLX instructions with an extra lane operand.
413   bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
414                           unsigned &AddSubOpc, bool &NegAcc,
415                           bool &HasLane) const;
416 
417   /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
418   /// will cause stalls when scheduled after (within 4-cycle window) a fp
419   /// MLA / MLS instruction.
canCauseFpMLxStall(unsigned Opcode)420   bool canCauseFpMLxStall(unsigned Opcode) const {
421     return MLxHazardOpcodes.count(Opcode);
422   }
423 
424   /// Returns true if the instruction has a shift by immediate that can be
425   /// executed in one cycle less.
426   bool isSwiftFastImmShift(const MachineInstr *MI) const;
427 
428   /// Returns predicate register associated with the given frame instruction.
getFramePred(const MachineInstr & MI)429   unsigned getFramePred(const MachineInstr &MI) const {
430     assert(isFrameInstr(MI));
431     // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
432     // - argument declared in the pattern:
433     // 0 - frame size
434     // 1 - arg of CALLSEQ_START/CALLSEQ_END
435     // 2 - predicate code (like ARMCC::AL)
436     // - added by predOps:
437     // 3 - predicate reg
438     return MI.getOperand(3).getReg();
439   }
440 };
441 
442 /// Get the operands corresponding to the given \p Pred value. By default, the
443 /// predicate register is assumed to be 0 (no register), but you can pass in a
444 /// \p PredReg if that is not the case.
445 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
446                                                     unsigned PredReg = 0) {
447   return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
448            MachineOperand::CreateReg(PredReg, false)}};
449 }
450 
451 /// Get the operand corresponding to the conditional code result. By default,
452 /// this is 0 (no register).
453 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
454   return MachineOperand::CreateReg(CCReg, false);
455 }
456 
457 /// Get the operand corresponding to the conditional code result for Thumb1.
458 /// This operand will always refer to CPSR and it will have the Define flag set.
459 /// You can optionally set the Dead flag by means of \p isDead.
460 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
461   return MachineOperand::CreateReg(ARM::CPSR,
462                                    /*Define*/ true, /*Implicit*/ false,
463                                    /*Kill*/ false, isDead);
464 }
465 
466 static inline
isUncondBranchOpcode(int Opc)467 bool isUncondBranchOpcode(int Opc) {
468   return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
469 }
470 
471 static inline
isCondBranchOpcode(int Opc)472 bool isCondBranchOpcode(int Opc) {
473   return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
474 }
475 
isJumpTableBranchOpcode(int Opc)476 static inline bool isJumpTableBranchOpcode(int Opc) {
477   return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
478          Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
479          Opc == ARM::t2BR_JT;
480 }
481 
482 static inline
isIndirectBranchOpcode(int Opc)483 bool isIndirectBranchOpcode(int Opc) {
484   return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
485 }
486 
isPopOpcode(int Opc)487 static inline bool isPopOpcode(int Opc) {
488   return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
489          Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
490          Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
491 }
492 
isPushOpcode(int Opc)493 static inline bool isPushOpcode(int Opc) {
494   return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
495          Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
496 }
497 
498 /// getInstrPredicate - If instruction is predicated, returns its predicate
499 /// condition, otherwise returns AL. It also returns the condition code
500 /// register by reference.
501 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
502 
503 unsigned getMatchingCondBranchOpcode(unsigned Opc);
504 
505 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
506 /// opcode of the SSA instruction representing the conditional MI.
507 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
508                                   MachineInstr *&MI,
509                                   const MachineRegisterInfo &MRI);
510 
511 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
512 /// the instruction is encoded with an 'S' bit is determined by the optional
513 /// CPSR def operand.
514 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
515 
516 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
517 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
518 /// code.
519 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
520                              MachineBasicBlock::iterator &MBBI,
521                              const DebugLoc &dl, unsigned DestReg,
522                              unsigned BaseReg, int NumBytes,
523                              ARMCC::CondCodes Pred, unsigned PredReg,
524                              const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
525 
526 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
527                             MachineBasicBlock::iterator &MBBI,
528                             const DebugLoc &dl, unsigned DestReg,
529                             unsigned BaseReg, int NumBytes,
530                             ARMCC::CondCodes Pred, unsigned PredReg,
531                             const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
532 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
533                                MachineBasicBlock::iterator &MBBI,
534                                const DebugLoc &dl, unsigned DestReg,
535                                unsigned BaseReg, int NumBytes,
536                                const TargetInstrInfo &TII,
537                                const ARMBaseRegisterInfo &MRI,
538                                unsigned MIFlags = 0);
539 
540 /// Tries to add registers to the reglist of a given base-updating
541 /// push/pop instruction to adjust the stack by an additional
542 /// NumBytes. This can save a few bytes per function in code-size, but
543 /// obviously generates more memory traffic. As such, it only takes
544 /// effect in functions being optimised for size.
545 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
546                                 MachineFunction &MF, MachineInstr *MI,
547                                 unsigned NumBytes);
548 
549 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
550 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
551 /// offset could not be handled directly in MI, and return the left-over
552 /// portion by reference.
553 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
554                           unsigned FrameReg, int &Offset,
555                           const ARMBaseInstrInfo &TII);
556 
557 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
558                          unsigned FrameReg, int &Offset,
559                          const ARMBaseInstrInfo &TII);
560 
561 } // end namespace llvm
562 
563 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
564