1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Gateworks Corporation
4 *
5 * Author: Tim Harvey <tharvey@gateworks.com>
6 */
7
8 #include <linux/errno.h>
9 #include <common.h>
10 #include <i2c.h>
11 #include <linux/ctype.h>
12
13 #include "ventana_eeprom.h"
14 #include "gsc.h"
15
16 /*
17 * The Gateworks System Controller will fail to ACK a master transaction if
18 * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
19 * When this does occur, it will never be busy long enough to fail more than
20 * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
21 * 3 retries.
22 */
gsc_i2c_read(uchar chip,uint addr,int alen,uchar * buf,int len)23 int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
24 {
25 int retry = 3;
26 int n = 0;
27 int ret;
28
29 while (n++ < retry) {
30 ret = i2c_read(chip, addr, alen, buf, len);
31 if (!ret)
32 break;
33 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
34 n, ret);
35 if (ret != -ENODEV)
36 break;
37 mdelay(10);
38 }
39 return ret;
40 }
41
gsc_i2c_write(uchar chip,uint addr,int alen,uchar * buf,int len)42 int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
43 {
44 int retry = 3;
45 int n = 0;
46 int ret;
47
48 while (n++ < retry) {
49 ret = i2c_write(chip, addr, alen, buf, len);
50 if (!ret)
51 break;
52 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
53 n, ret);
54 if (ret != -ENODEV)
55 break;
56 mdelay(10);
57 }
58 mdelay(100);
59 return ret;
60 }
61
read_hwmon(const char * name,uint reg,uint size)62 static void read_hwmon(const char *name, uint reg, uint size)
63 {
64 unsigned char buf[3];
65 uint ui;
66
67 printf("%-8s:", name);
68 memset(buf, 0, sizeof(buf));
69 if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
70 puts("fRD\n");
71 } else {
72 ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
73 if (reg == GSC_HWMON_TEMP && ui > 0x8000)
74 ui -= 0xffff;
75 if (ui == 0xffffff)
76 puts("invalid\n");
77 else
78 printf("%d\n", ui);
79 }
80 }
81
gsc_info(int verbose)82 int gsc_info(int verbose)
83 {
84 unsigned char buf[16];
85
86 i2c_set_bus_num(0);
87 if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
88 return CMD_RET_FAILURE;
89
90 printf("GSC: v%d", buf[GSC_SC_FWVER]);
91 printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8);
92 printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN))
93 ? "en" : "dis");
94 if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) {
95 buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG);
96 puts(" WDT_RESET");
97 gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
98 &buf[GSC_SC_STATUS], 1);
99 }
100 if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) {
101 int ui = buf[0] | buf[1]<<8;
102 if (ui > 0x8000)
103 ui -= 0xffff;
104 printf(" board temp at %dC", ui / 10);
105 }
106 puts("\n");
107 if (!verbose)
108 return CMD_RET_SUCCESS;
109
110 read_hwmon("Temp", GSC_HWMON_TEMP, 2);
111 read_hwmon("VIN", GSC_HWMON_VIN, 3);
112 read_hwmon("VBATT", GSC_HWMON_VBATT, 3);
113 read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3);
114 read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3);
115 read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
116 read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
117 read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3);
118 read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3);
119 if (strncasecmp((const char*) ventana_info.model, "GW553", 5))
120 read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
121 read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3);
122 read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3);
123 switch (ventana_info.model[3]) {
124 case '1': /* GW51xx */
125 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
126 break;
127 case '2': /* GW52xx */
128 break;
129 case '3': /* GW53xx */
130 read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */
131 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
132 break;
133 case '4': /* GW54xx */
134 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
135 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
136 break;
137 case '5': /* GW55xx */
138 break;
139 case '6': /* GW560x */
140 read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3);
141 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
142 break;
143 }
144 return 0;
145 }
146
147 /*
148 * The Gateworks System Controller implements a boot
149 * watchdog (always enabled) as a workaround for IMX6 boot related
150 * errata such as:
151 * ERR005768 - no fix scheduled
152 * ERR006282 - fixed in silicon r1.2
153 * ERR007117 - fixed in silicon r1.3
154 * ERR007220 - fixed in silicon r1.3
155 * ERR007926 - no fix scheduled
156 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
157 *
158 * Disable the boot watchdog
159 */
gsc_boot_wd_disable(void)160 int gsc_boot_wd_disable(void)
161 {
162 u8 reg;
163
164 i2c_set_bus_num(CONFIG_I2C_GSC);
165 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
166 reg |= (1 << GSC_SC_CTRL1_WDDIS);
167 if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
168 return 0;
169 }
170 puts("Error: could not disable GSC Watchdog\n");
171 return 1;
172 }
173
174 #if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD)
do_gsc_sleep(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])175 static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
176 char * const argv[])
177 {
178 unsigned char reg;
179 unsigned long secs = 0;
180
181 if (argc < 2)
182 return CMD_RET_USAGE;
183
184 secs = simple_strtoul(argv[1], NULL, 10);
185 printf("GSC Sleeping for %ld seconds\n", secs);
186
187 i2c_set_bus_num(0);
188 reg = (secs >> 24) & 0xff;
189 if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1))
190 goto error;
191 reg = (secs >> 16) & 0xff;
192 if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, ®, 1))
193 goto error;
194 reg = (secs >> 8) & 0xff;
195 if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, ®, 1))
196 goto error;
197 reg = secs & 0xff;
198 if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, ®, 1))
199 goto error;
200 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
201 goto error;
202 reg |= (1 << 2);
203 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
204 goto error;
205 reg &= ~(1 << 2);
206 reg |= 0x3;
207 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
208 goto error;
209
210 return CMD_RET_SUCCESS;
211
212 error:
213 printf("i2c error\n");
214 return CMD_RET_FAILURE;
215 }
216
do_gsc_wd(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])217 static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
218 {
219 unsigned char reg;
220
221 if (argc < 2)
222 return CMD_RET_USAGE;
223
224 if (strcasecmp(argv[1], "enable") == 0) {
225 int timeout = 0;
226
227 if (argc > 2)
228 timeout = simple_strtoul(argv[2], NULL, 10);
229 i2c_set_bus_num(0);
230 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
231 return CMD_RET_FAILURE;
232 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
233 if (timeout == 60)
234 reg |= (1 << GSC_SC_CTRL1_WDTIME);
235 else
236 timeout = 30;
237 reg |= (1 << GSC_SC_CTRL1_WDEN);
238 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
239 return CMD_RET_FAILURE;
240 printf("GSC Watchdog enabled with timeout=%d seconds\n",
241 timeout);
242 } else if (strcasecmp(argv[1], "disable") == 0) {
243 i2c_set_bus_num(0);
244 if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
245 return CMD_RET_FAILURE;
246 reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
247 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
248 return CMD_RET_FAILURE;
249 printf("GSC Watchdog disabled\n");
250 } else {
251 return CMD_RET_USAGE;
252 }
253 return CMD_RET_SUCCESS;
254 }
255
do_gsc(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])256 static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
257 {
258 if (argc < 2)
259 return gsc_info(1);
260
261 if (strcasecmp(argv[1], "wd") == 0)
262 return do_gsc_wd(cmdtp, flag, --argc, ++argv);
263 else if (strcasecmp(argv[1], "sleep") == 0)
264 return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
265
266 return CMD_RET_USAGE;
267 }
268
269 U_BOOT_CMD(
270 gsc, 4, 1, do_gsc, "GSC configuration",
271 "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
272 );
273
274 #endif /* CONFIG_CMD_GSC */
275