1 /*
2 * Copyright 2003 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "main/mtypes.h"
27 #include "main/blit.h"
28 #include "main/context.h"
29 #include "main/enums.h"
30 #include "main/fbobject.h"
31
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_fbo.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_mipmap_tree.h"
39
40 #define FILE_DEBUG_FLAG DEBUG_BLIT
41
42 static void
43 intel_miptree_set_alpha_to_one(struct brw_context *brw,
44 struct intel_mipmap_tree *mt,
45 int x, int y, int width, int height);
46
translate_raster_op(GLenum logicop)47 static GLuint translate_raster_op(GLenum logicop)
48 {
49 switch(logicop) {
50 case GL_CLEAR: return 0x00;
51 case GL_AND: return 0x88;
52 case GL_AND_REVERSE: return 0x44;
53 case GL_COPY: return 0xCC;
54 case GL_AND_INVERTED: return 0x22;
55 case GL_NOOP: return 0xAA;
56 case GL_XOR: return 0x66;
57 case GL_OR: return 0xEE;
58 case GL_NOR: return 0x11;
59 case GL_EQUIV: return 0x99;
60 case GL_INVERT: return 0x55;
61 case GL_OR_REVERSE: return 0xDD;
62 case GL_COPY_INVERTED: return 0x33;
63 case GL_OR_INVERTED: return 0xBB;
64 case GL_NAND: return 0x77;
65 case GL_SET: return 0xFF;
66 default: return 0;
67 }
68 }
69
70 static uint32_t
br13_for_cpp(int cpp)71 br13_for_cpp(int cpp)
72 {
73 switch (cpp) {
74 case 16:
75 return BR13_32323232;
76 case 8:
77 return BR13_16161616;
78 case 4:
79 return BR13_8888;
80 case 2:
81 return BR13_565;
82 case 1:
83 return BR13_8;
84 default:
85 unreachable("not reached");
86 }
87 }
88
89 /**
90 * Emits the packet for switching the blitter from X to Y tiled or back.
91 *
92 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
93 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
94 * part of the power context, not a render context, and if the batchbuffer was
95 * to get flushed between setting and blitting, or blitting and restoring, our
96 * tiling state would leak into other unsuspecting applications (like the X
97 * server).
98 */
99 static uint32_t *
set_blitter_tiling(struct brw_context * brw,bool dst_y_tiled,bool src_y_tiled,uint32_t * __map)100 set_blitter_tiling(struct brw_context *brw,
101 bool dst_y_tiled, bool src_y_tiled,
102 uint32_t *__map)
103 {
104 const struct gen_device_info *devinfo = &brw->screen->devinfo;
105 const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4;
106 assert(devinfo->gen >= 6);
107
108 /* Idle the blitter before we update how tiling is interpreted. */
109 OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2));
110 OUT_BATCH(0);
111 OUT_BATCH(0);
112 OUT_BATCH(0);
113 if (n_dwords == 5)
114 OUT_BATCH(0);
115
116 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
117 OUT_BATCH(BCS_SWCTRL);
118 OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
119 (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
120 (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
121 return __map;
122 }
123 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
124
125 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
126 unsigned set_tiling_batch_size = 0; \
127 if (dst_y_tiled || src_y_tiled) { \
128 if (devinfo->gen >= 8) \
129 set_tiling_batch_size = 16; \
130 else \
131 set_tiling_batch_size = 14; \
132 } \
133 BEGIN_BATCH_BLT(n + set_tiling_batch_size); \
134 if (dst_y_tiled || src_y_tiled) \
135 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
136
137 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \
138 if (dst_y_tiled || src_y_tiled) \
139 SET_BLITTER_TILING(brw, false, false); \
140 ADVANCE_BATCH()
141
142 static int
blt_pitch(struct intel_mipmap_tree * mt)143 blt_pitch(struct intel_mipmap_tree *mt)
144 {
145 int pitch = mt->surf.row_pitch;
146 if (mt->surf.tiling != ISL_TILING_LINEAR)
147 pitch /= 4;
148 return pitch;
149 }
150
151 bool
intel_miptree_blit_compatible_formats(mesa_format src,mesa_format dst)152 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
153 {
154 /* The BLT doesn't handle sRGB conversion */
155 assert(src == _mesa_get_srgb_format_linear(src));
156 assert(dst == _mesa_get_srgb_format_linear(dst));
157
158 /* No swizzle or format conversions possible, except... */
159 if (src == dst)
160 return true;
161
162 /* ...we can either discard the alpha channel when going from A->X,
163 * or we can fill the alpha channel with 0xff when going from X->A
164 */
165 if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
166 return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
167 dst == MESA_FORMAT_B8G8R8X8_UNORM);
168
169 if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
170 return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
171 dst == MESA_FORMAT_R8G8B8X8_UNORM);
172
173 /* We can also discard alpha when going from A2->X2 for 2 bit alpha,
174 * however we can't fill the alpha channel with two 1 bits when going
175 * from X2->A2, because intel_miptree_set_alpha_to_one() is not yet
176 * ready for this / can only handle 8 bit alpha.
177 */
178 if (src == MESA_FORMAT_B10G10R10A2_UNORM)
179 return (dst == MESA_FORMAT_B10G10R10A2_UNORM ||
180 dst == MESA_FORMAT_B10G10R10X2_UNORM);
181
182 if (src == MESA_FORMAT_R10G10B10A2_UNORM)
183 return (dst == MESA_FORMAT_R10G10B10A2_UNORM ||
184 dst == MESA_FORMAT_R10G10B10X2_UNORM);
185
186 return false;
187 }
188
189 static void
get_blit_intratile_offset_el(const struct brw_context * brw,struct intel_mipmap_tree * mt,uint32_t total_x_offset_el,uint32_t total_y_offset_el,uint32_t * base_address_offset,uint32_t * x_offset_el,uint32_t * y_offset_el)190 get_blit_intratile_offset_el(const struct brw_context *brw,
191 struct intel_mipmap_tree *mt,
192 uint32_t total_x_offset_el,
193 uint32_t total_y_offset_el,
194 uint32_t *base_address_offset,
195 uint32_t *x_offset_el,
196 uint32_t *y_offset_el)
197 {
198 isl_tiling_get_intratile_offset_el(mt->surf.tiling,
199 mt->cpp * 8, mt->surf.row_pitch,
200 total_x_offset_el, total_y_offset_el,
201 base_address_offset,
202 x_offset_el, y_offset_el);
203 if (mt->surf.tiling == ISL_TILING_LINEAR) {
204 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
205 *
206 * "Base address of the destination surface: X=0, Y=0. Lower 32bits
207 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
208 * enabled), this address must be 4KB-aligned. When Tiling is not
209 * enabled, this address should be CL (64byte) aligned."
210 *
211 * The offsets we get from ISL in the tiled case are already aligned.
212 * In the linear case, we need to do some of our own aligning.
213 */
214 uint32_t delta = *base_address_offset & 63;
215 assert(delta % mt->cpp == 0);
216 *base_address_offset -= delta;
217 *x_offset_el += delta / mt->cpp;
218 } else {
219 assert(*base_address_offset % 4096 == 0);
220 }
221 }
222
223 static bool
emit_miptree_blit(struct brw_context * brw,struct intel_mipmap_tree * src_mt,uint32_t src_x,uint32_t src_y,struct intel_mipmap_tree * dst_mt,uint32_t dst_x,uint32_t dst_y,uint32_t width,uint32_t height,bool reverse,GLenum logicop)224 emit_miptree_blit(struct brw_context *brw,
225 struct intel_mipmap_tree *src_mt,
226 uint32_t src_x, uint32_t src_y,
227 struct intel_mipmap_tree *dst_mt,
228 uint32_t dst_x, uint32_t dst_y,
229 uint32_t width, uint32_t height,
230 bool reverse, GLenum logicop)
231 {
232 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
233 * Data Size Limitations):
234 *
235 * The BLT engine is capable of transferring very large quantities of
236 * graphics data. Any graphics data read from and written to the
237 * destination is permitted to represent a number of pixels that
238 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
239 * at the destination. The maximum number of pixels that may be
240 * represented per scan line’s worth of graphics data depends on the
241 * color depth.
242 *
243 * The blitter's pitch is a signed 16-bit integer, but measured in bytes
244 * for linear surfaces and DWords for tiled surfaces. So the maximum
245 * pitch is 32k linear and 128k tiled.
246 */
247 if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
248 perf_debug("Falling back due to >= 32k/128k pitch\n");
249 return false;
250 }
251
252 /* We need to split the blit into chunks that each fit within the blitter's
253 * restrictions. We can't use a chunk size of 32768 because we need to
254 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
255 * a nice round power of two, big enough that performance won't suffer, and
256 * small enough to guarantee everything fits.
257 */
258 const uint32_t max_chunk_size = 16384;
259
260 for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
261 for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
262 const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
263 const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
264
265 uint32_t src_offset, src_tile_x, src_tile_y;
266 get_blit_intratile_offset_el(brw, src_mt,
267 src_x + chunk_x, src_y + chunk_y,
268 &src_offset, &src_tile_x, &src_tile_y);
269
270 uint32_t dst_offset, dst_tile_x, dst_tile_y;
271 get_blit_intratile_offset_el(brw, dst_mt,
272 dst_x + chunk_x, dst_y + chunk_y,
273 &dst_offset, &dst_tile_x, &dst_tile_y);
274
275 if (!intelEmitCopyBlit(brw,
276 src_mt->cpp,
277 reverse ? -src_mt->surf.row_pitch :
278 src_mt->surf.row_pitch,
279 src_mt->bo, src_mt->offset + src_offset,
280 src_mt->surf.tiling,
281 dst_mt->surf.row_pitch,
282 dst_mt->bo, dst_mt->offset + dst_offset,
283 dst_mt->surf.tiling,
284 src_tile_x, src_tile_y,
285 dst_tile_x, dst_tile_y,
286 chunk_w, chunk_h,
287 logicop)) {
288 /* If this is ever going to fail, it will fail on the first chunk */
289 assert(chunk_x == 0 && chunk_y == 0);
290 return false;
291 }
292 }
293 }
294
295 return true;
296 }
297
298 /**
299 * Implements a rectangular block transfer (blit) of pixels between two
300 * miptrees.
301 *
302 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
303 * but limited, pitches and sizes allowed.
304 *
305 * The src/dst coordinates are relative to the given level/slice of the
306 * miptree.
307 *
308 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
309 * will be inverted (including scanline order) when copying. This is common
310 * in GL when copying between window system and user-created
311 * renderbuffers/textures.
312 */
313 bool
intel_miptree_blit(struct brw_context * brw,struct intel_mipmap_tree * src_mt,int src_level,int src_slice,uint32_t src_x,uint32_t src_y,bool src_flip,struct intel_mipmap_tree * dst_mt,int dst_level,int dst_slice,uint32_t dst_x,uint32_t dst_y,bool dst_flip,uint32_t width,uint32_t height,GLenum logicop)314 intel_miptree_blit(struct brw_context *brw,
315 struct intel_mipmap_tree *src_mt,
316 int src_level, int src_slice,
317 uint32_t src_x, uint32_t src_y, bool src_flip,
318 struct intel_mipmap_tree *dst_mt,
319 int dst_level, int dst_slice,
320 uint32_t dst_x, uint32_t dst_y, bool dst_flip,
321 uint32_t width, uint32_t height,
322 GLenum logicop)
323 {
324 /* The blitter doesn't understand multisampling at all. */
325 if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
326 return false;
327
328 /* No sRGB decode or encode is done by the hardware blitter, which is
329 * consistent with what we want in many callers (glCopyTexSubImage(),
330 * texture validation, etc.).
331 */
332 mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
333 mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
334
335 /* The blitter doesn't support doing any format conversions. We do also
336 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
337 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
338 * channel to 1.0 at the end. Also trivially ARGB2101010 to XRGB2101010,
339 * but not XRGB2101010 to ARGB2101010 yet.
340 */
341 if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
342 perf_debug("%s: Can't use hardware blitter from %s to %s, "
343 "falling back.\n", __func__,
344 _mesa_get_format_name(src_format),
345 _mesa_get_format_name(dst_format));
346 return false;
347 }
348
349 /* The blitter has no idea about HiZ or fast color clears, so we need to
350 * resolve the miptrees before we do anything.
351 */
352 intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
353 intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
354
355 if (src_flip) {
356 const unsigned h0 = src_mt->surf.phys_level0_sa.height;
357 src_y = minify(h0, src_level - src_mt->first_level) - src_y - height;
358 }
359
360 if (dst_flip) {
361 const unsigned h0 = dst_mt->surf.phys_level0_sa.height;
362 dst_y = minify(h0, dst_level - dst_mt->first_level) - dst_y - height;
363 }
364
365 uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
366 intel_miptree_get_image_offset(src_mt, src_level, src_slice,
367 &src_image_x, &src_image_y);
368 intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
369 &dst_image_x, &dst_image_y);
370 src_x += src_image_x;
371 src_y += src_image_y;
372 dst_x += dst_image_x;
373 dst_y += dst_image_y;
374
375 if (!emit_miptree_blit(brw, src_mt, src_x, src_y,
376 dst_mt, dst_x, dst_y, width, height,
377 src_flip != dst_flip, logicop)) {
378 return false;
379 }
380
381 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
382 if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
383 _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
384 intel_miptree_set_alpha_to_one(brw, dst_mt,
385 dst_x, dst_y,
386 width, height);
387 }
388
389 return true;
390 }
391
392 bool
intel_miptree_copy(struct brw_context * brw,struct intel_mipmap_tree * src_mt,int src_level,int src_slice,uint32_t src_x,uint32_t src_y,struct intel_mipmap_tree * dst_mt,int dst_level,int dst_slice,uint32_t dst_x,uint32_t dst_y,uint32_t src_width,uint32_t src_height)393 intel_miptree_copy(struct brw_context *brw,
394 struct intel_mipmap_tree *src_mt,
395 int src_level, int src_slice,
396 uint32_t src_x, uint32_t src_y,
397 struct intel_mipmap_tree *dst_mt,
398 int dst_level, int dst_slice,
399 uint32_t dst_x, uint32_t dst_y,
400 uint32_t src_width, uint32_t src_height)
401 {
402 /* The blitter doesn't understand multisampling at all. */
403 if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
404 return false;
405
406 if (src_mt->format == MESA_FORMAT_S_UINT8)
407 return false;
408
409 /* The blitter has no idea about HiZ or fast color clears, so we need to
410 * resolve the miptrees before we do anything.
411 */
412 intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
413 intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
414
415 uint32_t src_image_x, src_image_y;
416 intel_miptree_get_image_offset(src_mt, src_level, src_slice,
417 &src_image_x, &src_image_y);
418
419 if (_mesa_is_format_compressed(src_mt->format)) {
420 GLuint bw, bh;
421 _mesa_get_format_block_size(src_mt->format, &bw, &bh);
422
423 /* Compressed textures need not have dimensions that are a multiple of
424 * the block size. Rectangles in compressed textures do need to be a
425 * multiple of the block size. The one exception is that the right and
426 * bottom edges may be at the right or bottom edge of the miplevel even
427 * if it's not aligned.
428 */
429 assert(src_x % bw == 0);
430 assert(src_y % bh == 0);
431
432 assert(src_width % bw == 0 ||
433 src_x + src_width ==
434 minify(src_mt->surf.logical_level0_px.width, src_level));
435 assert(src_height % bh == 0 ||
436 src_y + src_height ==
437 minify(src_mt->surf.logical_level0_px.height, src_level));
438
439 src_x /= (int)bw;
440 src_y /= (int)bh;
441 src_width = DIV_ROUND_UP(src_width, (int)bw);
442 src_height = DIV_ROUND_UP(src_height, (int)bh);
443 }
444 src_x += src_image_x;
445 src_y += src_image_y;
446
447 uint32_t dst_image_x, dst_image_y;
448 intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
449 &dst_image_x, &dst_image_y);
450
451 if (_mesa_is_format_compressed(dst_mt->format)) {
452 GLuint bw, bh;
453 _mesa_get_format_block_size(dst_mt->format, &bw, &bh);
454
455 assert(dst_x % bw == 0);
456 assert(dst_y % bh == 0);
457
458 dst_x /= (int)bw;
459 dst_y /= (int)bh;
460 }
461 dst_x += dst_image_x;
462 dst_y += dst_image_y;
463
464 return emit_miptree_blit(brw, src_mt, src_x, src_y,
465 dst_mt, dst_x, dst_y,
466 src_width, src_height, false, GL_COPY);
467 }
468
469 static bool
alignment_valid(struct brw_context * brw,unsigned offset,enum isl_tiling tiling)470 alignment_valid(struct brw_context *brw, unsigned offset,
471 enum isl_tiling tiling)
472 {
473 const struct gen_device_info *devinfo = &brw->screen->devinfo;
474
475 /* Tiled buffers must be page-aligned (4K). */
476 if (tiling != ISL_TILING_LINEAR)
477 return (offset & 4095) == 0;
478
479 /* On Gen8+, linear buffers must be cacheline-aligned. */
480 if (devinfo->gen >= 8)
481 return (offset & 63) == 0;
482
483 return true;
484 }
485
486 static uint32_t
xy_blit_cmd(enum isl_tiling src_tiling,enum isl_tiling dst_tiling,uint32_t cpp)487 xy_blit_cmd(enum isl_tiling src_tiling, enum isl_tiling dst_tiling,
488 uint32_t cpp)
489 {
490 uint32_t CMD = 0;
491
492 assert(cpp <= 4);
493 switch (cpp) {
494 case 1:
495 case 2:
496 CMD = XY_SRC_COPY_BLT_CMD;
497 break;
498 case 4:
499 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
500 break;
501 default:
502 unreachable("not reached");
503 }
504
505 if (dst_tiling != ISL_TILING_LINEAR)
506 CMD |= XY_DST_TILED;
507
508 if (src_tiling != ISL_TILING_LINEAR)
509 CMD |= XY_SRC_TILED;
510
511 return CMD;
512 }
513
514 /* Copy BitBlt
515 */
516 bool
intelEmitCopyBlit(struct brw_context * brw,GLuint cpp,int32_t src_pitch,struct brw_bo * src_buffer,GLuint src_offset,enum isl_tiling src_tiling,int32_t dst_pitch,struct brw_bo * dst_buffer,GLuint dst_offset,enum isl_tiling dst_tiling,GLshort src_x,GLshort src_y,GLshort dst_x,GLshort dst_y,GLshort w,GLshort h,GLenum logic_op)517 intelEmitCopyBlit(struct brw_context *brw,
518 GLuint cpp,
519 int32_t src_pitch,
520 struct brw_bo *src_buffer,
521 GLuint src_offset,
522 enum isl_tiling src_tiling,
523 int32_t dst_pitch,
524 struct brw_bo *dst_buffer,
525 GLuint dst_offset,
526 enum isl_tiling dst_tiling,
527 GLshort src_x, GLshort src_y,
528 GLshort dst_x, GLshort dst_y,
529 GLshort w, GLshort h,
530 GLenum logic_op)
531 {
532 const struct gen_device_info *devinfo = &brw->screen->devinfo;
533 GLuint CMD, BR13;
534 int dst_y2 = dst_y + h;
535 int dst_x2 = dst_x + w;
536 bool dst_y_tiled = dst_tiling == ISL_TILING_Y0;
537 bool src_y_tiled = src_tiling == ISL_TILING_Y0;
538 uint32_t src_tile_w, src_tile_h;
539 uint32_t dst_tile_w, dst_tile_h;
540
541 if ((dst_y_tiled || src_y_tiled) && devinfo->gen < 6)
542 return false;
543
544 const unsigned bo_sizes = dst_buffer->size + src_buffer->size;
545
546 /* do space check before going any further */
547 if (!brw_batch_has_aperture_space(brw, bo_sizes))
548 intel_batchbuffer_flush(brw);
549
550 if (!brw_batch_has_aperture_space(brw, bo_sizes))
551 return false;
552
553 unsigned length = devinfo->gen >= 8 ? 10 : 8;
554
555 intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
556 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
557 __func__,
558 src_buffer, src_pitch, src_offset, src_x, src_y,
559 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
560
561 intel_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h);
562 intel_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h);
563
564 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
565 * (X direction width of the Tile). This is ensured while allocating the
566 * buffer object.
567 */
568 assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0);
569 assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0);
570
571 /* For big formats (such as floating point), do the copy using 16 or
572 * 32bpp and multiply the coordinates.
573 */
574 if (cpp > 4) {
575 if (cpp % 4 == 2) {
576 dst_x *= cpp / 2;
577 dst_x2 *= cpp / 2;
578 src_x *= cpp / 2;
579 cpp = 2;
580 } else {
581 assert(cpp % 4 == 0);
582 dst_x *= cpp / 4;
583 dst_x2 *= cpp / 4;
584 src_x *= cpp / 4;
585 cpp = 4;
586 }
587 }
588
589 if (!alignment_valid(brw, dst_offset, dst_tiling))
590 return false;
591 if (!alignment_valid(brw, src_offset, src_tiling))
592 return false;
593
594 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
595 * the low bits. Offsets must be naturally aligned.
596 */
597 if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
598 dst_pitch % 4 != 0 || dst_offset % cpp != 0)
599 return false;
600
601 assert(cpp <= 4);
602 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
603
604 CMD = xy_blit_cmd(src_tiling, dst_tiling, cpp);
605
606 /* For tiled source and destination, pitch value should be specified
607 * as a number of Dwords.
608 */
609 if (dst_tiling != ISL_TILING_LINEAR)
610 dst_pitch /= 4;
611
612 if (src_tiling != ISL_TILING_LINEAR)
613 src_pitch /= 4;
614
615 if (dst_y2 <= dst_y || dst_x2 <= dst_x)
616 return true;
617
618 assert(dst_x < dst_x2);
619 assert(dst_y < dst_y2);
620
621 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
622 OUT_BATCH(CMD | (length - 2));
623 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
624 OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
625 OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
626 if (devinfo->gen >= 8) {
627 OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
628 } else {
629 OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
630 }
631 OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
632 OUT_BATCH((uint16_t)src_pitch);
633 if (devinfo->gen >= 8) {
634 OUT_RELOC64(src_buffer, 0, src_offset);
635 } else {
636 OUT_RELOC(src_buffer, 0, src_offset);
637 }
638
639 ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
640
641 brw_emit_mi_flush(brw);
642
643 return true;
644 }
645
646 bool
intelEmitImmediateColorExpandBlit(struct brw_context * brw,GLuint cpp,GLubyte * src_bits,GLuint src_size,GLuint fg_color,GLshort dst_pitch,struct brw_bo * dst_buffer,GLuint dst_offset,enum isl_tiling dst_tiling,GLshort x,GLshort y,GLshort w,GLshort h,GLenum logic_op)647 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
648 GLuint cpp,
649 GLubyte *src_bits, GLuint src_size,
650 GLuint fg_color,
651 GLshort dst_pitch,
652 struct brw_bo *dst_buffer,
653 GLuint dst_offset,
654 enum isl_tiling dst_tiling,
655 GLshort x, GLshort y,
656 GLshort w, GLshort h,
657 GLenum logic_op)
658 {
659 const struct gen_device_info *devinfo = &brw->screen->devinfo;
660 int dwords = ALIGN(src_size, 8) / 4;
661 uint32_t opcode, br13, blit_cmd;
662
663 if (dst_tiling != ISL_TILING_LINEAR) {
664 if (dst_offset & 4095)
665 return false;
666 if (dst_tiling == ISL_TILING_Y0)
667 return false;
668 }
669
670 assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
671 assert(dst_pitch > 0);
672
673 if (w < 0 || h < 0)
674 return true;
675
676 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
677 __func__,
678 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
679
680 unsigned xy_setup_blt_length = devinfo->gen >= 8 ? 10 : 8;
681 intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
682 (3 * 4) + dwords * 4, BLT_RING);
683
684 opcode = XY_SETUP_BLT_CMD;
685 if (cpp == 4)
686 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
687 if (dst_tiling != ISL_TILING_LINEAR) {
688 opcode |= XY_DST_TILED;
689 dst_pitch /= 4;
690 }
691
692 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
693 br13 |= br13_for_cpp(cpp);
694
695 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
696 if (dst_tiling != ISL_TILING_LINEAR)
697 blit_cmd |= XY_DST_TILED;
698
699 BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
700 OUT_BATCH(opcode | (xy_setup_blt_length - 2));
701 OUT_BATCH(br13);
702 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
703 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
704 if (devinfo->gen >= 8) {
705 OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
706 } else {
707 OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
708 }
709 OUT_BATCH(0); /* bg */
710 OUT_BATCH(fg_color); /* fg */
711 OUT_BATCH(0); /* pattern base addr */
712 if (devinfo->gen >= 8)
713 OUT_BATCH(0);
714
715 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
716 OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
717 OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
718 ADVANCE_BATCH();
719
720 intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
721
722 brw_emit_mi_flush(brw);
723
724 return true;
725 }
726
727 /* We don't have a memmove-type blit like some other hardware, so we'll do a
728 * rectangular blit covering a large space, then emit 1-scanline blit at the
729 * end to cover the last if we need.
730 */
731 void
intel_emit_linear_blit(struct brw_context * brw,struct brw_bo * dst_bo,unsigned int dst_offset,struct brw_bo * src_bo,unsigned int src_offset,unsigned int size)732 intel_emit_linear_blit(struct brw_context *brw,
733 struct brw_bo *dst_bo,
734 unsigned int dst_offset,
735 struct brw_bo *src_bo,
736 unsigned int src_offset,
737 unsigned int size)
738 {
739 struct gl_context *ctx = &brw->ctx;
740 GLuint pitch, height;
741 int16_t src_x, dst_x;
742 bool ok;
743
744 do {
745 /* The pitch given to the GPU must be DWORD aligned, and
746 * we want width to match pitch. Max width is (1 << 15 - 1),
747 * rounding that down to the nearest DWORD is 1 << 15 - 4
748 */
749 pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
750 height = (size < pitch || pitch == 0) ? 1 : size / pitch;
751
752 src_x = src_offset % 64;
753 dst_x = dst_offset % 64;
754 pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
755 assert(src_x + pitch < 1 << 15);
756 assert(dst_x + pitch < 1 << 15);
757
758 ok = intelEmitCopyBlit(brw, 1,
759 pitch, src_bo, src_offset - src_x,
760 ISL_TILING_LINEAR,
761 pitch, dst_bo, dst_offset - dst_x,
762 ISL_TILING_LINEAR,
763 src_x, 0, /* src x/y */
764 dst_x, 0, /* dst x/y */
765 MIN2(size, pitch), height, /* w, h */
766 GL_COPY);
767 if (!ok) {
768 _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
769 MIN2(size, pitch), height);
770 return;
771 }
772
773 pitch *= height;
774 if (size <= pitch)
775 return;
776
777 src_offset += pitch;
778 dst_offset += pitch;
779 size -= pitch;
780 } while (1);
781 }
782
783 /**
784 * Used to initialize the alpha value of an ARGB8888 miptree after copying
785 * into it from an XRGB8888 source.
786 *
787 * This is very common with glCopyTexImage2D(). Note that the coordinates are
788 * relative to the start of the miptree, not relative to a slice within the
789 * miptree.
790 */
791 static void
intel_miptree_set_alpha_to_one(struct brw_context * brw,struct intel_mipmap_tree * mt,int x,int y,int width,int height)792 intel_miptree_set_alpha_to_one(struct brw_context *brw,
793 struct intel_mipmap_tree *mt,
794 int x, int y, int width, int height)
795 {
796 const struct gen_device_info *devinfo = &brw->screen->devinfo;
797 uint32_t BR13, CMD;
798 int pitch, cpp;
799
800 pitch = mt->surf.row_pitch;
801 cpp = mt->cpp;
802
803 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
804 __func__, mt->bo, pitch, x, y, width, height);
805
806 /* Note: Currently only handles 8 bit alpha channel. Extension to < 8 Bit
807 * alpha channel would be likely possible via ROP code 0xfa instead of 0xf0
808 * and writing a suitable bit-mask instead of 0xffffffff.
809 */
810 BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
811 CMD = XY_COLOR_BLT_CMD;
812 CMD |= XY_BLT_WRITE_ALPHA;
813
814 if (mt->surf.tiling != ISL_TILING_LINEAR) {
815 CMD |= XY_DST_TILED;
816 pitch /= 4;
817 }
818 BR13 |= pitch;
819
820 /* do space check before going any further */
821 if (!brw_batch_has_aperture_space(brw, mt->bo->size))
822 intel_batchbuffer_flush(brw);
823
824 unsigned length = devinfo->gen >= 8 ? 7 : 6;
825 const bool dst_y_tiled = mt->surf.tiling == ISL_TILING_Y0;
826
827 /* We need to split the blit into chunks that each fit within the blitter's
828 * restrictions. We can't use a chunk size of 32768 because we need to
829 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
830 * a nice round power of two, big enough that performance won't suffer, and
831 * small enough to guarantee everything fits.
832 */
833 const uint32_t max_chunk_size = 16384;
834
835 for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
836 for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
837 const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
838 const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
839
840 uint32_t offset, tile_x, tile_y;
841 get_blit_intratile_offset_el(brw, mt,
842 x + chunk_x, y + chunk_y,
843 &offset, &tile_x, &tile_y);
844
845 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
846 OUT_BATCH(CMD | (length - 2));
847 OUT_BATCH(BR13);
848 OUT_BATCH(SET_FIELD(y + chunk_y, BLT_Y) |
849 SET_FIELD(x + chunk_x, BLT_X));
850 OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
851 SET_FIELD(x + chunk_x + chunk_w, BLT_X));
852 if (devinfo->gen >= 8) {
853 OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset);
854 } else {
855 OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset);
856 }
857 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
858 ADVANCE_BATCH_TILED(dst_y_tiled, false);
859 }
860 }
861
862 brw_emit_mi_flush(brw);
863 }
864