| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 782 __ ld1(v18.V16B(), v19.V16B(), v20.V16B(), v21.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
783 __ ld1(v23.V16B(), in GenerateTestSequenceNEON() local
788 __ ld1(v5.V16B(), in GenerateTestSequenceNEON() local
793 __ ld1(v18.V16B(), v19.V16B(), v20.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
794 __ ld1(v13.V16B(), v14.V16B(), v15.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
795 __ ld1(v19.V16B(), v20.V16B(), v21.V16B(), MemOperand(x1, 48, PostIndex)); in GenerateTestSequenceNEON() local
796 __ ld1(v17.V16B(), v18.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
797 __ ld1(v20.V16B(), v21.V16B(), MemOperand(x1, x2, PostIndex)); in GenerateTestSequenceNEON() local
798 __ ld1(v28.V16B(), v29.V16B(), MemOperand(x1, 32, PostIndex)); in GenerateTestSequenceNEON() local
799 __ ld1(v29.V16B(), MemOperand(x0)); in GenerateTestSequenceNEON() local
[all …]
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| /external/clang/test/CodeGen/ |
| D | x86_32-arguments-iamcu.c | 68 long double longDoubleArg(long double ld1) { return ld1; } in longDoubleArg()
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 2729 void Assembler::ld1(const VRegister& vt, const MemOperand& src) { in ld1() function in v8::internal::Assembler
2733 void Assembler::ld1(const VRegister& vt, const VRegister& vt2, in ld1() function in v8::internal::Assembler
2741 void Assembler::ld1(const VRegister& vt, const VRegister& vt2, in ld1() function in v8::internal::Assembler
2750 void Assembler::ld1(const VRegister& vt, const VRegister& vt2, in ld1() function in v8::internal::Assembler
2975 void Assembler::ld1(const VRegister& vt, int lane, const MemOperand& src) { in ld1() function in v8::internal::Assembler
|
| D | simulator-logic-arm64.cc | 347 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() function in v8::internal::Simulator
355 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, int index, in ld1() function in v8::internal::Simulator
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 1896 void Assembler::ld1(const VRegister& vt, const MemOperand& src) { in ld1() function in vixl::aarch64::Assembler
1902 void Assembler::ld1(const VRegister& vt, in ld1() function in vixl::aarch64::Assembler
1913 void Assembler::ld1(const VRegister& vt, in ld1() function in vixl::aarch64::Assembler
1925 void Assembler::ld1(const VRegister& vt, in ld1() function in vixl::aarch64::Assembler
2206 void Assembler::ld1(const VRegister& vt, int lane, const MemOperand& src) { in ld1() function in vixl::aarch64::Assembler
|
| D | logic-aarch64.cc | 170 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() function in vixl::aarch64::Simulator
179 void Simulator::ld1(VectorFormat vform, in ld1() function in vixl::aarch64::Simulator
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_peephole.cpp | 3698 DeadCodeElim::checkSplitLoad(Instruction *ld1) in checkSplitLoad()
|