1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
4 * (C) Copyright 2004-2008
5 * Texas Instruments, <www.ti.com>
6 *
7 * Derived from Beagle Board code by
8 * Sunil Kumar <sunilsaini05@gmail.com>
9 * Shashi Ranjan <shashiranjanmca05@gmail.com>
10 *
11 */
12
13 #include <common.h>
14 #include <usb.h>
15 #include <usb/ulpi.h>
16 #include <errno.h>
17 #include <asm/io.h>
18 #include <asm/gpio.h>
19 #include <asm/arch/ehci.h>
20 #include <asm/ehci-omap.h>
21
22 #include "ehci.h"
23
24 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
25 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
26 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
27
omap_uhh_reset(void)28 static int omap_uhh_reset(void)
29 {
30 int timeout = 0;
31 u32 rev;
32
33 rev = readl(&uhh->rev);
34
35 /* Soft RESET */
36 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
37
38 switch (rev) {
39 case OMAP_USBHS_REV1:
40 /* Wait for soft RESET to complete */
41 while (!(readl(&uhh->syss) & 0x1)) {
42 if (timeout > 100) {
43 printf("%s: RESET timeout\n", __func__);
44 return -1;
45 }
46 udelay(10);
47 timeout++;
48 }
49
50 /* Set No-Idle, No-Standby */
51 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
52 break;
53
54 default: /* Rev. 2 onwards */
55
56 udelay(2); /* Need to wait before accessing SYSCONFIG back */
57
58 /* Wait for soft RESET to complete */
59 while ((readl(&uhh->sysc) & 0x1)) {
60 if (timeout > 100) {
61 printf("%s: RESET timeout\n", __func__);
62 return -1;
63 }
64 udelay(10);
65 timeout++;
66 }
67
68 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
69 break;
70 }
71
72 return 0;
73 }
74
omap_ehci_tll_reset(void)75 static int omap_ehci_tll_reset(void)
76 {
77 unsigned long init = get_timer(0);
78
79 /* perform TLL soft reset, and wait until reset is complete */
80 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
81
82 /* Wait for TLL reset to complete */
83 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
84 if (get_timer(init) > CONFIG_SYS_HZ) {
85 debug("OMAP EHCI error: timeout resetting TLL\n");
86 return -EL3RST;
87 }
88
89 return 0;
90 }
91
omap_usbhs_hsic_init(int port)92 static void omap_usbhs_hsic_init(int port)
93 {
94 unsigned int reg;
95
96 /* Enable channels now */
97 reg = readl(&usbtll->channel_conf + port);
98
99 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
100 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
101 | OMAP_TLL_CHANNEL_CONF_DRVVBUS
102 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
103 | OMAP_TLL_CHANNEL_CONF_CHANEN));
104
105 writel(reg, &usbtll->channel_conf + port);
106 }
107
108 #ifdef CONFIG_USB_ULPI
omap_ehci_soft_phy_reset(int port)109 static void omap_ehci_soft_phy_reset(int port)
110 {
111 struct ulpi_viewport ulpi_vp;
112
113 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
114 ulpi_vp.port_num = port;
115
116 ulpi_reset(&ulpi_vp);
117 }
118 #else
omap_ehci_soft_phy_reset(int port)119 static void omap_ehci_soft_phy_reset(int port)
120 {
121 return;
122 }
123 #endif
124
125 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
126 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
127 defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
128 /* controls PHY(s) reset signal(s) */
omap_ehci_phy_reset(int on,int delay)129 static inline void omap_ehci_phy_reset(int on, int delay)
130 {
131 /*
132 * Refer ISSUE1:
133 * Hold the PHY in RESET for enough time till
134 * PHY is settled and ready
135 */
136 if (delay && !on)
137 udelay(delay);
138 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
139 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
140 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
141 #endif
142 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
143 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
144 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
145 #endif
146 #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
147 gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
148 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
149 #endif
150
151 /* Hold the PHY in RESET for enough time till DIR is high */
152 /* Refer: ISSUE1 */
153 if (delay && on)
154 udelay(delay);
155 }
156 #else
157 #define omap_ehci_phy_reset(on, delay) do {} while (0)
158 #endif
159
160 /* Reset is needed otherwise the kernel-driver will throw an error. */
omap_ehci_hcd_stop(void)161 int omap_ehci_hcd_stop(void)
162 {
163 debug("Resetting OMAP EHCI\n");
164 omap_ehci_phy_reset(1, 0);
165
166 if (omap_uhh_reset() < 0)
167 return -1;
168
169 if (omap_ehci_tll_reset() < 0)
170 return -1;
171
172 return 0;
173 }
174
175 /*
176 * Initialize the OMAP EHCI controller and PHY.
177 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
178 * See there for additional Copyrights.
179 */
omap_ehci_hcd_init(int index,struct omap_usbhs_board_data * usbhs_pdata,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)180 int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
181 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
182 {
183 int ret;
184 unsigned int i, reg = 0, rev = 0;
185
186 debug("Initializing OMAP EHCI\n");
187
188 ret = board_usb_init(index, USB_INIT_HOST);
189 if (ret < 0)
190 return ret;
191
192 /* Put the PHY in RESET */
193 omap_ehci_phy_reset(1, 10);
194
195 ret = omap_uhh_reset();
196 if (ret < 0)
197 return ret;
198
199 ret = omap_ehci_tll_reset();
200 if (ret)
201 return ret;
202
203 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
204 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
205 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
206
207 /* Put UHH in NoIdle/NoStandby mode */
208 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
209
210 /* setup ULPI bypass and burst configurations */
211 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
212 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
213 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
214 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
215
216 rev = readl(&uhh->rev);
217 if (rev == OMAP_USBHS_REV1) {
218 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
219 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
220 else
221 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
222
223 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
224 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
225 else
226 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
227
228 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
229 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
230 else
231 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
232 } else if (rev == OMAP_USBHS_REV2) {
233
234 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
235 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
236
237 /* Clear port mode fields for PHY mode */
238
239 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
240 setbits_le32(®, OMAP_P1_MODE_HSIC);
241
242 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
243 setbits_le32(®, OMAP_P2_MODE_HSIC);
244
245 } else if (rev == OMAP_USBHS_REV2_1) {
246
247 clrsetbits_le32(®,
248 (OMAP_P1_MODE_CLEAR |
249 OMAP_P2_MODE_CLEAR |
250 OMAP_P3_MODE_CLEAR),
251 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
252
253 /* Clear port mode fields for PHY mode */
254
255 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
256 setbits_le32(®, OMAP_P1_MODE_HSIC);
257
258 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
259 setbits_le32(®, OMAP_P2_MODE_HSIC);
260
261 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
262 setbits_le32(®, OMAP_P3_MODE_HSIC);
263 }
264
265 debug("OMAP UHH_REVISION 0x%x\n", rev);
266 writel(reg, &uhh->hostconfig);
267
268 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
269 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
270 omap_usbhs_hsic_init(i);
271
272 omap_ehci_phy_reset(0, 10);
273
274 /*
275 * An undocumented "feature" in the OMAP3 EHCI controller,
276 * causes suspended ports to be taken out of suspend when
277 * the USBCMD.Run/Stop bit is cleared (for example when
278 * we do ehci_bus_suspend).
279 * This breaks suspend-resume if the root-hub is allowed
280 * to suspend. Writing 1 to this undocumented register bit
281 * disables this feature and restores normal behavior.
282 */
283 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
284
285 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
286 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
287 omap_ehci_soft_phy_reset(i);
288
289 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
290 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
291
292 debug("OMAP EHCI init done\n");
293 return 0;
294 }
295