1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 */
6
7 /*
8 * PCI Configuration space access support
9 */
10 #include <common.h>
11 #include <pci.h>
12 #include <asm/io.h>
13 #include <asm/immap.h>
14
15 #if defined(CONFIG_PCI)
16 /* System RAM mapped over PCI */
17 #define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
18 #define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
19 #define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
20
21 #define cfg_read(val, addr, type, op) *val = op((type)(addr));
22 #define cfg_write(val, addr, type, op) op((type *)(addr), (val));
23
24 #define PCI_OP(rw, size, type, op, mask) \
25 int pci_##rw##_cfg_##size(struct pci_controller *hose, \
26 pci_dev_t dev, int offset, type val) \
27 { \
28 u32 addr = 0; \
29 u16 cfg_type = 0; \
30 addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
31 out_be32(hose->cfg_addr, addr); \
32 cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
33 out_be32(hose->cfg_addr, addr & 0x7fffffff); \
34 return 0; \
35 }
36
37 PCI_OP(read, byte, u8 *, in_8, 3)
38 PCI_OP(read, word, u16 *, in_le16, 2)
39 PCI_OP(read, dword, u32 *, in_le32, 0)
40 PCI_OP(write, byte, u8, out_8, 3)
41 PCI_OP(write, word, u16, out_le16, 2)
42 PCI_OP(write, dword, u32, out_le32, 0)
43
pci_mcf5445x_init(struct pci_controller * hose)44 void pci_mcf5445x_init(struct pci_controller *hose)
45 {
46 pci_t *pci = (pci_t *)MMAP_PCI;
47 pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
48 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
49 u32 barEn = 0;
50
51 out_be32(&pciarb->acr, 0x001f001f);
52
53 /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
54 PCIREQ2, PCIGNT2 */
55 out_be16(&gpio->par_pci,
56 GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
57 GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
58 GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
59 GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
60
61 /* Assert reset bit */
62 setbits_be32(&pci->gscr, PCI_GSCR_PR);
63
64 setbits_be32(&pci->tcr1, PCI_TCR1_P);
65
66 /* Initiator windows */
67 out_be32(&pci->iw0btar,
68 CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
69 out_be32(&pci->iw1btar,
70 CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
71 out_be32(&pci->iw2btar,
72 CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
73
74 out_be32(&pci->iwcr,
75 PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
76 PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
77
78 out_be32(&pci->icr, 0);
79
80 /* Enable bus master and mem access */
81 out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
82
83 /* Cache line size and master latency */
84 out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
85 out_be32(&pci->cr2, 0);
86
87 #ifdef CONFIG_SYS_PCI_BAR0
88 out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
89 out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
90 barEn |= PCI_TCR2_B0E;
91 #endif
92 #ifdef CONFIG_SYS_PCI_BAR1
93 out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
94 out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
95 barEn |= PCI_TCR2_B1E;
96 #endif
97 #ifdef CONFIG_SYS_PCI_BAR2
98 out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
99 out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
100 barEn |= PCI_TCR2_B2E;
101 #endif
102 #ifdef CONFIG_SYS_PCI_BAR3
103 out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
104 out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
105 barEn |= PCI_TCR2_B3E;
106 #endif
107 #ifdef CONFIG_SYS_PCI_BAR4
108 out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
109 out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
110 barEn |= PCI_TCR2_B4E;
111 #endif
112 #ifdef CONFIG_SYS_PCI_BAR5
113 out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
114 out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
115 barEn |= PCI_TCR2_B5E;
116 #endif
117
118 out_be32(&pci->tcr2, barEn);
119
120 /* Deassert reset bit */
121 clrbits_be32(&pci->gscr, PCI_GSCR_PR);
122 udelay(1000);
123
124 /* Enable PCI bus master support */
125 hose->first_busno = 0;
126 hose->last_busno = 0xff;
127
128 pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
129 CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
130
131 pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
132 CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
133
134 pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
135 CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
136 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
137
138 hose->region_count = 3;
139
140 hose->cfg_addr = &(pci->car);
141 hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
142
143 pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
144 pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
145 pci_write_cfg_dword);
146
147 /* Hose scan */
148 pci_register_hose(hose);
149 hose->last_busno = pci_hose_scan(hose);
150 }
151 #endif /* CONFIG_PCI */
152