1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include <errno.h>
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_math.h"
38 #include "vl/vl_decoder.h"
39 #include "vl/vl_video_buffer.h"
40 #include "radeon_video.h"
41 #include "radeon_uvd.h"
42 #include "util/os_time.h"
43
44 static const struct debug_named_value r600_debug_options[] = {
45 /* features */
46 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
47
48 /* shader backend */
49 { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
50 { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
51 { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
52 { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
53 { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
54 { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
55 { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
56 { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
57
58 DEBUG_NAMED_VALUE_END /* must be last */
59 };
60
61 /*
62 * pipe_context
63 */
64
r600_destroy_context(struct pipe_context * context)65 static void r600_destroy_context(struct pipe_context *context)
66 {
67 struct r600_context *rctx = (struct r600_context *)context;
68 unsigned sh;
69
70 r600_isa_destroy(rctx->isa);
71
72 r600_sb_context_destroy(rctx->sb_context);
73
74 r600_resource_reference(&rctx->dummy_cmask, NULL);
75 r600_resource_reference(&rctx->dummy_fmask, NULL);
76
77 if (rctx->append_fence)
78 pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
79 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
80 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
81 free(rctx->driver_consts[sh].constants);
82 }
83
84 if (rctx->fixed_func_tcs_shader)
85 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
86
87 if (rctx->dummy_pixel_shader) {
88 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
89 }
90 if (rctx->custom_dsa_flush) {
91 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
92 }
93 if (rctx->custom_blend_resolve) {
94 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
95 }
96 if (rctx->custom_blend_decompress) {
97 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
98 }
99 if (rctx->custom_blend_fastclear) {
100 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
101 }
102 util_unreference_framebuffer_state(&rctx->framebuffer.state);
103
104 if (rctx->blitter) {
105 util_blitter_destroy(rctx->blitter);
106 }
107 if (rctx->allocator_fetch_shader) {
108 u_suballocator_destroy(rctx->allocator_fetch_shader);
109 }
110
111 r600_release_command_buffer(&rctx->start_cs_cmd);
112
113 FREE(rctx->start_compute_cs_cmd.buf);
114
115 r600_common_context_cleanup(&rctx->b);
116
117 r600_resource_reference(&rctx->trace_buf, NULL);
118 r600_resource_reference(&rctx->last_trace_buf, NULL);
119 radeon_clear_saved_cs(&rctx->last_gfx);
120
121 FREE(rctx);
122 }
123
r600_create_context(struct pipe_screen * screen,void * priv,unsigned flags)124 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
125 void *priv, unsigned flags)
126 {
127 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
128 struct r600_screen* rscreen = (struct r600_screen *)screen;
129 struct radeon_winsys *ws = rscreen->b.ws;
130
131 if (!rctx)
132 return NULL;
133
134 rctx->b.b.screen = screen;
135 assert(!priv);
136 rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
137 rctx->b.b.destroy = r600_destroy_context;
138 rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
139
140 if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
141 goto fail;
142
143 rctx->screen = rscreen;
144 LIST_INITHEAD(&rctx->texture_buffers);
145
146 r600_init_blit_functions(rctx);
147
148 if (rscreen->b.info.has_hw_decode) {
149 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
150 rctx->b.b.create_video_buffer = r600_video_buffer_create;
151 } else {
152 rctx->b.b.create_video_codec = vl_create_decoder;
153 rctx->b.b.create_video_buffer = vl_video_buffer_create;
154 }
155
156 if (getenv("R600_TRACE"))
157 rctx->is_debug = true;
158 r600_init_common_state_functions(rctx);
159
160 switch (rctx->b.chip_class) {
161 case R600:
162 case R700:
163 r600_init_state_functions(rctx);
164 r600_init_atom_start_cs(rctx);
165 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
166 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
167 : r600_create_resolve_blend(rctx);
168 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
169 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
170 rctx->b.family == CHIP_RV620 ||
171 rctx->b.family == CHIP_RS780 ||
172 rctx->b.family == CHIP_RS880 ||
173 rctx->b.family == CHIP_RV710);
174 break;
175 case EVERGREEN:
176 case CAYMAN:
177 evergreen_init_state_functions(rctx);
178 evergreen_init_atom_start_cs(rctx);
179 evergreen_init_atom_start_compute_cs(rctx);
180 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
181 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
182 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
183 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
184 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
185 rctx->b.family == CHIP_PALM ||
186 rctx->b.family == CHIP_SUMO ||
187 rctx->b.family == CHIP_SUMO2 ||
188 rctx->b.family == CHIP_CAICOS ||
189 rctx->b.family == CHIP_CAYMAN ||
190 rctx->b.family == CHIP_ARUBA);
191
192 rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
193 PIPE_USAGE_DEFAULT, 32);
194 break;
195 default:
196 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
197 goto fail;
198 }
199
200 rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
201 r600_context_gfx_flush, rctx);
202 rctx->b.gfx.flush = r600_context_gfx_flush;
203
204 rctx->allocator_fetch_shader =
205 u_suballocator_create(&rctx->b.b, 64 * 1024,
206 0, PIPE_USAGE_DEFAULT, 0, FALSE);
207 if (!rctx->allocator_fetch_shader)
208 goto fail;
209
210 rctx->isa = calloc(1, sizeof(struct r600_isa));
211 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
212 goto fail;
213
214 if (rscreen->b.debug_flags & DBG_FORCE_DMA)
215 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
216
217 rctx->blitter = util_blitter_create(&rctx->b.b);
218 if (rctx->blitter == NULL)
219 goto fail;
220 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
221 rctx->blitter->draw_rectangle = r600_draw_rectangle;
222
223 r600_begin_new_cs(rctx);
224
225 rctx->dummy_pixel_shader =
226 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
227 TGSI_SEMANTIC_GENERIC,
228 TGSI_INTERPOLATE_CONSTANT);
229 rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
230
231 return &rctx->b.b;
232
233 fail:
234 r600_destroy_context(&rctx->b.b);
235 return NULL;
236 }
237
238 /*
239 * pipe_screen
240 */
241
r600_get_param(struct pipe_screen * pscreen,enum pipe_cap param)242 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
243 {
244 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
245 enum radeon_family family = rscreen->b.family;
246
247 switch (param) {
248 /* Supported features (boolean caps). */
249 case PIPE_CAP_NPOT_TEXTURES:
250 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
251 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
252 case PIPE_CAP_ANISOTROPIC_FILTER:
253 case PIPE_CAP_POINT_SPRITE:
254 case PIPE_CAP_OCCLUSION_QUERY:
255 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
256 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
257 case PIPE_CAP_TEXTURE_SWIZZLE:
258 case PIPE_CAP_DEPTH_CLIP_DISABLE:
259 case PIPE_CAP_SHADER_STENCIL_EXPORT:
260 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
261 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
262 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
263 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
264 case PIPE_CAP_SM3:
265 case PIPE_CAP_SEAMLESS_CUBE_MAP:
266 case PIPE_CAP_PRIMITIVE_RESTART:
267 case PIPE_CAP_CONDITIONAL_RENDER:
268 case PIPE_CAP_TEXTURE_BARRIER:
269 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
270 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
271 case PIPE_CAP_TGSI_INSTANCEID:
272 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
273 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
274 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
275 case PIPE_CAP_START_INSTANCE:
276 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
277 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
278 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
279 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
280 case PIPE_CAP_TEXTURE_MULTISAMPLE:
281 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
282 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
283 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
284 case PIPE_CAP_SAMPLE_SHADING:
285 case PIPE_CAP_CLIP_HALFZ:
286 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
287 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
288 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
289 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
290 case PIPE_CAP_TGSI_TXQS:
291 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
292 case PIPE_CAP_INVALIDATE_BUFFER:
293 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
294 case PIPE_CAP_QUERY_MEMORY_INFO:
295 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
296 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
297 case PIPE_CAP_CLEAR_TEXTURE:
298 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
299 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
300 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
301 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
302 return 1;
303
304 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
305 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
306
307 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
308 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
309
310 case PIPE_CAP_COMPUTE:
311 return rscreen->b.chip_class > R700;
312
313 case PIPE_CAP_TGSI_TEXCOORD:
314 return 0;
315
316 case PIPE_CAP_FAKE_SW_MSAA:
317 return 0;
318
319 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
320 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
321
322 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
323 return R600_MAP_BUFFER_ALIGNMENT;
324
325 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
326 return 256;
327
328 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
329 return 1;
330
331 case PIPE_CAP_GLSL_FEATURE_LEVEL:
332 if (family >= CHIP_CEDAR)
333 return 430;
334 /* pre-evergreen geom shaders need newer kernel */
335 if (rscreen->b.info.drm_minor >= 37)
336 return 330;
337 return 140;
338
339 /* Supported except the original R600. */
340 case PIPE_CAP_INDEP_BLEND_ENABLE:
341 case PIPE_CAP_INDEP_BLEND_FUNC:
342 /* R600 doesn't support per-MRT blends */
343 return family == CHIP_R600 ? 0 : 1;
344
345 /* Supported on Evergreen. */
346 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
347 case PIPE_CAP_CUBE_MAP_ARRAY:
348 case PIPE_CAP_TEXTURE_GATHER_SM5:
349 case PIPE_CAP_TEXTURE_QUERY_LOD:
350 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
351 case PIPE_CAP_SAMPLER_VIEW_TARGET:
352 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
353 case PIPE_CAP_TGSI_CLOCK:
354 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
355 return family >= CHIP_CEDAR ? 1 : 0;
356 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
357 return family >= CHIP_CEDAR ? 4 : 0;
358 case PIPE_CAP_DRAW_INDIRECT:
359 /* kernel command checker support is also required */
360 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
361
362 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
363 return family >= CHIP_CEDAR ? 0 : 1;
364
365 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
366 return 8;
367
368 /* Unsupported features. */
369 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
370 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
371 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
372 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
373 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
374 case PIPE_CAP_USER_VERTEX_BUFFERS:
375 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
376 case PIPE_CAP_VERTEXID_NOBASE:
377 case PIPE_CAP_DEPTH_BOUNDS_TEST:
378 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
379 case PIPE_CAP_SHAREABLE_SHADERS:
380 case PIPE_CAP_DRAW_PARAMETERS:
381 case PIPE_CAP_MULTI_DRAW_INDIRECT:
382 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
383 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
384 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
385 case PIPE_CAP_GENERATE_MIPMAP:
386 case PIPE_CAP_STRING_MARKER:
387 case PIPE_CAP_QUERY_BUFFER_OBJECT:
388 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
389 case PIPE_CAP_TGSI_VOTE:
390 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
391 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
392 case PIPE_CAP_NATIVE_FENCE_FD:
393 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
394 case PIPE_CAP_TGSI_FS_FBFETCH:
395 case PIPE_CAP_INT64:
396 case PIPE_CAP_INT64_DIVMOD:
397 case PIPE_CAP_TGSI_TEX_TXF_LZ:
398 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
399 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
400 case PIPE_CAP_TGSI_BALLOT:
401 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
402 case PIPE_CAP_POST_DEPTH_COVERAGE:
403 case PIPE_CAP_BINDLESS_TEXTURE:
404 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
405 case PIPE_CAP_QUERY_SO_OVERFLOW:
406 case PIPE_CAP_MEMOBJ:
407 case PIPE_CAP_LOAD_CONSTBUF:
408 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
409 case PIPE_CAP_TILE_RASTER_ORDER:
410 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
411 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
412 return 0;
413
414 case PIPE_CAP_DOUBLES:
415 if (rscreen->b.family == CHIP_ARUBA ||
416 rscreen->b.family == CHIP_CAYMAN ||
417 rscreen->b.family == CHIP_CYPRESS ||
418 rscreen->b.family == CHIP_HEMLOCK)
419 return 1;
420 return 0;
421 case PIPE_CAP_CULL_DISTANCE:
422 return 1;
423
424 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
425 if (family >= CHIP_CEDAR)
426 return 256;
427 return 0;
428
429 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
430 if (family >= CHIP_CEDAR)
431 return 30;
432 else
433 return 0;
434 /* Stream output. */
435 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
436 return rscreen->b.has_streamout ? 4 : 0;
437 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
438 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
439 return rscreen->b.has_streamout ? 1 : 0;
440 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
441 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
442 return 32*4;
443
444 /* Geometry shader output. */
445 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
446 return 1024;
447 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
448 return 16384;
449 case PIPE_CAP_MAX_VERTEX_STREAMS:
450 return family >= CHIP_CEDAR ? 4 : 1;
451
452 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
453 return 2047;
454
455 /* Texturing. */
456 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
457 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
458 if (family >= CHIP_CEDAR)
459 return 15;
460 else
461 return 14;
462 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
463 /* textures support 8192, but layered rendering supports 2048 */
464 return 12;
465 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
466 /* textures support 8192, but layered rendering supports 2048 */
467 return 2048;
468
469 /* Render targets. */
470 case PIPE_CAP_MAX_RENDER_TARGETS:
471 /* XXX some r6xx are buggy and can only do 4 */
472 return 8;
473
474 case PIPE_CAP_MAX_VIEWPORTS:
475 return R600_MAX_VIEWPORTS;
476 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
477 return 8;
478
479 /* Timer queries, present when the clock frequency is non zero. */
480 case PIPE_CAP_QUERY_TIME_ELAPSED:
481 return rscreen->b.info.clock_crystal_freq != 0;
482 case PIPE_CAP_QUERY_TIMESTAMP:
483 return rscreen->b.info.drm_minor >= 20 &&
484 rscreen->b.info.clock_crystal_freq != 0;
485
486 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
487 case PIPE_CAP_MIN_TEXEL_OFFSET:
488 return -8;
489
490 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
491 case PIPE_CAP_MAX_TEXEL_OFFSET:
492 return 7;
493
494 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
495 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
496 case PIPE_CAP_ENDIANNESS:
497 return PIPE_ENDIAN_LITTLE;
498
499 case PIPE_CAP_VENDOR_ID:
500 return ATI_VENDOR_ID;
501 case PIPE_CAP_DEVICE_ID:
502 return rscreen->b.info.pci_id;
503 case PIPE_CAP_ACCELERATED:
504 return 1;
505 case PIPE_CAP_VIDEO_MEMORY:
506 return rscreen->b.info.vram_size >> 20;
507 case PIPE_CAP_UMA:
508 return 0;
509 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
510 return rscreen->b.chip_class >= R700;
511 case PIPE_CAP_PCI_GROUP:
512 return rscreen->b.info.pci_domain;
513 case PIPE_CAP_PCI_BUS:
514 return rscreen->b.info.pci_bus;
515 case PIPE_CAP_PCI_DEVICE:
516 return rscreen->b.info.pci_dev;
517 case PIPE_CAP_PCI_FUNCTION:
518 return rscreen->b.info.pci_func;
519 }
520 return 0;
521 }
522
r600_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)523 static int r600_get_shader_param(struct pipe_screen* pscreen,
524 enum pipe_shader_type shader,
525 enum pipe_shader_cap param)
526 {
527 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
528
529 switch(shader)
530 {
531 case PIPE_SHADER_FRAGMENT:
532 case PIPE_SHADER_VERTEX:
533 case PIPE_SHADER_COMPUTE:
534 break;
535 case PIPE_SHADER_GEOMETRY:
536 if (rscreen->b.family >= CHIP_CEDAR)
537 break;
538 /* pre-evergreen geom shaders need newer kernel */
539 if (rscreen->b.info.drm_minor >= 37)
540 break;
541 return 0;
542 case PIPE_SHADER_TESS_CTRL:
543 case PIPE_SHADER_TESS_EVAL:
544 if (rscreen->b.family >= CHIP_CEDAR)
545 break;
546 default:
547 return 0;
548 }
549
550 switch (param) {
551 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
552 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
553 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
554 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
555 return 16384;
556 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
557 return 32;
558 case PIPE_SHADER_CAP_MAX_INPUTS:
559 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
560 case PIPE_SHADER_CAP_MAX_OUTPUTS:
561 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
562 case PIPE_SHADER_CAP_MAX_TEMPS:
563 return 256; /* Max native temporaries. */
564 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
565 if (shader == PIPE_SHADER_COMPUTE) {
566 uint64_t max_const_buffer_size;
567 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
568 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
569 &max_const_buffer_size);
570 return MIN2(max_const_buffer_size, INT_MAX);
571
572 } else {
573 return R600_MAX_CONST_BUFFER_SIZE;
574 }
575 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
576 return R600_MAX_USER_CONST_BUFFERS;
577 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
578 return 1;
579 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
580 return 1;
581 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
582 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
583 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
584 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
585 return 1;
586 case PIPE_SHADER_CAP_SUBROUTINES:
587 case PIPE_SHADER_CAP_INT64_ATOMICS:
588 case PIPE_SHADER_CAP_FP16:
589 return 0;
590 case PIPE_SHADER_CAP_INTEGERS:
591 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
592 return 1;
593 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
594 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
595 return 16;
596 case PIPE_SHADER_CAP_PREFERRED_IR:
597 if (shader == PIPE_SHADER_COMPUTE) {
598 return PIPE_SHADER_IR_NATIVE;
599 } else {
600 return PIPE_SHADER_IR_TGSI;
601 }
602 case PIPE_SHADER_CAP_SUPPORTED_IRS:
603 if (rscreen->b.family >= CHIP_CEDAR)
604 return (1 << PIPE_SHADER_IR_TGSI);
605 return 0;
606 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
607 if (rscreen->b.family == CHIP_ARUBA ||
608 rscreen->b.family == CHIP_CAYMAN ||
609 rscreen->b.family == CHIP_CYPRESS ||
610 rscreen->b.family == CHIP_HEMLOCK)
611 return 1;
612 return 0;
613 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
614 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
615 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
616 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
617 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
618 return 0;
619 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
620 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
621 if (rscreen->b.family >= CHIP_CEDAR &&
622 (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
623 return 8;
624 return 0;
625 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
626 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
627 return 8;
628 return 0;
629 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
630 /* having to allocate the atomics out amongst shaders stages is messy,
631 so give compute 8 buffers and all the others one */
632 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
633 return EG_MAX_ATOMIC_BUFFERS;
634 }
635 return 0;
636 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
637 /* due to a bug in the shader compiler, some loops hang
638 * if they are not unrolled, see:
639 * https://bugs.freedesktop.org/show_bug.cgi?id=86720
640 */
641 return 255;
642 }
643 return 0;
644 }
645
r600_destroy_screen(struct pipe_screen * pscreen)646 static void r600_destroy_screen(struct pipe_screen* pscreen)
647 {
648 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
649
650 if (!rscreen)
651 return;
652
653 if (!rscreen->b.ws->unref(rscreen->b.ws))
654 return;
655
656 if (rscreen->global_pool) {
657 compute_memory_pool_delete(rscreen->global_pool);
658 }
659
660 r600_destroy_common_screen(&rscreen->b);
661 }
662
r600_resource_create(struct pipe_screen * screen,const struct pipe_resource * templ)663 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
664 const struct pipe_resource *templ)
665 {
666 if (templ->target == PIPE_BUFFER &&
667 (templ->bind & PIPE_BIND_GLOBAL))
668 return r600_compute_global_buffer_create(screen, templ);
669
670 return r600_resource_create_common(screen, templ);
671 }
672
r600_screen_create(struct radeon_winsys * ws,const struct pipe_screen_config * config)673 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
674 const struct pipe_screen_config *config)
675 {
676 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
677
678 if (!rscreen) {
679 return NULL;
680 }
681
682 /* Set functions first. */
683 rscreen->b.b.context_create = r600_create_context;
684 rscreen->b.b.destroy = r600_destroy_screen;
685 rscreen->b.b.get_param = r600_get_param;
686 rscreen->b.b.get_shader_param = r600_get_shader_param;
687 rscreen->b.b.resource_create = r600_resource_create;
688
689 if (!r600_common_screen_init(&rscreen->b, ws)) {
690 FREE(rscreen);
691 return NULL;
692 }
693
694 if (rscreen->b.info.chip_class >= EVERGREEN) {
695 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
696 } else {
697 rscreen->b.b.is_format_supported = r600_is_format_supported;
698 }
699
700 rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
701 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
702 rscreen->b.debug_flags |= DBG_COMPUTE;
703 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
704 rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
705 if (!debug_get_bool_option("R600_HYPERZ", TRUE))
706 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
707
708 if (rscreen->b.family == CHIP_UNKNOWN) {
709 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
710 FREE(rscreen);
711 return NULL;
712 }
713
714 /* Figure out streamout kernel support. */
715 switch (rscreen->b.chip_class) {
716 case R600:
717 if (rscreen->b.family < CHIP_RS780) {
718 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
719 } else {
720 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
721 }
722 break;
723 case R700:
724 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
725 break;
726 case EVERGREEN:
727 case CAYMAN:
728 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
729 break;
730 default:
731 rscreen->b.has_streamout = FALSE;
732 break;
733 }
734
735 /* MSAA support. */
736 switch (rscreen->b.chip_class) {
737 case R600:
738 case R700:
739 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
740 rscreen->has_compressed_msaa_texturing = false;
741 break;
742 case EVERGREEN:
743 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
744 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
745 break;
746 case CAYMAN:
747 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
748 rscreen->has_compressed_msaa_texturing = true;
749 break;
750 default:
751 rscreen->has_msaa = FALSE;
752 rscreen->has_compressed_msaa_texturing = false;
753 }
754
755 rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
756 !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
757
758 rscreen->b.barrier_flags.cp_to_L2 =
759 R600_CONTEXT_INV_VERTEX_CACHE |
760 R600_CONTEXT_INV_TEX_CACHE |
761 R600_CONTEXT_INV_CONST_CACHE;
762 rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_PS_PARTIAL_FLUSH;
763
764 rscreen->global_pool = compute_memory_pool_new(rscreen);
765
766 /* Create the auxiliary context. This must be done last. */
767 rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
768
769 rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
770 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
771 struct pipe_resource templ = {};
772
773 templ.width0 = 4;
774 templ.height0 = 2048;
775 templ.depth0 = 1;
776 templ.array_size = 1;
777 templ.target = PIPE_TEXTURE_2D;
778 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
779 templ.usage = PIPE_USAGE_DEFAULT;
780
781 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
782 unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
783
784 memset(map, 0, 256);
785
786 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
787 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
788 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
789 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
790 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
791
792 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
793
794 int i;
795 for (i = 0; i < 256; i++) {
796 printf("%02X", map[i]);
797 if (i % 16 == 15)
798 printf("\n");
799 }
800 #endif
801
802 if (rscreen->b.debug_flags & DBG_TEST_DMA)
803 r600_test_dma(&rscreen->b);
804
805 r600_query_fix_enabled_rb_mask(&rscreen->b);
806 return &rscreen->b.b;
807 }
808