| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
| D | rbit.s | 10 rbit z0.b, p7/m, z31.b label
16 rbit z0.h, p7/m, z31.h label
22 rbit z0.s, p7/m, z31.s label
28 rbit z0.d, p7/m, z31.d label
44 rbit z0.d, p7/m, z31.d label
56 rbit z0.d, p7/m, z31.d label
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| D | rbit-diagnostics.s | 7 rbit z0.d, p8/m, z0.d label
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | not-armv4.s | 8 rbit r4,r9 label
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| /external/llvm/test/MC/ARM/ |
| D | not-armv4.s | 8 rbit r4,r9 label
|
| /external/clang/test/CodeGen/ |
| D | builtins-arm64.c | 14 unsigned rbit(unsigned a) { in rbit() function
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| D | builtins-arm.c | 73 unsigned rbit(unsigned a) { in rbit() function
|
| /external/libnl/lib/route/qdisc/ |
| D | cbq.c | 101 double r, rbit; in cbq_dump_line() local
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| D | htb.c | 135 double r, rbit; in htb_class_dump_line() local
156 double r, rbit; in htb_class_dump_details() local
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| D | tbf.c | 79 double r, rbit, lim; in tbf_dump_line() local
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 269 __ rbit(w12, w13); in GenerateTestSequenceBase() local
270 __ rbit(x14, x15); in GenerateTestSequenceBase() local
1323 __ rbit(v22.V16B(), v15.V16B()); in GenerateTestSequenceNEON() local
1324 __ rbit(v30.V8B(), v3.V8B()); in GenerateTestSequenceNEON() local
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 1557 void Assembler::rbit(const Register& rd, in rbit() function in v8::internal::Assembler
3854 void Assembler::rbit(const VRegister& vd, const VRegister& vn) { in rbit() function in v8::internal::Assembler
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| D | simulator-logic-arm64.cc | 1877 LogicVRegister Simulator::rbit(VectorFormat vform, LogicVRegister dst, in rbit() function in v8::internal::Simulator
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 992 void Assembler::rbit(const Register& rd, const Register& rn) { in rbit() function in vixl::aarch64::Assembler
4160 void Assembler::rbit(const VRegister& vd, const VRegister& vn) { in rbit() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 2085 LogicVRegister Simulator::rbit(VectorFormat vform, in rbit() function in vixl::aarch64::Simulator
|
| /external/v8/src/compiler/arm/ |
| D | code-generator-arm.cc | 1190 __ rbit(i.OutputRegister(), i.InputRegister(0)); in AssembleArchInstruction() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 2134 void AssemblerARM32::rbit(const Operand *OpRd, const Operand *OpRm, in rbit() function in Ice::ARM32::AssemblerARM32
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3353 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); in LowerCTTZ() local
|
| /external/v8/src/arm/ |
| D | assembler-arm.cc | 2052 void Assembler::rbit(Register dst, Register src, Condition cond) { in rbit() function in v8::internal::Assembler
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4685 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0)); in LowerCTTZ() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 5442 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0)); in LowerCTTZ() local
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2855 void rbit(Register rd, Register rm) { rbit(al, rd, rm); } in rbit() function
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| D | assembler-aarch32.cc | 8805 void Assembler::rbit(Condition cond, Register rd, Register rm) { in rbit() function in vixl::aarch32::Assembler
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| D | disasm-aarch32.cc | 2255 void Disassembler::rbit(Condition cond, Register rd, Register rm) { in rbit() function in vixl::aarch32::Disassembler
|