1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
19 #include "llvm/TableGen/Record.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/Format.h"
24 #include <algorithm>
25 #include <set>
26 using namespace llvm;
27
28 // runEnums - Print out enum values for all of the registers.
29 void
runEnums(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & Bank)30 RegisterInfoEmitter::runEnums(raw_ostream &OS,
31 CodeGenTarget &Target, CodeGenRegBank &Bank) {
32 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33
34 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
35
36 EmitSourceFileHeader("Target Register Enum Values", OS);
37
38 OS << "\n#ifdef GET_REGINFO_ENUM\n";
39 OS << "#undef GET_REGINFO_ENUM\n";
40
41 OS << "namespace llvm {\n\n";
42
43 OS << "class MCRegisterClass;\n"
44 << "extern MCRegisterClass " << Namespace << "MCRegisterClasses[];\n\n";
45
46 if (!Namespace.empty())
47 OS << "namespace " << Namespace << " {\n";
48 OS << "enum {\n NoRegister,\n";
49
50 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
51 OS << " " << Registers[i]->getName() << " = " <<
52 Registers[i]->EnumValue << ",\n";
53 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
54 "Register enum value mismatch!");
55 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
56 OS << "};\n";
57 if (!Namespace.empty())
58 OS << "}\n";
59
60 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
61 if (!RegisterClasses.empty()) {
62 OS << "\n// Register classes\n";
63 if (!Namespace.empty())
64 OS << "namespace " << Namespace << " {\n";
65 OS << "enum {\n";
66 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
67 if (i) OS << ",\n";
68 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
69 OS << " = " << i;
70 }
71 OS << "\n };\n";
72 if (!Namespace.empty())
73 OS << "}\n";
74 }
75
76 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
77 // If the only definition is the default NoRegAltName, we don't need to
78 // emit anything.
79 if (RegAltNameIndices.size() > 1) {
80 OS << "\n// Register alternate name indices\n";
81 if (!Namespace.empty())
82 OS << "namespace " << Namespace << " {\n";
83 OS << "enum {\n";
84 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
85 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
86 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
87 OS << "};\n";
88 if (!Namespace.empty())
89 OS << "}\n";
90 }
91
92
93 OS << "} // End llvm namespace \n";
94 OS << "#endif // GET_REGINFO_ENUM\n\n";
95 }
96
97 void
EmitRegMapping(raw_ostream & OS,const std::vector<CodeGenRegister * > & Regs,bool isCtor)98 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
99 const std::vector<CodeGenRegister*> &Regs,
100 bool isCtor) {
101
102 // Collect all information about dwarf register numbers
103 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
104 DwarfRegNumsMapTy DwarfRegNums;
105
106 // First, just pull all provided information to the map
107 unsigned maxLength = 0;
108 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
109 Record *Reg = Regs[i]->TheDef;
110 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
111 maxLength = std::max((size_t)maxLength, RegNums.size());
112 if (DwarfRegNums.count(Reg))
113 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
114 << "specified multiple times\n";
115 DwarfRegNums[Reg] = RegNums;
116 }
117
118 if (!maxLength)
119 return;
120
121 // Now we know maximal length of number list. Append -1's, where needed
122 for (DwarfRegNumsMapTy::iterator
123 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
124 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
125 I->second.push_back(-1);
126
127 // Emit reverse information about the dwarf register numbers.
128 for (unsigned j = 0; j < 2; ++j) {
129 OS << " switch (";
130 if (j == 0)
131 OS << "DwarfFlavour";
132 else
133 OS << "EHFlavour";
134 OS << ") {\n"
135 << " default:\n"
136 << " assert(0 && \"Unknown DWARF flavour\");\n"
137 << " break;\n";
138
139 for (unsigned i = 0, e = maxLength; i != e; ++i) {
140 OS << " case " << i << ":\n";
141 for (DwarfRegNumsMapTy::iterator
142 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
143 int DwarfRegNo = I->second[i];
144 if (DwarfRegNo < 0)
145 continue;
146 OS << " ";
147 if (!isCtor)
148 OS << "RI->";
149 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
150 << getQualifiedName(I->first) << ", ";
151 if (j == 0)
152 OS << "false";
153 else
154 OS << "true";
155 OS << " );\n";
156 }
157 OS << " break;\n";
158 }
159 OS << " }\n";
160 }
161
162 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
163 Record *Reg = Regs[i]->TheDef;
164 const RecordVal *V = Reg->getValue("DwarfAlias");
165 if (!V || !V->getValue())
166 continue;
167
168 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
169 Record *Alias = DI->getDef();
170 DwarfRegNums[Reg] = DwarfRegNums[Alias];
171 }
172
173 // Emit information about the dwarf register numbers.
174 for (unsigned j = 0; j < 2; ++j) {
175 OS << " switch (";
176 if (j == 0)
177 OS << "DwarfFlavour";
178 else
179 OS << "EHFlavour";
180 OS << ") {\n"
181 << " default:\n"
182 << " assert(0 && \"Unknown DWARF flavour\");\n"
183 << " break;\n";
184
185 for (unsigned i = 0, e = maxLength; i != e; ++i) {
186 OS << " case " << i << ":\n";
187 // Sort by name to get a stable order.
188 for (DwarfRegNumsMapTy::iterator
189 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
190 int RegNo = I->second[i];
191 OS << " ";
192 if (!isCtor)
193 OS << "RI->";
194 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
195 << RegNo << ", ";
196 if (j == 0)
197 OS << "false";
198 else
199 OS << "true";
200 OS << " );\n";
201 }
202 OS << " break;\n";
203 }
204 OS << " }\n";
205 }
206 }
207
208 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
209 // Width is the number of bits per hex number.
printBitVectorAsHex(raw_ostream & OS,const BitVector & Bits,unsigned Width)210 static void printBitVectorAsHex(raw_ostream &OS,
211 const BitVector &Bits,
212 unsigned Width) {
213 assert(Width <= 32 && "Width too large");
214 unsigned Digits = (Width + 3) / 4;
215 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
216 unsigned Value = 0;
217 for (unsigned j = 0; j != Width && i + j != e; ++j)
218 Value |= Bits.test(i + j) << j;
219 OS << format("0x%0*x, ", Digits, Value);
220 }
221 }
222
223 // Helper to emit a set of bits into a constant byte array.
224 class BitVectorEmitter {
225 BitVector Values;
226 public:
add(unsigned v)227 void add(unsigned v) {
228 if (v >= Values.size())
229 Values.resize(((v/8)+1)*8); // Round up to the next byte.
230 Values[v] = true;
231 }
232
print(raw_ostream & OS)233 void print(raw_ostream &OS) {
234 printBitVectorAsHex(OS, Values, 8);
235 }
236 };
237
238 //
239 // runMCDesc - Print out MC register descriptions.
240 //
241 void
runMCDesc(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank)242 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
243 CodeGenRegBank &RegBank) {
244 EmitSourceFileHeader("MC Register Information", OS);
245
246 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
247 OS << "#undef GET_REGINFO_MC_DESC\n";
248
249 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
250 RegBank.computeOverlaps(Overlaps);
251
252 OS << "namespace llvm {\n\n";
253
254 const std::string &TargetName = Target.getName();
255 std::string ClassName = TargetName + "GenMCRegisterInfo";
256 OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
257 << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
258 OS << "};\n";
259
260 OS << "\nnamespace {\n";
261
262 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
263
264 // Emit an overlap list for all registers.
265 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
266 const CodeGenRegister *Reg = Regs[i];
267 const CodeGenRegister::Set &O = Overlaps[Reg];
268 // Move Reg to the front so TRI::getAliasSet can share the list.
269 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
270 << getQualifiedName(Reg->TheDef) << ", ";
271 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
272 I != E; ++I)
273 if (*I != Reg)
274 OS << getQualifiedName((*I)->TheDef) << ", ";
275 OS << "0 };\n";
276 }
277
278 // Emit the empty sub-registers list
279 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
280 // Loop over all of the registers which have sub-registers, emitting the
281 // sub-registers list to memory.
282 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
283 const CodeGenRegister &Reg = *Regs[i];
284 if (Reg.getSubRegs().empty())
285 continue;
286 // getSubRegs() orders by SubRegIndex. We want a topological order.
287 SetVector<CodeGenRegister*> SR;
288 Reg.addSubRegsPreOrder(SR);
289 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
290 for (unsigned j = 0, je = SR.size(); j != je; ++j)
291 OS << getQualifiedName(SR[j]->TheDef) << ", ";
292 OS << "0 };\n";
293 }
294
295 // Emit the empty super-registers list
296 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
297 // Loop over all of the registers which have super-registers, emitting the
298 // super-registers list to memory.
299 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
300 const CodeGenRegister &Reg = *Regs[i];
301 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
302 if (SR.empty())
303 continue;
304 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
305 for (unsigned j = 0, je = SR.size(); j != je; ++j)
306 OS << getQualifiedName(SR[j]->TheDef) << ", ";
307 OS << "0 };\n";
308 }
309 OS << "}\n"; // End of anonymous namespace...
310
311 OS << "\nMCRegisterDesc " << TargetName
312 << "RegDesc[] = { // Descriptors\n";
313 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
314
315 // Now that register alias and sub-registers sets have been emitted, emit the
316 // register descriptors now.
317 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
318 const CodeGenRegister &Reg = *Regs[i];
319 OS << " { \"";
320 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
321 if (!Reg.getSubRegs().empty())
322 OS << Reg.getName() << "_SubRegsSet,\t";
323 else
324 OS << "Empty_SubRegsSet,\t";
325 if (!Reg.getSuperRegs().empty())
326 OS << Reg.getName() << "_SuperRegsSet";
327 else
328 OS << "Empty_SuperRegsSet";
329 OS << " },\n";
330 }
331 OS << "};\n\n"; // End of register descriptors...
332
333 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
334
335 // Loop over all of the register classes... emitting each one.
336 OS << "namespace { // Register classes...\n";
337
338 // Emit the register enum value arrays for each RegisterClass
339 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
340 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
341 ArrayRef<Record*> Order = RC.getOrder();
342
343 // Give the register class a legal C name if it's anonymous.
344 std::string Name = RC.getName();
345
346 // Emit the register list now.
347 OS << " // " << Name << " Register Class...\n"
348 << " static const unsigned " << Name
349 << "[] = {\n ";
350 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
351 Record *Reg = Order[i];
352 OS << getQualifiedName(Reg) << ", ";
353 }
354 OS << "\n };\n\n";
355
356 OS << " // " << Name << " Bit set.\n"
357 << " static const unsigned char " << Name
358 << "Bits[] = {\n ";
359 BitVectorEmitter BVE;
360 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
361 Record *Reg = Order[i];
362 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
363 }
364 BVE.print(OS);
365 OS << "\n };\n\n";
366
367 }
368 OS << "}\n\n";
369
370 OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n";
371
372 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
373 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
374 OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", "
375 << '\"' << RC.getName() << "\", "
376 << RC.SpillSize/8 << ", "
377 << RC.SpillAlignment/8 << ", "
378 << RC.CopyCost << ", "
379 << RC.Allocatable << ", "
380 << RC.getName() << ", " << RC.getName() << " + "
381 << RC.getOrder().size() << ", "
382 << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)"
383 << "),\n";
384 }
385
386 OS << "};\n\n";
387
388 // MCRegisterInfo initialization routine.
389 OS << "static inline void Init" << TargetName
390 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
391 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
392 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
393 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
394 << RegisterClasses.size() << ");\n\n";
395
396 EmitRegMapping(OS, Regs, false);
397
398 OS << "}\n\n";
399
400
401 OS << "} // End llvm namespace \n";
402 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
403 }
404
405 void
runTargetHeader(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank)406 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
407 CodeGenRegBank &RegBank) {
408 EmitSourceFileHeader("Register Information Header Fragment", OS);
409
410 OS << "\n#ifdef GET_REGINFO_HEADER\n";
411 OS << "#undef GET_REGINFO_HEADER\n";
412
413 const std::string &TargetName = Target.getName();
414 std::string ClassName = TargetName + "GenRegisterInfo";
415
416 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
417 OS << "#include <string>\n\n";
418
419 OS << "namespace llvm {\n\n";
420
421 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
422 << " explicit " << ClassName
423 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
424 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
425 << " { return false; }\n"
426 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
427 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
428 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
429 << " const TargetRegisterClass *"
430 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
431 << "};\n\n";
432
433 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
434 if (!SubRegIndices.empty()) {
435 OS << "\n// Subregister indices\n";
436 std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
437 if (!Namespace.empty())
438 OS << "namespace " << Namespace << " {\n";
439 OS << "enum {\n NoSubRegister,\n";
440 for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
441 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
442 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
443 OS << "};\n";
444 if (!Namespace.empty())
445 OS << "}\n";
446 }
447
448 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
449
450 if (!RegisterClasses.empty()) {
451 OS << "namespace " << RegisterClasses[0]->Namespace
452 << " { // Register classes\n";
453
454 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
455 const CodeGenRegisterClass &RC = *RegisterClasses[i];
456 const std::string &Name = RC.getName();
457
458 // Output the register class definition.
459 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
460 << " " << Name << "Class();\n";
461 if (!RC.AltOrderSelect.empty())
462 OS << " ArrayRef<unsigned> "
463 "getRawAllocationOrder(const MachineFunction&) const;\n";
464 OS << " };\n";
465
466 // Output the extern for the instance.
467 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
468 // Output the extern for the pointer to the instance (should remove).
469 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
470 << Name << "RegClass;\n";
471 }
472 OS << "} // end of namespace " << TargetName << "\n\n";
473 }
474 OS << "} // End llvm namespace \n";
475 OS << "#endif // GET_REGINFO_HEADER\n\n";
476 }
477
478 //
479 // runTargetDesc - Output the target register and register file descriptions.
480 //
481 void
runTargetDesc(raw_ostream & OS,CodeGenTarget & Target,CodeGenRegBank & RegBank)482 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
483 CodeGenRegBank &RegBank){
484 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
485
486 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
487 OS << "#undef GET_REGINFO_TARGET_DESC\n";
488
489 OS << "namespace llvm {\n\n";
490
491 // Get access to MCRegisterClass data.
492 OS << "extern MCRegisterClass " << Target.getName()
493 << "MCRegisterClasses[];\n";
494
495 // Start out by emitting each of the register classes.
496 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
497
498 // Collect all registers belonging to any allocatable class.
499 std::set<Record*> AllocatableRegs;
500
501 // Collect allocatable registers.
502 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
503 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
504 ArrayRef<Record*> Order = RC.getOrder();
505
506 if (RC.Allocatable)
507 AllocatableRegs.insert(Order.begin(), Order.end());
508 }
509
510 OS << "namespace { // Register classes...\n";
511
512 // Emit the ValueType arrays for each RegisterClass
513 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
514 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
515
516 // Give the register class a legal C name if it's anonymous.
517 std::string Name = RC.getName() + "VTs";
518
519 // Emit the register list now.
520 OS << " // " << Name
521 << " Register Class Value Types...\n"
522 << " static const EVT " << Name
523 << "[] = {\n ";
524 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
525 OS << getEnumName(RC.VTs[i]) << ", ";
526 OS << "MVT::Other\n };\n\n";
527 }
528 OS << "} // end anonymous namespace\n\n";
529
530 // Now that all of the structs have been emitted, emit the instances.
531 if (!RegisterClasses.empty()) {
532 OS << "namespace " << RegisterClasses[0]->Namespace
533 << " { // Register class instances\n";
534 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
535 OS << " " << RegisterClasses[i]->getName() << "Class\t"
536 << RegisterClasses[i]->getName() << "RegClass;\n";
537
538 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
539
540 OS << "\n static const TargetRegisterClass* const "
541 << "NullRegClasses[] = { NULL };\n\n";
542
543 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
544
545 if (NumSubRegIndices) {
546 // Compute the super-register classes for each RegisterClass
547 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
548 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
549 for (DenseMap<Record*,Record*>::const_iterator
550 i = RC.SubRegClasses.begin(),
551 e = RC.SubRegClasses.end(); i != e; ++i) {
552 // Find the register class number of i->second for SuperRegClassMap.
553 const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
554 assert(RC2 && "Invalid register class in SubRegClasses");
555 SuperRegClassMap[RC2->EnumValue].insert(rc);
556 }
557 }
558
559 // Emit the super-register classes for each RegisterClass
560 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
561 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
562
563 // Give the register class a legal C name if it's anonymous.
564 std::string Name = RC.getName();
565
566 OS << " // " << Name
567 << " Super-register Classes...\n"
568 << " static const TargetRegisterClass* const "
569 << Name << "SuperRegClasses[] = {\n ";
570
571 bool Empty = true;
572 std::map<unsigned, std::set<unsigned> >::iterator I =
573 SuperRegClassMap.find(rc);
574 if (I != SuperRegClassMap.end()) {
575 for (std::set<unsigned>::iterator II = I->second.begin(),
576 EE = I->second.end(); II != EE; ++II) {
577 const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
578 if (!Empty)
579 OS << ", ";
580 OS << "&" << RC2.getQualifiedName() << "RegClass";
581 Empty = false;
582 }
583 }
584
585 OS << (!Empty ? ", " : "") << "NULL";
586 OS << "\n };\n\n";
587 }
588 }
589
590 // Emit the sub-classes array for each RegisterClass
591 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
592 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
593
594 // Give the register class a legal C name if it's anonymous.
595 std::string Name = RC.getName();
596
597 OS << " static const unsigned " << Name << "SubclassMask[] = { ";
598 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
599 OS << "};\n\n";
600 }
601
602 // Emit NULL terminated super-class lists.
603 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
604 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
605 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
606
607 // Skip classes without supers. We can reuse NullRegClasses.
608 if (Supers.empty())
609 continue;
610
611 OS << " static const TargetRegisterClass* const "
612 << RC.getName() << "Superclasses[] = {\n";
613 for (unsigned i = 0; i != Supers.size(); ++i)
614 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
615 OS << " NULL\n };\n\n";
616 }
617
618 // Emit methods.
619 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
620 const CodeGenRegisterClass &RC = *RegisterClasses[i];
621 OS << RC.getName() << "Class::" << RC.getName()
622 << "Class() : TargetRegisterClass(&"
623 << Target.getName() << "MCRegisterClasses["
624 << RC.getName() + "RegClassID" << "], "
625 << RC.getName() + "VTs" << ", "
626 << RC.getName() + "SubclassMask" << ", ";
627 if (RC.getSuperClasses().empty())
628 OS << "NullRegClasses, ";
629 else
630 OS << RC.getName() + "Superclasses, ";
631 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
632 << "RegClasses"
633 << ") {}\n";
634 if (!RC.AltOrderSelect.empty()) {
635 OS << "\nstatic inline unsigned " << RC.getName()
636 << "AltOrderSelect(const MachineFunction &MF) {"
637 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
638 << RC.getName() << "Class::"
639 << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
640 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
641 ArrayRef<Record*> Elems = RC.getOrder(oi);
642 OS << " static const unsigned AltOrder" << oi << "[] = {";
643 for (unsigned elem = 0; elem != Elems.size(); ++elem)
644 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
645 OS << " };\n";
646 }
647 OS << " const MCRegisterClass &MCR = " << Target.getName()
648 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];"
649 << " static const ArrayRef<unsigned> Order[] = {\n"
650 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
651 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
652 OS << "),\n makeArrayRef(AltOrder" << oi;
653 OS << ")\n };\n const unsigned Select = " << RC.getName()
654 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
655 << ");\n return Order[Select];\n}\n";
656 }
657 }
658
659 OS << "}\n";
660 }
661
662 OS << "\nnamespace {\n";
663 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
664 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
665 OS << " &" << RegisterClasses[i]->getQualifiedName()
666 << "RegClass,\n";
667 OS << " };\n";
668 OS << "}\n"; // End of anonymous namespace...
669
670 // Emit extra information about registers.
671 const std::string &TargetName = Target.getName();
672 OS << "\n static const TargetRegisterInfoDesc "
673 << TargetName << "RegInfoDesc[] = "
674 << "{ // Extra Descriptors\n";
675 OS << " { 0, 0 },\n";
676
677 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
678 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
679 const CodeGenRegister &Reg = *Regs[i];
680 OS << " { ";
681 OS << Reg.CostPerUse << ", "
682 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
683 }
684 OS << " };\n"; // End of register descriptors...
685
686
687 // Calculate the mapping of subregister+index pairs to physical registers.
688 // This will also create further anonymous indexes.
689 unsigned NamedIndices = RegBank.getNumNamedIndices();
690
691 // Emit SubRegIndex names, skipping 0
692 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
693 OS << "\n static const char *const " << TargetName
694 << "SubRegIndexTable[] = { \"";
695 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
696 OS << SubRegIndices[i]->getName();
697 if (i+1 != e)
698 OS << "\", \"";
699 }
700 OS << "\" };\n\n";
701
702 // Emit names of the anonymus subreg indexes.
703 if (SubRegIndices.size() > NamedIndices) {
704 OS << " enum {";
705 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
706 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
707 if (i+1 != e)
708 OS << ',';
709 }
710 OS << "\n };\n\n";
711 }
712 OS << "\n";
713
714 std::string ClassName = Target.getName() + "GenRegisterInfo";
715
716 // Emit the subregister + index mapping function based on the information
717 // calculated above.
718 OS << "unsigned " << ClassName
719 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
720 << " switch (RegNo) {\n"
721 << " default:\n return 0;\n";
722 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
723 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
724 if (SRM.empty())
725 continue;
726 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
727 OS << " switch (Index) {\n";
728 OS << " default: return 0;\n";
729 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
730 ie = SRM.end(); ii != ie; ++ii)
731 OS << " case " << getQualifiedName(ii->first)
732 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
733 OS << " };\n" << " break;\n";
734 }
735 OS << " };\n";
736 OS << " return 0;\n";
737 OS << "}\n\n";
738
739 OS << "unsigned " << ClassName
740 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
741 << " switch (RegNo) {\n"
742 << " default:\n return 0;\n";
743 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
744 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
745 if (SRM.empty())
746 continue;
747 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
748 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
749 ie = SRM.end(); ii != ie; ++ii)
750 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
751 << ") return " << getQualifiedName(ii->first) << ";\n";
752 OS << " return 0;\n";
753 }
754 OS << " };\n";
755 OS << " return 0;\n";
756 OS << "}\n\n";
757
758 // Emit composeSubRegIndices
759 OS << "unsigned " << ClassName
760 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
761 << " switch (IdxA) {\n"
762 << " default:\n return IdxB;\n";
763 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
764 bool Open = false;
765 for (unsigned j = 0; j != e; ++j) {
766 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
767 SubRegIndices[j])) {
768 if (!Open) {
769 OS << " case " << getQualifiedName(SubRegIndices[i])
770 << ": switch(IdxB) {\n default: return IdxB;\n";
771 Open = true;
772 }
773 OS << " case " << getQualifiedName(SubRegIndices[j])
774 << ": return " << getQualifiedName(Comp) << ";\n";
775 }
776 }
777 if (Open)
778 OS << " }\n";
779 }
780 OS << " }\n}\n\n";
781
782 // Emit getSubClassWithSubReg.
783 OS << "const TargetRegisterClass *" << ClassName
784 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
785 " const {\n";
786 if (SubRegIndices.empty()) {
787 OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n"
788 << " return RC;\n";
789 } else {
790 // Use the smallest type that can hold a regclass ID with room for a
791 // sentinel.
792 if (RegisterClasses.size() < UINT8_MAX)
793 OS << " static const uint8_t Table[";
794 else if (RegisterClasses.size() < UINT16_MAX)
795 OS << " static const uint16_t Table[";
796 else
797 throw "Too many register classes.";
798 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
799 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
800 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
801 OS << " {\t// " << RC.getName() << "\n";
802 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
803 Record *Idx = SubRegIndices[sri];
804 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
805 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
806 << " -> " << SRC->getName() << "\n";
807 else
808 OS << " 0,\t// " << Idx->getName() << "\n";
809 }
810 OS << " },\n";
811 }
812 OS << " };\n assert(RC && \"Missing regclass\");\n"
813 << " if (!Idx) return RC;\n --Idx;\n"
814 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
815 << " unsigned TV = Table[RC->getID()][Idx];\n"
816 << " return TV ? getRegClass(TV - 1) : 0;\n";
817 }
818 OS << "}\n\n";
819
820 // Emit the constructor of the class...
821 OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
822
823 OS << ClassName << "::" << ClassName
824 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
825 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
826 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
827 << " " << TargetName << "SubRegIndexTable) {\n"
828 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
829 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
830 << RegisterClasses.size() << ");\n\n";
831
832 EmitRegMapping(OS, Regs, true);
833
834 OS << "}\n\n";
835
836 OS << "} // End llvm namespace \n";
837 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
838 }
839
run(raw_ostream & OS)840 void RegisterInfoEmitter::run(raw_ostream &OS) {
841 CodeGenTarget Target(Records);
842 CodeGenRegBank &RegBank = Target.getRegBank();
843 RegBank.computeDerivedInfo();
844
845 runEnums(OS, Target, RegBank);
846 runMCDesc(OS, Target, RegBank);
847 runTargetHeader(OS, Target, RegBank);
848 runTargetDesc(OS, Target, RegBank);
849 }
850