Searched defs:sunxi_mctl_ctl_reg (Results 1 – 6 of 6) sorted by relevance
65 struct sunxi_mctl_ctl_reg { struct66 u32 pir; /* 0x00 */67 u32 pwrctl; /* 0x04 */68 u32 mrctrl0; /* 0x08 */69 u32 clken; /* 0x0c */70 u32 pgsr0; /* 0x10 */71 u32 pgsr1; /* 0x14 */72 u32 statr; /* 0x18 */73 u8 res1[0x14]; /* 0x1c */74 u32 mr0; /* 0x30 */[all …]
40 struct sunxi_mctl_ctl_reg { struct41 u8 res0[0x04]; /* 0x00 */42 u32 sctl; /* 0x04 */43 u32 sstat; /* 0x08 */44 u8 res1[0x34]; /* 0x0c */45 u32 mcmd; /* 0x40 */46 u8 res2[0x08]; /* 0x44 */47 u32 cmdstat; /* 0x4c */48 u32 cmdstaten; /* 0x50 */49 u8 res3[0x0c]; /* 0x54 */[all …]
81 struct sunxi_mctl_ctl_reg { struct82 u32 pir; /* 0x00 PHY initialization register */83 u32 pwrctl; /* 0x04 */84 u32 mrctrl; /* 0x08 */85 u32 clken; /* 0x0c */86 u32 pgsr[2]; /* 0x10 PHY general status registers */87 u32 statr; /* 0x18 */88 u8 res1[0x10]; /* 0x1c */89 u32 lp3mr11; /* 0x2c */90 u32 mr[4]; /* 0x30 mode registers */[all …]
91 struct sunxi_mctl_ctl_reg { struct92 u32 mstr; /* 0x00 */93 u32 statr; /* 0x04 */94 u8 res0[0x08]; /* 0x08 */95 u32 mrctrl0; /* 0x10 */96 u32 mrctrl1; /* 0x14 */97 u32 mrstatr; /* 0x18 */98 u8 res1[0x04]; /* 0x1c */99 u32 derateen; /* 0x20 */100 u32 deratenint; /* 0x24 */[all …]
40 struct sunxi_mctl_ctl_reg { struct41 u32 mstr; /* 0x00 master register */42 u32 stat; /* 0x04 operating mode status register */43 u8 res1[0x8]; /* 0x08 */44 u32 mrctrl[2]; /* 0x10 mode register read/write control reg */45 u32 mstat; /* 0x18 mode register read/write status reg */46 u8 res2[0x4]; /* 0x1c */47 u32 derateen; /* 0x20 temperature derate enable register */48 u32 derateint; /* 0x24 temperature derate interval register */49 u8 res3[0x8]; /* 0x28 */[all …]