| /external/v8/src/compiler/arm/ |
| D | code-generator-arm.cc | 1215 __ teq(i.InputRegister(0), i.InputOperand2(1)); in AssembleArchInstruction() local
2785 __ teq(i.TempRegister(1), Operand(0)); in AssembleArchInstruction() local
2814 __ teq(i.TempRegister(1), Operand(0)); in AssembleArchInstruction() local
2826 __ teq(i.InputRegister(0), Operand(i.OutputRegister(0))); in AssembleArchInstruction() local
2828 __ teq(i.InputRegister(1), Operand(i.OutputRegister(1))); in AssembleArchInstruction() local
2832 __ teq(i.TempRegister(1), Operand(0)); in AssembleArchInstruction() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips/ |
| D | valid.s | 246 teq $8, $9 # CHECK: teq $8, $9 # encoding: [0x01,0x28,0x00,0x3c] label
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 1148 void AssemblerMIPS32::teq(const Operand *OpRs, const Operand *OpRt, in teq() function in Ice::MIPS32::AssemblerMIPS32
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.cc | 263 void Assembler::teq(Register rn, Operand o, Condition cond) { in teq() function in dart::Assembler
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| /external/v8/src/mips/ |
| D | assembler-mips.cc | 2436 void Assembler::teq(Register rs, Register rt, uint16_t code) { in teq() function in v8::internal::Assembler
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| /external/v8/src/mips64/ |
| D | assembler-mips64.cc | 2680 void Assembler::teq(Register rs, Register rt, uint16_t code) { in teq() function in v8::internal::Assembler
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| /external/v8/src/arm/ |
| D | assembler-arm.cc | 1551 void Assembler::teq(Register src1, const Operand& src2, Condition cond) { in teq() function in v8::internal::Assembler
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3601 void teq(Register rn, const Operand& operand) { teq(al, rn, operand); } in teq() function
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| D | assembler-aarch32.cc | 12755 void Assembler::teq(Condition cond, Register rn, const Operand& operand) { in teq() function in vixl::aarch32::Assembler
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| D | disasm-aarch32.cc | 3309 void Disassembler::teq(Condition cond, Register rn, const Operand& operand) { in teq() function in vixl::aarch32::Disassembler
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