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/external/webrtc/webrtc/modules/audio_processing/ns/
Dwindows_private.h15 static const float kHanning64w128[128] = {
64 static const float kBlocks80w128[128] = {
65 (float)0.00000000, (float)0.03271908, (float)0.06540313, (float)0.09801714, (float)0.13052619,
66 (float)0.16289547, (float)0.19509032, (float)0.22707626, (float)0.25881905, (float)0.29028468,
67 (float)0.32143947, (float)0.35225005, (float)0.38268343, (float)0.41270703, (float)0.44228869,
68 (float)0.47139674, (float)0.50000000, (float)0.52806785, (float)0.55557023, (float)0.58247770,
69 (float)0.60876143, (float)0.63439328, (float)0.65934582, (float)0.68359230, (float)0.70710678,
70 (float)0.72986407, (float)0.75183981, (float)0.77301045, (float)0.79335334, (float)0.81284668,
71 (float)0.83146961, (float)0.84920218, (float)0.86602540, (float)0.88192126, (float)0.89687274,
72 (float)0.91086382, (float)0.92387953, (float)0.93590593, (float)0.94693013, (float)0.95694034,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dscratch-simple.ll21 define amdgpu_ps float @ps_main(i32 %idx) {
22 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
23 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
24 %r = fadd float %v1, %v2
25 ret float %r
33 define amdgpu_vs float @vs_main(i32 %idx) {
34 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
35 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
36 %r = fadd float %v1, %v2
37 ret float %r
[all …]
Dschedule-ilp.ll5 define amdgpu_kernel void @load_fma_store(float addrspace(3)* nocapture readonly %arg, float addrsp…
7 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 1
8 %tmp2 = load float, float addrspace(3)* %tmp, align 4
9 %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 2
10 %tmp4 = load float, float addrspace(3)* %tmp3, align 4
11 %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 3
12 %tmp6 = load float, float addrspace(3)* %tmp5, align 4
13 %tmp7 = tail call float @llvm.fmuladd.f32(float %tmp2, float %tmp4, float %tmp6)
14 %tmp8 = getelementptr inbounds float, float addrspace(3)* %arg, i32 5
15 %tmp9 = load float, float addrspace(3)* %tmp8, align 4
[all …]
Dschedule-regpressure-limit3.ll7 define amdgpu_kernel void @load_fma_store(float addrspace(3)* nocapture readonly %arg, float addrsp…
9 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 1
10 %tmp2 = load float, float addrspace(3)* %tmp, align 4
11 %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 2
12 %tmp4 = load float, float addrspace(3)* %tmp3, align 4
13 %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 3
14 %tmp6 = load float, float addrspace(3)* %tmp5, align 4
15 %tmp7 = tail call float @llvm.fmuladd.f32(float %tmp2, float %tmp4, float %tmp6)
16 %tmp8 = getelementptr inbounds float, float addrspace(3)* %arg, i32 5
17 %tmp9 = load float, float addrspace(3)* %tmp8, align 4
[all …]
Dschedule-regpressure-limit.ll8 define amdgpu_kernel void @load_fma_store(float addrspace(3)* nocapture readonly %arg, float addrsp…
10 %tmp = getelementptr inbounds float, float addrspace(3)* %arg, i32 1
11 %tmp2 = load float, float addrspace(3)* %tmp, align 4
12 %tmp3 = getelementptr inbounds float, float addrspace(3)* %arg, i32 2
13 %tmp4 = load float, float addrspace(3)* %tmp3, align 4
14 %tmp5 = getelementptr inbounds float, float addrspace(3)* %arg, i32 3
15 %tmp6 = load float, float addrspace(3)* %tmp5, align 4
16 %tmp7 = tail call float @llvm.fmuladd.f32(float %tmp2, float %tmp4, float %tmp6)
17 %tmp8 = getelementptr inbounds float, float addrspace(3)* %arg, i32 5
18 %tmp9 = load float, float addrspace(3)* %tmp8, align 4
[all …]
Dbig_alu.ll5 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 …
7 %tmp = extractelement <4 x float> %reg0, i32 0
8 %tmp1 = extractelement <4 x float> %reg0, i32 1
9 %tmp2 = extractelement <4 x float> %reg0, i32 2
10 %tmp3 = extractelement <4 x float> %reg0, i32 3
11 %tmp4 = extractelement <4 x float> %reg1, i32 0
12 %tmp5 = extractelement <4 x float> %reg9, i32 0
13 %tmp6 = extractelement <4 x float> %reg8, i32 0
14 %tmp7 = fcmp ugt float %tmp6, 0.000000e+00
15 %tmp8 = select i1 %tmp7, float %tmp4, float %tmp5
[all …]
Dwaitcnt-looptest.ll15 …float] [float 0.000000e+00, float 0x3FB99999A0000000, float 0x3FC99999A0000000, float 0x3FD3333340…
16 …float] [float 0.000000e+00, float 0x3FB99999A0000000, float 0x3FC99999A0000000, float 0x3FD3333340…
20 …float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 …
21 …float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 …
49 …%tmp22 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i…
50 %tmp23 = load float, float addrspace(1)* %tmp22, align 4
51 …%tmp24 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_reference, i64 0,…
52 %tmp25 = load float, float addrspace(1)* %tmp24, align 4
53 %tmp26 = fcmp oeq float %tmp23, %tmp25
57 …%tmp30 = getelementptr inbounds [100 x float], [100 x float] addrspace(1)* @data_generic, i64 0, i…
[all …]
Dschedule-regpressure-limit2.ll16 define amdgpu_kernel void @load_fma_store(float addrspace(3)* nocapture readonly %in_arg, float add…
18 %adr.a.0 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 20004
19 %adr.b.0 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 20252
20 %adr.c.0 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 20508
21 %adr.a.1 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 20772
22 %adr.b.1 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 21020
23 %adr.c.1 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 21276
24 %adr.a.2 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 21540
25 %adr.b.2 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 21788
26 %adr.c.2 = getelementptr inbounds float, float addrspace(3)* %in_arg, i32 22044
[all …]
/external/llvm/test/CodeGen/X86/
Dlarge-gep-chain.ll4 %0 = type { i32, float* }
24 %tmp = getelementptr inbounds float, float* null, i64 1
25 %tmp3 = getelementptr inbounds float, float* %tmp, i64 1
26 %tmp4 = getelementptr inbounds float, float* %tmp3, i64 1
27 %tmp5 = getelementptr inbounds float, float* %tmp4, i64 1
28 %tmp6 = getelementptr inbounds float, float* %tmp5, i64 1
29 %tmp7 = getelementptr inbounds float, float* %tmp6, i64 1
30 %tmp8 = getelementptr inbounds float, float* %tmp7, i64 1
31 %tmp9 = getelementptr inbounds float, float* %tmp8, i64 1
32 %tmp10 = getelementptr inbounds float, float* %tmp9, i64 1
[all …]
D2008-07-19-movups-spills.ll7 @0 = external global <4 x float>, align 1 ; <<4 x float>*>:0 [#uses=2]
8 @1 = external global <4 x float>, align 1 ; <<4 x float>*>:1 [#uses=1]
9 @2 = external global <4 x float>, align 1 ; <<4 x float>*>:2 [#uses=1]
10 @3 = external global <4 x float>, align 1 ; <<4 x float>*>:3 [#uses=1]
11 @4 = external global <4 x float>, align 1 ; <<4 x float>*>:4 [#uses=1]
12 @5 = external global <4 x float>, align 1 ; <<4 x float>*>:5 [#uses=1]
13 @6 = external global <4 x float>, align 1 ; <<4 x float>*>:6 [#uses=1]
14 @7 = external global <4 x float>, align 1 ; <<4 x float>*>:7 [#uses=1]
15 @8 = external global <4 x float>, align 1 ; <<4 x float>*>:8 [#uses=1]
16 @9 = external global <4 x float>, align 1 ; <<4 x float>*>:9 [#uses=1]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dlarge-gep-chain.ll4 %0 = type { i32, float* }
24 %tmp = getelementptr inbounds float, float* null, i64 1
25 %tmp3 = getelementptr inbounds float, float* %tmp, i64 1
26 %tmp4 = getelementptr inbounds float, float* %tmp3, i64 1
27 %tmp5 = getelementptr inbounds float, float* %tmp4, i64 1
28 %tmp6 = getelementptr inbounds float, float* %tmp5, i64 1
29 %tmp7 = getelementptr inbounds float, float* %tmp6, i64 1
30 %tmp8 = getelementptr inbounds float, float* %tmp7, i64 1
31 %tmp9 = getelementptr inbounds float, float* %tmp8, i64 1
32 %tmp10 = getelementptr inbounds float, float* %tmp9, i64 1
[all …]
D2008-07-19-movups-spills.ll7 @0 = external global <4 x float>, align 1 ; <<4 x float>*>:0 [#uses=2]
8 @1 = external global <4 x float>, align 1 ; <<4 x float>*>:1 [#uses=1]
9 @2 = external global <4 x float>, align 1 ; <<4 x float>*>:2 [#uses=1]
10 @3 = external global <4 x float>, align 1 ; <<4 x float>*>:3 [#uses=1]
11 @4 = external global <4 x float>, align 1 ; <<4 x float>*>:4 [#uses=1]
12 @5 = external global <4 x float>, align 1 ; <<4 x float>*>:5 [#uses=1]
13 @6 = external global <4 x float>, align 1 ; <<4 x float>*>:6 [#uses=1]
14 @7 = external global <4 x float>, align 1 ; <<4 x float>*>:7 [#uses=1]
15 @8 = external global <4 x float>, align 1 ; <<4 x float>*>:8 [#uses=1]
16 @9 = external global <4 x float>, align 1 ; <<4 x float>*>:9 [#uses=1]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/
Dx86-sse.ll5 define float @test_rcp_ss_0(float %a) {
7 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
8 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP1]])
9 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
10 ; CHECK-NEXT: ret float [[TMP3]]
12 %1 = insertelement <4 x float> undef, float %a, i32 0
13 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
14 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
15 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
16 %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4)
[all …]
/external/llvm/test/Transforms/InstCombine/
Dminnum.ll3 declare float @llvm.minnum.f32(float, float) #0
4 declare float @llvm.minnum.v2f32(<2 x float>, <2 x float>) #0
5 declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #0
10 declare float @llvm.maxnum.f32(float, float) #0
13 ; CHECK-NEXT: ret float 1.000000e+00
14 define float @constant_fold_minnum_f32() #0 {
15 %x = call float @llvm.minnum.f32(float 1.0, float 2.0) #0
16 ret float %x
20 ; CHECK-NEXT: ret float 1.000000e+00
21 define float @constant_fold_minnum_f32_inv() #0 {
[all …]
Dx86-sse.ll5 define float @test_rcp_ss_0(float %a) {
7 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
8 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP1]])
9 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
10 ; CHECK-NEXT: ret float [[TMP3]]
12 %1 = insertelement <4 x float> undef, float %a, i32 0
13 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
14 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
15 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
16 %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dfma.ll4 declare float @llvm.fma.f32(float, float, float) #1
5 declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
6 declare float @llvm.fmuladd.f32(float, float, float) #1
7 declare float @llvm.fabs.f32(float) #1
11 define float @fma_fneg_x_fneg_y(float %x, float %y, float %z) {
13 ; CHECK-NEXT: [[FMA:%.*]] = call float @llvm.fma.f32(float [[X:%.*]], float [[Y:%.*]], float [[Z…
14 ; CHECK-NEXT: ret float [[FMA]]
16 %x.fneg = fsub float -0.0, %x
17 %y.fneg = fsub float -0.0, %y
18 %fma = call float @llvm.fma.f32(float %x.fneg, float %y.fneg, float %z)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
D2003-05-28-ManyArgs.ll21 %struct..s_annealing_sched = type { i32, float, float, float, float }
22 %struct..s_chan = type { i32, float, float, float, float }
23 …%struct..s_det_routing_arch = type { i32, float, float, float, i32, i32, i16, i16, i16, float, flo…
24 %struct..s_placer_opts = type { i32, float, i32, i32, i8*, i32, i32 }
25 %struct..s_router_opts = type { float, float, float, float, float, i32, i32, i32, i32 }
26 %struct..s_segment_inf = type { float, i32, i16, i16, float, float, i32, float, float }
27 %struct..s_switch_inf = type { i32, float, float, float, float }
44 … float, float, float, float, float, float, float, float, float, float } ; <{ i32, float, float, f…
50 …2, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, fl…
56 …tr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 1 ; <float*> [#uses=1]
[all …]
/external/llvm/test/CodeGen/Generic/
D2003-05-28-ManyArgs.ll21 %struct..s_annealing_sched = type { i32, float, float, float, float }
22 %struct..s_chan = type { i32, float, float, float, float }
23 …%struct..s_det_routing_arch = type { i32, float, float, float, i32, i32, i16, i16, i16, float, flo…
24 %struct..s_placer_opts = type { i32, float, i32, i32, i8*, i32, i32 }
25 %struct..s_router_opts = type { float, float, float, float, float, i32, i32, i32, i32 }
26 %struct..s_segment_inf = type { float, i32, i16, i16, float, float, i32, float, float }
27 %struct..s_switch_inf = type { i32, float, float, float, float }
44 … float, float, float, float, float, float, float, float, float, float } ; <{ i32, float, float, f…
50 …2, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, fl…
56 …tr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 1 ; <float*> [#uses=1]
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dlocal-stack-slot-bug.ll16 define amdgpu_ps float @main(i32 %idx) {
18 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
19 …float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef,…
20 %r = fadd float %v1, %v2
21 ret float %r
Dbig_alu.ll5 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 …
7 %tmp = extractelement <4 x float> %reg0, i32 0
8 %tmp1 = extractelement <4 x float> %reg0, i32 1
9 %tmp2 = extractelement <4 x float> %reg0, i32 2
10 %tmp3 = extractelement <4 x float> %reg0, i32 3
11 %tmp4 = extractelement <4 x float> %reg1, i32 0
12 %tmp5 = extractelement <4 x float> %reg9, i32 0
13 %tmp6 = extractelement <4 x float> %reg8, i32 0
14 %tmp7 = fcmp ugt float %tmp6, 0.000000e+00
15 %tmp8 = select i1 %tmp7, float %tmp4, float %tmp5
[all …]
Dvgpr-spill-emergency-stack-slot-compute.ll46 …void @spill_vgpr_compute(<4 x float> %arg6, float addrspace(1)* %arg, i32 %arg1, i32 %arg2, float …
49 %tmp7 = extractelement <4 x float> %arg6, i32 0
50 %tmp8 = extractelement <4 x float> %arg6, i32 1
51 %tmp9 = extractelement <4 x float> %arg6, i32 2
52 %tmp10 = extractelement <4 x float> %arg6, i32 3
53 %tmp11 = bitcast float %arg5 to i32
57 %tmp13 = phi float [ 0.000000e+00, %bb ], [ %tmp338, %bb145 ]
58 %tmp14 = phi float [ 0.000000e+00, %bb ], [ %tmp337, %bb145 ]
59 %tmp15 = phi float [ 0.000000e+00, %bb ], [ %tmp336, %bb145 ]
60 %tmp16 = phi float [ 0.000000e+00, %bb ], [ %tmp339, %bb145 ]
[all …]
Dpv.ll6 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 …
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
12 %4 = extractelement <4 x float> %reg2, i32 0
13 %5 = extractelement <4 x float> %reg2, i32 1
14 %6 = extractelement <4 x float> %reg2, i32 2
15 %7 = extractelement <4 x float> %reg2, i32 3
16 %8 = extractelement <4 x float> %reg3, i32 0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dlarge-number-of-preds.ll6 @g0 = external global void (float*, i32, i32, float*, float*)**
9 define void @f0(float* nocapture %a0, float* nocapture %a1, float* %a2) #0 {
11 %v0 = alloca [64 x float], align 16
12 %v1 = alloca [8 x float], align 8
13 %v2 = bitcast [64 x float]* %v0 to i8*
15 %v3 = load float, float* %a0, align 4, !tbaa !0
16 %v4 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 35
17 store float %v3, float* %v4, align 4, !tbaa !0
18 %v5 = getelementptr inbounds [64 x float], [64 x float]* %v0, i32 0, i32 0
19 store float %v3, float* %v5, align 16, !tbaa !0
[all …]
/external/llvm/test/Transforms/LoopReroll/
Dbasic32iters.ll5 ; void goo32(float alpha, float *a, float *b) {
43 define void @goo32(float %alpha, float* %a, float* readonly %b) #0 {
49 %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
50 %0 = load float, float* %arrayidx, align 4
51 %mul = fmul float %0, %alpha
52 %arrayidx2 = getelementptr inbounds float, float* %a, i64 %indvars.iv
53 %1 = load float, float* %arrayidx2, align 4
54 %add = fadd float %1, %mul
55 store float %add, float* %arrayidx2, align 4
57 %arrayidx5 = getelementptr inbounds float, float* %b, i64 %2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopReroll/
Dbasic32iters.ll5 ; void goo32(float alpha, float *a, float *b) {
43 define void @goo32(float %alpha, float* %a, float* readonly %b) #0 {
49 %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
50 %0 = load float, float* %arrayidx, align 4
51 %mul = fmul float %0, %alpha
52 %arrayidx2 = getelementptr inbounds float, float* %a, i64 %indvars.iv
53 %1 = load float, float* %arrayidx2, align 4
54 %add = fadd float %1, %mul
55 store float %add, float* %arrayidx2, align 4
57 %arrayidx5 = getelementptr inbounds float, float* %b, i64 %2
[all …]

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