1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Assembly Matcher Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_ASSEMBLER_HEADER 11#undef GET_ASSEMBLER_HEADER 12 // This should be included into the middle of the declaration of 13 // your subclasses implementation of MCTargetAsmParser. 14 uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const; 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 16 const OperandVector &Operands); 17 void convertToMapAndConstraints(unsigned Kind, 18 const OperandVector &Operands) override; 19 unsigned MatchInstructionImpl(const OperandVector &Operands, 20 MCInst &Inst, 21 SmallVectorImpl<NearMissInfo> *NearMisses, 22 bool matchingInlineAsm, 23 unsigned VariantID = 0); 24 OperandMatchResultTy MatchOperandParserImpl( 25 OperandVector &Operands, 26 StringRef Mnemonic, 27 bool ParseForAllFeatures = false); 28 OperandMatchResultTy tryCustomParseOperand( 29 OperandVector &Operands, 30 unsigned MCK); 31 32#endif // GET_ASSEMBLER_HEADER_INFO 33 34 35#ifdef GET_OPERAND_DIAGNOSTIC_TYPES 36#undef GET_OPERAND_DIAGNOSTIC_TYPES 37 38 Match_AlignedMemory16, 39 Match_AlignedMemory32, 40 Match_AlignedMemory64, 41 Match_AlignedMemory64or128, 42 Match_AlignedMemory64or128or256, 43 Match_AlignedMemoryNone, 44 Match_ComplexRotationEven, 45 Match_ComplexRotationOdd, 46 Match_DPR, 47 Match_DPR_8, 48 Match_DPR_RegList, 49 Match_DPR_VFP2, 50 Match_DupAlignedMemory16, 51 Match_DupAlignedMemory32, 52 Match_DupAlignedMemory64, 53 Match_DupAlignedMemory64or128, 54 Match_DupAlignedMemoryNone, 55 Match_GPR, 56 Match_GPRnopc, 57 Match_GPRsp, 58 Match_GPRwithAPSR, 59 Match_Imm0_1, 60 Match_Imm0_15, 61 Match_Imm0_239, 62 Match_Imm0_255, 63 Match_Imm0_3, 64 Match_Imm0_31, 65 Match_Imm0_32, 66 Match_Imm0_4095, 67 Match_Imm0_63, 68 Match_Imm0_65535, 69 Match_Imm0_65535Expr, 70 Match_Imm0_7, 71 Match_Imm16, 72 Match_Imm1_15, 73 Match_Imm1_31, 74 Match_Imm1_7, 75 Match_Imm24bit, 76 Match_Imm256_65535Expr, 77 Match_Imm32, 78 Match_Imm8, 79 Match_Imm8_255, 80 Match_ImmRange1_16, 81 Match_ImmRange1_32, 82 Match_ImmThumbSR, 83 Match_PKHLSLImm, 84 Match_QPR, 85 Match_QPR_8, 86 Match_QPR_VFP2, 87 Match_SPR, 88 Match_SPRRegList, 89 Match_SPR_8, 90 Match_SetEndImm, 91 Match_ShrImm16, 92 Match_ShrImm32, 93 Match_ShrImm64, 94 Match_ShrImm8, 95 Match_hGPR, 96 Match_rGPR, 97 Match_tGPR, 98 END_OPERAND_DIAGNOSTIC_TYPES 99#endif // GET_OPERAND_DIAGNOSTIC_TYPES 100 101 102#ifdef GET_REGISTER_MATCHER 103#undef GET_REGISTER_MATCHER 104 105// Flags for subtarget features that participate in instruction matching. 106enum SubtargetFeatureFlag : uint64_t { 107 Feature_HasV4T = (1ULL << 20), 108 Feature_HasV5T = (1ULL << 21), 109 Feature_HasV5TE = (1ULL << 22), 110 Feature_HasV6 = (1ULL << 23), 111 Feature_HasV6M = (1ULL << 25), 112 Feature_HasV8MBaseline = (1ULL << 30), 113 Feature_HasV8MMainline = (1ULL << 31), 114 Feature_HasV6T2 = (1ULL << 26), 115 Feature_HasV6K = (1ULL << 24), 116 Feature_HasV7 = (1ULL << 27), 117 Feature_HasV8 = (1ULL << 29), 118 Feature_PreV8 = (1ULL << 45), 119 Feature_HasV8_1a = (1ULL << 32), 120 Feature_HasV8_2a = (1ULL << 33), 121 Feature_HasV8_3a = (1ULL << 34), 122 Feature_HasV8_4a = (1ULL << 35), 123 Feature_HasVFP2 = (1ULL << 36), 124 Feature_HasVFP3 = (1ULL << 37), 125 Feature_HasVFP4 = (1ULL << 38), 126 Feature_HasDPVFP = (1ULL << 7), 127 Feature_HasFPARMv8 = (1ULL << 13), 128 Feature_HasNEON = (1ULL << 16), 129 Feature_HasSHA2 = (1ULL << 18), 130 Feature_HasAES = (1ULL << 1), 131 Feature_HasCrypto = (1ULL << 4), 132 Feature_HasDotProd = (1ULL << 11), 133 Feature_HasCRC = (1ULL << 3), 134 Feature_HasRAS = (1ULL << 17), 135 Feature_HasFP16 = (1ULL << 12), 136 Feature_HasFullFP16 = (1ULL << 14), 137 Feature_HasDivideInThumb = (1ULL << 10), 138 Feature_HasDivideInARM = (1ULL << 9), 139 Feature_HasDSP = (1ULL << 8), 140 Feature_HasDB = (1ULL << 5), 141 Feature_HasDFB = (1ULL << 6), 142 Feature_HasV7Clrex = (1ULL << 28), 143 Feature_HasAcquireRelease = (1ULL << 2), 144 Feature_HasMP = (1ULL << 15), 145 Feature_HasVirtualization = (1ULL << 39), 146 Feature_HasTrustZone = (1ULL << 19), 147 Feature_Has8MSecExt = (1ULL << 0), 148 Feature_IsThumb = (1ULL << 43), 149 Feature_IsThumb2 = (1ULL << 44), 150 Feature_IsMClass = (1ULL << 41), 151 Feature_IsNotMClass = (1ULL << 42), 152 Feature_IsARM = (1ULL << 40), 153 Feature_UseNaClTrap = (1ULL << 46), 154 Feature_UseNegativeImmediates = (1ULL << 47), 155 Feature_None = 0 156}; 157 158static unsigned MatchRegisterName(StringRef Name) { 159 switch (Name.size()) { 160 default: break; 161 case 2: // 43 strings to match. 162 switch (Name[0]) { 163 default: break; 164 case 'd': // 10 strings to match. 165 switch (Name[1]) { 166 default: break; 167 case '0': // 1 string to match. 168 return 14; // "d0" 169 case '1': // 1 string to match. 170 return 15; // "d1" 171 case '2': // 1 string to match. 172 return 16; // "d2" 173 case '3': // 1 string to match. 174 return 17; // "d3" 175 case '4': // 1 string to match. 176 return 18; // "d4" 177 case '5': // 1 string to match. 178 return 19; // "d5" 179 case '6': // 1 string to match. 180 return 20; // "d6" 181 case '7': // 1 string to match. 182 return 21; // "d7" 183 case '8': // 1 string to match. 184 return 22; // "d8" 185 case '9': // 1 string to match. 186 return 23; // "d9" 187 } 188 break; 189 case 'l': // 1 string to match. 190 if (Name[1] != 'r') 191 break; 192 return 10; // "lr" 193 case 'p': // 1 string to match. 194 if (Name[1] != 'c') 195 break; 196 return 11; // "pc" 197 case 'q': // 10 strings to match. 198 switch (Name[1]) { 199 default: break; 200 case '0': // 1 string to match. 201 return 50; // "q0" 202 case '1': // 1 string to match. 203 return 51; // "q1" 204 case '2': // 1 string to match. 205 return 52; // "q2" 206 case '3': // 1 string to match. 207 return 53; // "q3" 208 case '4': // 1 string to match. 209 return 54; // "q4" 210 case '5': // 1 string to match. 211 return 55; // "q5" 212 case '6': // 1 string to match. 213 return 56; // "q6" 214 case '7': // 1 string to match. 215 return 57; // "q7" 216 case '8': // 1 string to match. 217 return 58; // "q8" 218 case '9': // 1 string to match. 219 return 59; // "q9" 220 } 221 break; 222 case 'r': // 10 strings to match. 223 switch (Name[1]) { 224 default: break; 225 case '0': // 1 string to match. 226 return 66; // "r0" 227 case '1': // 1 string to match. 228 return 67; // "r1" 229 case '2': // 1 string to match. 230 return 68; // "r2" 231 case '3': // 1 string to match. 232 return 69; // "r3" 233 case '4': // 1 string to match. 234 return 70; // "r4" 235 case '5': // 1 string to match. 236 return 71; // "r5" 237 case '6': // 1 string to match. 238 return 72; // "r6" 239 case '7': // 1 string to match. 240 return 73; // "r7" 241 case '8': // 1 string to match. 242 return 74; // "r8" 243 case '9': // 1 string to match. 244 return 75; // "r9" 245 } 246 break; 247 case 's': // 11 strings to match. 248 switch (Name[1]) { 249 default: break; 250 case '0': // 1 string to match. 251 return 79; // "s0" 252 case '1': // 1 string to match. 253 return 80; // "s1" 254 case '2': // 1 string to match. 255 return 81; // "s2" 256 case '3': // 1 string to match. 257 return 82; // "s3" 258 case '4': // 1 string to match. 259 return 83; // "s4" 260 case '5': // 1 string to match. 261 return 84; // "s5" 262 case '6': // 1 string to match. 263 return 85; // "s6" 264 case '7': // 1 string to match. 265 return 86; // "s7" 266 case '8': // 1 string to match. 267 return 87; // "s8" 268 case '9': // 1 string to match. 269 return 88; // "s9" 270 case 'p': // 1 string to match. 271 return 12; // "sp" 272 } 273 break; 274 } 275 break; 276 case 3: // 53 strings to match. 277 switch (Name[0]) { 278 default: break; 279 case 'd': // 22 strings to match. 280 switch (Name[1]) { 281 default: break; 282 case '1': // 10 strings to match. 283 switch (Name[2]) { 284 default: break; 285 case '0': // 1 string to match. 286 return 24; // "d10" 287 case '1': // 1 string to match. 288 return 25; // "d11" 289 case '2': // 1 string to match. 290 return 26; // "d12" 291 case '3': // 1 string to match. 292 return 27; // "d13" 293 case '4': // 1 string to match. 294 return 28; // "d14" 295 case '5': // 1 string to match. 296 return 29; // "d15" 297 case '6': // 1 string to match. 298 return 30; // "d16" 299 case '7': // 1 string to match. 300 return 31; // "d17" 301 case '8': // 1 string to match. 302 return 32; // "d18" 303 case '9': // 1 string to match. 304 return 33; // "d19" 305 } 306 break; 307 case '2': // 10 strings to match. 308 switch (Name[2]) { 309 default: break; 310 case '0': // 1 string to match. 311 return 34; // "d20" 312 case '1': // 1 string to match. 313 return 35; // "d21" 314 case '2': // 1 string to match. 315 return 36; // "d22" 316 case '3': // 1 string to match. 317 return 37; // "d23" 318 case '4': // 1 string to match. 319 return 38; // "d24" 320 case '5': // 1 string to match. 321 return 39; // "d25" 322 case '6': // 1 string to match. 323 return 40; // "d26" 324 case '7': // 1 string to match. 325 return 41; // "d27" 326 case '8': // 1 string to match. 327 return 42; // "d28" 328 case '9': // 1 string to match. 329 return 43; // "d29" 330 } 331 break; 332 case '3': // 2 strings to match. 333 switch (Name[2]) { 334 default: break; 335 case '0': // 1 string to match. 336 return 44; // "d30" 337 case '1': // 1 string to match. 338 return 45; // "d31" 339 } 340 break; 341 } 342 break; 343 case 'q': // 6 strings to match. 344 if (Name[1] != '1') 345 break; 346 switch (Name[2]) { 347 default: break; 348 case '0': // 1 string to match. 349 return 60; // "q10" 350 case '1': // 1 string to match. 351 return 61; // "q11" 352 case '2': // 1 string to match. 353 return 62; // "q12" 354 case '3': // 1 string to match. 355 return 63; // "q13" 356 case '4': // 1 string to match. 357 return 64; // "q14" 358 case '5': // 1 string to match. 359 return 65; // "q15" 360 } 361 break; 362 case 'r': // 3 strings to match. 363 if (Name[1] != '1') 364 break; 365 switch (Name[2]) { 366 default: break; 367 case '0': // 1 string to match. 368 return 76; // "r10" 369 case '1': // 1 string to match. 370 return 77; // "r11" 371 case '2': // 1 string to match. 372 return 78; // "r12" 373 } 374 break; 375 case 's': // 22 strings to match. 376 switch (Name[1]) { 377 default: break; 378 case '1': // 10 strings to match. 379 switch (Name[2]) { 380 default: break; 381 case '0': // 1 string to match. 382 return 89; // "s10" 383 case '1': // 1 string to match. 384 return 90; // "s11" 385 case '2': // 1 string to match. 386 return 91; // "s12" 387 case '3': // 1 string to match. 388 return 92; // "s13" 389 case '4': // 1 string to match. 390 return 93; // "s14" 391 case '5': // 1 string to match. 392 return 94; // "s15" 393 case '6': // 1 string to match. 394 return 95; // "s16" 395 case '7': // 1 string to match. 396 return 96; // "s17" 397 case '8': // 1 string to match. 398 return 97; // "s18" 399 case '9': // 1 string to match. 400 return 98; // "s19" 401 } 402 break; 403 case '2': // 10 strings to match. 404 switch (Name[2]) { 405 default: break; 406 case '0': // 1 string to match. 407 return 99; // "s20" 408 case '1': // 1 string to match. 409 return 100; // "s21" 410 case '2': // 1 string to match. 411 return 101; // "s22" 412 case '3': // 1 string to match. 413 return 102; // "s23" 414 case '4': // 1 string to match. 415 return 103; // "s24" 416 case '5': // 1 string to match. 417 return 104; // "s25" 418 case '6': // 1 string to match. 419 return 105; // "s26" 420 case '7': // 1 string to match. 421 return 106; // "s27" 422 case '8': // 1 string to match. 423 return 107; // "s28" 424 case '9': // 1 string to match. 425 return 108; // "s29" 426 } 427 break; 428 case '3': // 2 strings to match. 429 switch (Name[2]) { 430 default: break; 431 case '0': // 1 string to match. 432 return 109; // "s30" 433 case '1': // 1 string to match. 434 return 110; // "s31" 435 } 436 break; 437 } 438 break; 439 } 440 break; 441 case 4: // 3 strings to match. 442 switch (Name[0]) { 443 default: break; 444 case 'a': // 1 string to match. 445 if (memcmp(Name.data()+1, "psr", 3) != 0) 446 break; 447 return 1; // "apsr" 448 case 'c': // 1 string to match. 449 if (memcmp(Name.data()+1, "psr", 3) != 0) 450 break; 451 return 3; // "cpsr" 452 case 's': // 1 string to match. 453 if (memcmp(Name.data()+1, "psr", 3) != 0) 454 break; 455 return 13; // "spsr" 456 } 457 break; 458 case 5: // 6 strings to match. 459 switch (Name[0]) { 460 default: break; 461 case 'f': // 3 strings to match. 462 if (Name[1] != 'p') 463 break; 464 switch (Name[2]) { 465 default: break; 466 case 'e': // 1 string to match. 467 if (memcmp(Name.data()+3, "xc", 2) != 0) 468 break; 469 return 4; // "fpexc" 470 case 's': // 2 strings to match. 471 switch (Name[3]) { 472 default: break; 473 case 'c': // 1 string to match. 474 if (Name[4] != 'r') 475 break; 476 return 6; // "fpscr" 477 case 'i': // 1 string to match. 478 if (Name[4] != 'd') 479 break; 480 return 8; // "fpsid" 481 } 482 break; 483 } 484 break; 485 case 'm': // 3 strings to match. 486 if (memcmp(Name.data()+1, "vfr", 3) != 0) 487 break; 488 switch (Name[4]) { 489 default: break; 490 case '0': // 1 string to match. 491 return 47; // "mvfr0" 492 case '1': // 1 string to match. 493 return 48; // "mvfr1" 494 case '2': // 1 string to match. 495 return 49; // "mvfr2" 496 } 497 break; 498 } 499 break; 500 case 6: // 1 string to match. 501 if (memcmp(Name.data()+0, "fpinst", 6) != 0) 502 break; 503 return 5; // "fpinst" 504 case 7: // 2 strings to match. 505 switch (Name[0]) { 506 default: break; 507 case 'f': // 1 string to match. 508 if (memcmp(Name.data()+1, "pinst2", 6) != 0) 509 break; 510 return 46; // "fpinst2" 511 case 'i': // 1 string to match. 512 if (memcmp(Name.data()+1, "tstate", 6) != 0) 513 break; 514 return 9; // "itstate" 515 } 516 break; 517 case 9: // 1 string to match. 518 if (memcmp(Name.data()+0, "apsr_nzcv", 9) != 0) 519 break; 520 return 2; // "apsr_nzcv" 521 case 10: // 1 string to match. 522 if (memcmp(Name.data()+0, "fpscr_nzcv", 10) != 0) 523 break; 524 return 7; // "fpscr_nzcv" 525 } 526 return 0; 527} 528 529#endif // GET_REGISTER_MATCHER 530 531 532#ifdef GET_SUBTARGET_FEATURE_NAME 533#undef GET_SUBTARGET_FEATURE_NAME 534 535// User-level names for subtarget features that participate in 536// instruction matching. 537static const char *getSubtargetFeatureName(uint64_t Val) { 538 switch(Val) { 539 case Feature_HasV4T: return "armv4t"; 540 case Feature_HasV5T: return "armv5t"; 541 case Feature_HasV5TE: return "armv5te"; 542 case Feature_HasV6: return "armv6"; 543 case Feature_HasV6M: return "armv6m or armv6t2"; 544 case Feature_HasV8MBaseline: return "armv8m.base"; 545 case Feature_HasV8MMainline: return "armv8m.main"; 546 case Feature_HasV6T2: return "armv6t2"; 547 case Feature_HasV6K: return "armv6k"; 548 case Feature_HasV7: return "armv7"; 549 case Feature_HasV8: return "armv8"; 550 case Feature_PreV8: return "armv7 or earlier"; 551 case Feature_HasV8_1a: return "armv8.1a"; 552 case Feature_HasV8_2a: return "armv8.2a"; 553 case Feature_HasV8_3a: return "armv8.3a"; 554 case Feature_HasV8_4a: return "armv8.4a"; 555 case Feature_HasVFP2: return "VFP2"; 556 case Feature_HasVFP3: return "VFP3"; 557 case Feature_HasVFP4: return "VFP4"; 558 case Feature_HasDPVFP: return "double precision VFP"; 559 case Feature_HasFPARMv8: return "FPARMv8"; 560 case Feature_HasNEON: return "NEON"; 561 case Feature_HasSHA2: return "sha2"; 562 case Feature_HasAES: return "aes"; 563 case Feature_HasCrypto: return "crypto"; 564 case Feature_HasDotProd: return "dotprod"; 565 case Feature_HasCRC: return "crc"; 566 case Feature_HasRAS: return "ras"; 567 case Feature_HasFP16: return "half-float conversions"; 568 case Feature_HasFullFP16: return "full half-float"; 569 case Feature_HasDivideInThumb: return "divide in THUMB"; 570 case Feature_HasDivideInARM: return "divide in ARM"; 571 case Feature_HasDSP: return "dsp"; 572 case Feature_HasDB: return "data-barriers"; 573 case Feature_HasDFB: return "full-data-barrier"; 574 case Feature_HasV7Clrex: return "v7 clrex"; 575 case Feature_HasAcquireRelease: return "acquire/release"; 576 case Feature_HasMP: return "mp-extensions"; 577 case Feature_HasVirtualization: return "virtualization-extensions"; 578 case Feature_HasTrustZone: return "TrustZone"; 579 case Feature_Has8MSecExt: return "ARMv8-M Security Extensions"; 580 case Feature_IsThumb: return "thumb"; 581 case Feature_IsThumb2: return "thumb2"; 582 case Feature_IsMClass: return "armv*m"; 583 case Feature_IsNotMClass: return "!armv*m"; 584 case Feature_IsARM: return "arm-mode"; 585 case Feature_UseNaClTrap: return "NaCl"; 586 case Feature_UseNegativeImmediates: return "NegativeImmediates"; 587 default: return "(unknown)"; 588 } 589} 590 591#endif // GET_SUBTARGET_FEATURE_NAME 592 593 594#ifdef GET_MATCHER_IMPLEMENTATION 595#undef GET_MATCHER_IMPLEMENTATION 596 597static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) { 598 switch (VariantID) { 599 case 0: 600 break; 601 } 602 switch (Mnemonic.size()) { 603 default: break; 604 case 3: // 4 strings to match. 605 switch (Mnemonic[0]) { 606 default: break; 607 case 'r': // 1 string to match. 608 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0) 609 break; 610 Mnemonic = "rfeia"; // "rfe" 611 return; 612 case 's': // 3 strings to match. 613 switch (Mnemonic[1]) { 614 default: break; 615 case 'm': // 1 string to match. 616 if (Mnemonic[2] != 'i') 617 break; 618 Mnemonic = "smc"; // "smi" 619 return; 620 case 'r': // 1 string to match. 621 if (Mnemonic[2] != 's') 622 break; 623 Mnemonic = "srsia"; // "srs" 624 return; 625 case 'w': // 1 string to match. 626 if (Mnemonic[2] != 'i') 627 break; 628 Mnemonic = "svc"; // "swi" 629 return; 630 } 631 break; 632 } 633 break; 634 case 4: // 10 strings to match. 635 switch (Mnemonic[0]) { 636 default: break; 637 case 'f': // 8 strings to match. 638 switch (Mnemonic[1]) { 639 default: break; 640 case 'l': // 2 strings to match. 641 if (Mnemonic[2] != 'd') 642 break; 643 switch (Mnemonic[3]) { 644 default: break; 645 case 'd': // 1 string to match. 646 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldd" 647 Mnemonic = "vldr"; 648 return; 649 case 's': // 1 string to match. 650 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "flds" 651 Mnemonic = "vldr"; 652 return; 653 } 654 break; 655 case 'm': // 4 strings to match. 656 switch (Mnemonic[2]) { 657 default: break; 658 case 'r': // 2 strings to match. 659 switch (Mnemonic[3]) { 660 default: break; 661 case 's': // 1 string to match. 662 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrs" 663 Mnemonic = "vmov"; 664 return; 665 case 'x': // 1 string to match. 666 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrx" 667 Mnemonic = "vmrs"; 668 return; 669 } 670 break; 671 case 's': // 1 string to match. 672 if (Mnemonic[3] != 'r') 673 break; 674 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmsr" 675 Mnemonic = "vmov"; 676 return; 677 case 'x': // 1 string to match. 678 if (Mnemonic[3] != 'r') 679 break; 680 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmxr" 681 Mnemonic = "vmsr"; 682 return; 683 } 684 break; 685 case 's': // 2 strings to match. 686 if (Mnemonic[2] != 't') 687 break; 688 switch (Mnemonic[3]) { 689 default: break; 690 case 'd': // 1 string to match. 691 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstd" 692 Mnemonic = "vstr"; 693 return; 694 case 's': // 1 string to match. 695 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsts" 696 Mnemonic = "vstr"; 697 return; 698 } 699 break; 700 } 701 break; 702 case 'v': // 2 strings to match. 703 switch (Mnemonic[1]) { 704 default: break; 705 case 'l': // 1 string to match. 706 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0) 707 break; 708 Mnemonic = "vldmia"; // "vldm" 709 return; 710 case 's': // 1 string to match. 711 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0) 712 break; 713 Mnemonic = "vstmia"; // "vstm" 714 return; 715 } 716 break; 717 } 718 break; 719 case 5: // 51 strings to match. 720 switch (Mnemonic[0]) { 721 default: break; 722 case 'f': // 18 strings to match. 723 switch (Mnemonic[1]) { 724 default: break; 725 case 'a': // 2 strings to match. 726 if (memcmp(Mnemonic.data()+2, "dd", 2) != 0) 727 break; 728 switch (Mnemonic[4]) { 729 default: break; 730 case 'd': // 1 string to match. 731 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "faddd" 732 Mnemonic = "vadd.f64"; 733 return; 734 case 's': // 1 string to match. 735 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fadds" 736 Mnemonic = "vadd.f32"; 737 return; 738 } 739 break; 740 case 'c': // 4 strings to match. 741 switch (Mnemonic[2]) { 742 default: break; 743 case 'm': // 2 strings to match. 744 if (Mnemonic[3] != 'p') 745 break; 746 switch (Mnemonic[4]) { 747 default: break; 748 case 'd': // 1 string to match. 749 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcmpd" 750 Mnemonic = "vcmp.f64"; 751 return; 752 case 's': // 1 string to match. 753 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcmps" 754 Mnemonic = "vcmp.f32"; 755 return; 756 } 757 break; 758 case 'p': // 2 strings to match. 759 if (Mnemonic[3] != 'y') 760 break; 761 switch (Mnemonic[4]) { 762 default: break; 763 case 'd': // 1 string to match. 764 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcpyd" 765 Mnemonic = "vmov.f64"; 766 return; 767 case 's': // 1 string to match. 768 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fcpys" 769 Mnemonic = "vmov.f32"; 770 return; 771 } 772 break; 773 } 774 break; 775 case 'd': // 2 strings to match. 776 if (memcmp(Mnemonic.data()+2, "iv", 2) != 0) 777 break; 778 switch (Mnemonic[4]) { 779 default: break; 780 case 'd': // 1 string to match. 781 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fdivd" 782 Mnemonic = "vdiv.f64"; 783 return; 784 case 's': // 1 string to match. 785 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fdivs" 786 Mnemonic = "vdiv.f32"; 787 return; 788 } 789 break; 790 case 'm': // 8 strings to match. 791 switch (Mnemonic[2]) { 792 default: break; 793 case 'a': // 2 strings to match. 794 if (Mnemonic[3] != 'c') 795 break; 796 switch (Mnemonic[4]) { 797 default: break; 798 case 'd': // 1 string to match. 799 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmacd" 800 Mnemonic = "vmla.f64"; 801 return; 802 case 's': // 1 string to match. 803 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmacs" 804 Mnemonic = "vmla.f32"; 805 return; 806 } 807 break; 808 case 'd': // 1 string to match. 809 if (memcmp(Mnemonic.data()+3, "rr", 2) != 0) 810 break; 811 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmdrr" 812 Mnemonic = "vmov"; 813 return; 814 case 'r': // 3 strings to match. 815 switch (Mnemonic[3]) { 816 default: break; 817 case 'd': // 2 strings to match. 818 switch (Mnemonic[4]) { 819 default: break; 820 case 'd': // 1 string to match. 821 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrdd" 822 Mnemonic = "vmov"; 823 return; 824 case 's': // 1 string to match. 825 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrds" 826 Mnemonic = "vmov"; 827 return; 828 } 829 break; 830 case 'r': // 1 string to match. 831 if (Mnemonic[4] != 'd') 832 break; 833 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmrrd" 834 Mnemonic = "vmov"; 835 return; 836 } 837 break; 838 case 'u': // 2 strings to match. 839 if (Mnemonic[3] != 'l') 840 break; 841 switch (Mnemonic[4]) { 842 default: break; 843 case 'd': // 1 string to match. 844 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmuld" 845 Mnemonic = "vmul.f64"; 846 return; 847 case 's': // 1 string to match. 848 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fmuls" 849 Mnemonic = "vmul.f32"; 850 return; 851 } 852 break; 853 } 854 break; 855 case 'n': // 2 strings to match. 856 if (memcmp(Mnemonic.data()+2, "eg", 2) != 0) 857 break; 858 switch (Mnemonic[4]) { 859 default: break; 860 case 'd': // 1 string to match. 861 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fnegd" 862 Mnemonic = "vneg.f64"; 863 return; 864 case 's': // 1 string to match. 865 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fnegs" 866 Mnemonic = "vneg.f32"; 867 return; 868 } 869 break; 870 } 871 break; 872 case 'l': // 3 strings to match. 873 if (memcmp(Mnemonic.data()+1, "dm", 2) != 0) 874 break; 875 switch (Mnemonic[3]) { 876 default: break; 877 case 'e': // 1 string to match. 878 if (Mnemonic[4] != 'a') 879 break; 880 Mnemonic = "ldmdb"; // "ldmea" 881 return; 882 case 'f': // 1 string to match. 883 if (Mnemonic[4] != 'd') 884 break; 885 Mnemonic = "ldm"; // "ldmfd" 886 return; 887 case 'i': // 1 string to match. 888 if (Mnemonic[4] != 'a') 889 break; 890 Mnemonic = "ldm"; // "ldmia" 891 return; 892 } 893 break; 894 case 'r': // 4 strings to match. 895 if (memcmp(Mnemonic.data()+1, "fe", 2) != 0) 896 break; 897 switch (Mnemonic[3]) { 898 default: break; 899 case 'e': // 2 strings to match. 900 switch (Mnemonic[4]) { 901 default: break; 902 case 'a': // 1 string to match. 903 Mnemonic = "rfedb"; // "rfeea" 904 return; 905 case 'd': // 1 string to match. 906 Mnemonic = "rfeib"; // "rfeed" 907 return; 908 } 909 break; 910 case 'f': // 2 strings to match. 911 switch (Mnemonic[4]) { 912 default: break; 913 case 'a': // 1 string to match. 914 Mnemonic = "rfeda"; // "rfefa" 915 return; 916 case 'd': // 1 string to match. 917 Mnemonic = "rfeia"; // "rfefd" 918 return; 919 } 920 break; 921 } 922 break; 923 case 's': // 7 strings to match. 924 switch (Mnemonic[1]) { 925 default: break; 926 case 'r': // 4 strings to match. 927 if (Mnemonic[2] != 's') 928 break; 929 switch (Mnemonic[3]) { 930 default: break; 931 case 'e': // 2 strings to match. 932 switch (Mnemonic[4]) { 933 default: break; 934 case 'a': // 1 string to match. 935 Mnemonic = "srsia"; // "srsea" 936 return; 937 case 'd': // 1 string to match. 938 Mnemonic = "srsda"; // "srsed" 939 return; 940 } 941 break; 942 case 'f': // 2 strings to match. 943 switch (Mnemonic[4]) { 944 default: break; 945 case 'a': // 1 string to match. 946 Mnemonic = "srsib"; // "srsfa" 947 return; 948 case 'd': // 1 string to match. 949 Mnemonic = "srsdb"; // "srsfd" 950 return; 951 } 952 break; 953 } 954 break; 955 case 't': // 3 strings to match. 956 if (Mnemonic[2] != 'm') 957 break; 958 switch (Mnemonic[3]) { 959 default: break; 960 case 'e': // 1 string to match. 961 if (Mnemonic[4] != 'a') 962 break; 963 Mnemonic = "stm"; // "stmea" 964 return; 965 case 'f': // 1 string to match. 966 if (Mnemonic[4] != 'd') 967 break; 968 Mnemonic = "stmdb"; // "stmfd" 969 return; 970 case 'i': // 1 string to match. 971 if (Mnemonic[4] != 'a') 972 break; 973 Mnemonic = "stm"; // "stmia" 974 return; 975 } 976 break; 977 } 978 break; 979 case 'v': // 19 strings to match. 980 switch (Mnemonic[1]) { 981 default: break; 982 case 'a': // 3 strings to match. 983 switch (Mnemonic[2]) { 984 default: break; 985 case 'b': // 1 string to match. 986 if (memcmp(Mnemonic.data()+3, "sq", 2) != 0) 987 break; 988 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vabsq" 989 Mnemonic = "vabs"; 990 return; 991 case 'd': // 1 string to match. 992 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0) 993 break; 994 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vaddq" 995 Mnemonic = "vadd"; 996 return; 997 case 'n': // 1 string to match. 998 if (memcmp(Mnemonic.data()+3, "dq", 2) != 0) 999 break; 1000 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vandq" 1001 Mnemonic = "vand"; 1002 return; 1003 } 1004 break; 1005 case 'b': // 1 string to match. 1006 if (memcmp(Mnemonic.data()+2, "icq", 3) != 0) 1007 break; 1008 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vbicq" 1009 Mnemonic = "vbic"; 1010 return; 1011 case 'c': // 3 strings to match. 1012 switch (Mnemonic[2]) { 1013 default: break; 1014 case 'e': // 1 string to match. 1015 if (memcmp(Mnemonic.data()+3, "qq", 2) != 0) 1016 break; 1017 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vceqq" 1018 Mnemonic = "vceq"; 1019 return; 1020 case 'l': // 1 string to match. 1021 if (memcmp(Mnemonic.data()+3, "eq", 2) != 0) 1022 break; 1023 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vcleq" 1024 Mnemonic = "vcle"; 1025 return; 1026 case 'v': // 1 string to match. 1027 if (memcmp(Mnemonic.data()+3, "tq", 2) != 0) 1028 break; 1029 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vcvtq" 1030 Mnemonic = "vcvt"; 1031 return; 1032 } 1033 break; 1034 case 'e': // 1 string to match. 1035 if (memcmp(Mnemonic.data()+2, "orq", 3) != 0) 1036 break; 1037 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "veorq" 1038 Mnemonic = "veor"; 1039 return; 1040 case 'm': // 5 strings to match. 1041 switch (Mnemonic[2]) { 1042 default: break; 1043 case 'a': // 1 string to match. 1044 if (memcmp(Mnemonic.data()+3, "xq", 2) != 0) 1045 break; 1046 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmaxq" 1047 Mnemonic = "vmax"; 1048 return; 1049 case 'i': // 1 string to match. 1050 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0) 1051 break; 1052 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vminq" 1053 Mnemonic = "vmin"; 1054 return; 1055 case 'o': // 1 string to match. 1056 if (memcmp(Mnemonic.data()+3, "vq", 2) != 0) 1057 break; 1058 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmovq" 1059 Mnemonic = "vmov"; 1060 return; 1061 case 'u': // 1 string to match. 1062 if (memcmp(Mnemonic.data()+3, "lq", 2) != 0) 1063 break; 1064 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmulq" 1065 Mnemonic = "vmul"; 1066 return; 1067 case 'v': // 1 string to match. 1068 if (memcmp(Mnemonic.data()+3, "nq", 2) != 0) 1069 break; 1070 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmvnq" 1071 Mnemonic = "vmvn"; 1072 return; 1073 } 1074 break; 1075 case 'o': // 1 string to match. 1076 if (memcmp(Mnemonic.data()+2, "rrq", 3) != 0) 1077 break; 1078 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vorrq" 1079 Mnemonic = "vorr"; 1080 return; 1081 case 's': // 4 strings to match. 1082 switch (Mnemonic[2]) { 1083 default: break; 1084 case 'h': // 2 strings to match. 1085 switch (Mnemonic[3]) { 1086 default: break; 1087 case 'l': // 1 string to match. 1088 if (Mnemonic[4] != 'q') 1089 break; 1090 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vshlq" 1091 Mnemonic = "vshl"; 1092 return; 1093 case 'r': // 1 string to match. 1094 if (Mnemonic[4] != 'q') 1095 break; 1096 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vshrq" 1097 Mnemonic = "vshr"; 1098 return; 1099 } 1100 break; 1101 case 'u': // 1 string to match. 1102 if (memcmp(Mnemonic.data()+3, "bq", 2) != 0) 1103 break; 1104 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vsubq" 1105 Mnemonic = "vsub"; 1106 return; 1107 case 'w': // 1 string to match. 1108 if (memcmp(Mnemonic.data()+3, "pq", 2) != 0) 1109 break; 1110 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vswpq" 1111 Mnemonic = "vswp"; 1112 return; 1113 } 1114 break; 1115 case 'z': // 1 string to match. 1116 if (memcmp(Mnemonic.data()+2, "ipq", 3) != 0) 1117 break; 1118 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vzipq" 1119 Mnemonic = "vzip"; 1120 return; 1121 } 1122 break; 1123 } 1124 break; 1125 case 6: // 10 strings to match. 1126 if (Mnemonic[0] != 'f') 1127 break; 1128 switch (Mnemonic[1]) { 1129 default: break; 1130 case 's': // 4 strings to match. 1131 switch (Mnemonic[2]) { 1132 default: break; 1133 case 'i': // 2 strings to match. 1134 if (memcmp(Mnemonic.data()+3, "to", 2) != 0) 1135 break; 1136 switch (Mnemonic[5]) { 1137 default: break; 1138 case 'd': // 1 string to match. 1139 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsitod" 1140 Mnemonic = "vcvt.f64.s32"; 1141 return; 1142 case 's': // 1 string to match. 1143 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsitos" 1144 Mnemonic = "vcvt.f32.s32"; 1145 return; 1146 } 1147 break; 1148 case 'q': // 2 strings to match. 1149 if (memcmp(Mnemonic.data()+3, "rt", 2) != 0) 1150 break; 1151 switch (Mnemonic[5]) { 1152 default: break; 1153 case 'd': // 1 string to match. 1154 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsqrtd" 1155 Mnemonic = "vsqrt"; 1156 return; 1157 case 's': // 1 string to match. 1158 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fsqrts" 1159 Mnemonic = "vsqrt"; 1160 return; 1161 } 1162 break; 1163 } 1164 break; 1165 case 't': // 4 strings to match. 1166 if (Mnemonic[2] != 'o') 1167 break; 1168 switch (Mnemonic[3]) { 1169 default: break; 1170 case 's': // 2 strings to match. 1171 if (Mnemonic[4] != 'i') 1172 break; 1173 switch (Mnemonic[5]) { 1174 default: break; 1175 case 'd': // 1 string to match. 1176 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosid" 1177 Mnemonic = "vcvtr.s32.f64"; 1178 return; 1179 case 's': // 1 string to match. 1180 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosis" 1181 Mnemonic = "vcvtr.s32.f32"; 1182 return; 1183 } 1184 break; 1185 case 'u': // 2 strings to match. 1186 if (Mnemonic[4] != 'i') 1187 break; 1188 switch (Mnemonic[5]) { 1189 default: break; 1190 case 'd': // 1 string to match. 1191 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouid" 1192 Mnemonic = "vcvtr.u32.f64"; 1193 return; 1194 case 's': // 1 string to match. 1195 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouis" 1196 Mnemonic = "vcvtr.u32.f32"; 1197 return; 1198 } 1199 break; 1200 } 1201 break; 1202 case 'u': // 2 strings to match. 1203 if (memcmp(Mnemonic.data()+2, "ito", 3) != 0) 1204 break; 1205 switch (Mnemonic[5]) { 1206 default: break; 1207 case 'd': // 1 string to match. 1208 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fuitod" 1209 Mnemonic = "vcvt.f64.u32"; 1210 return; 1211 case 's': // 1 string to match. 1212 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fuitos" 1213 Mnemonic = "vcvt.f32.u32"; 1214 return; 1215 } 1216 break; 1217 } 1218 break; 1219 case 7: // 8 strings to match. 1220 if (Mnemonic[0] != 'f') 1221 break; 1222 switch (Mnemonic[1]) { 1223 default: break; 1224 case 'l': // 2 strings to match. 1225 if (memcmp(Mnemonic.data()+2, "dm", 2) != 0) 1226 break; 1227 switch (Mnemonic[4]) { 1228 default: break; 1229 case 'e': // 1 string to match. 1230 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0) 1231 break; 1232 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmeax" 1233 Mnemonic = "fldmdbx"; 1234 return; 1235 case 'f': // 1 string to match. 1236 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0) 1237 break; 1238 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fldmfdx" 1239 Mnemonic = "fldmiax"; 1240 return; 1241 } 1242 break; 1243 case 's': // 2 strings to match. 1244 if (memcmp(Mnemonic.data()+2, "tm", 2) != 0) 1245 break; 1246 switch (Mnemonic[4]) { 1247 default: break; 1248 case 'e': // 1 string to match. 1249 if (memcmp(Mnemonic.data()+5, "ax", 2) != 0) 1250 break; 1251 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmeax" 1252 Mnemonic = "fstmiax"; 1253 return; 1254 case 'f': // 1 string to match. 1255 if (memcmp(Mnemonic.data()+5, "dx", 2) != 0) 1256 break; 1257 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "fstmfdx" 1258 Mnemonic = "fstmdbx"; 1259 return; 1260 } 1261 break; 1262 case 't': // 4 strings to match. 1263 if (Mnemonic[2] != 'o') 1264 break; 1265 switch (Mnemonic[3]) { 1266 default: break; 1267 case 's': // 2 strings to match. 1268 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0) 1269 break; 1270 switch (Mnemonic[6]) { 1271 default: break; 1272 case 'd': // 1 string to match. 1273 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosizd" 1274 Mnemonic = "vcvt.s32.f64"; 1275 return; 1276 case 's': // 1 string to match. 1277 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftosizs" 1278 Mnemonic = "vcvt.s32.f32"; 1279 return; 1280 } 1281 break; 1282 case 'u': // 2 strings to match. 1283 if (memcmp(Mnemonic.data()+4, "iz", 2) != 0) 1284 break; 1285 switch (Mnemonic[6]) { 1286 default: break; 1287 case 'd': // 1 string to match. 1288 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouizd" 1289 Mnemonic = "vcvt.u32.f64"; 1290 return; 1291 case 's': // 1 string to match. 1292 if ((Features & Feature_HasVFP2) == Feature_HasVFP2) // "ftouizs" 1293 Mnemonic = "vcvt.u32.f32"; 1294 return; 1295 } 1296 break; 1297 } 1298 break; 1299 } 1300 break; 1301 case 8: // 5 strings to match. 1302 switch (Mnemonic[0]) { 1303 default: break; 1304 case 'q': // 1 string to match. 1305 if (memcmp(Mnemonic.data()+1, "subaddx", 7) != 0) 1306 break; 1307 Mnemonic = "qsax"; // "qsubaddx" 1308 return; 1309 case 's': // 2 strings to match. 1310 switch (Mnemonic[1]) { 1311 default: break; 1312 case 'a': // 1 string to match. 1313 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0) 1314 break; 1315 Mnemonic = "sasx"; // "saddsubx" 1316 return; 1317 case 's': // 1 string to match. 1318 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0) 1319 break; 1320 Mnemonic = "ssax"; // "ssubaddx" 1321 return; 1322 } 1323 break; 1324 case 'u': // 2 strings to match. 1325 switch (Mnemonic[1]) { 1326 default: break; 1327 case 'a': // 1 string to match. 1328 if (memcmp(Mnemonic.data()+2, "ddsubx", 6) != 0) 1329 break; 1330 Mnemonic = "uasx"; // "uaddsubx" 1331 return; 1332 case 's': // 1 string to match. 1333 if (memcmp(Mnemonic.data()+2, "ubaddx", 6) != 0) 1334 break; 1335 Mnemonic = "usax"; // "usubaddx" 1336 return; 1337 } 1338 break; 1339 } 1340 break; 1341 case 9: // 8 strings to match. 1342 switch (Mnemonic[0]) { 1343 default: break; 1344 case 's': // 2 strings to match. 1345 if (Mnemonic[1] != 'h') 1346 break; 1347 switch (Mnemonic[2]) { 1348 default: break; 1349 case 'a': // 1 string to match. 1350 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0) 1351 break; 1352 Mnemonic = "shasx"; // "shaddsubx" 1353 return; 1354 case 's': // 1 string to match. 1355 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0) 1356 break; 1357 Mnemonic = "shsax"; // "shsubaddx" 1358 return; 1359 } 1360 break; 1361 case 'u': // 4 strings to match. 1362 switch (Mnemonic[1]) { 1363 default: break; 1364 case 'h': // 2 strings to match. 1365 switch (Mnemonic[2]) { 1366 default: break; 1367 case 'a': // 1 string to match. 1368 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0) 1369 break; 1370 Mnemonic = "uhasx"; // "uhaddsubx" 1371 return; 1372 case 's': // 1 string to match. 1373 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0) 1374 break; 1375 Mnemonic = "uhsax"; // "uhsubaddx" 1376 return; 1377 } 1378 break; 1379 case 'q': // 2 strings to match. 1380 switch (Mnemonic[2]) { 1381 default: break; 1382 case 'a': // 1 string to match. 1383 if (memcmp(Mnemonic.data()+3, "ddsubx", 6) != 0) 1384 break; 1385 Mnemonic = "uqasx"; // "uqaddsubx" 1386 return; 1387 case 's': // 1 string to match. 1388 if (memcmp(Mnemonic.data()+3, "ubaddx", 6) != 0) 1389 break; 1390 Mnemonic = "uqsax"; // "uqsubaddx" 1391 return; 1392 } 1393 break; 1394 } 1395 break; 1396 case 'v': // 2 strings to match. 1397 if (memcmp(Mnemonic.data()+1, "movq.f", 6) != 0) 1398 break; 1399 switch (Mnemonic[7]) { 1400 default: break; 1401 case '3': // 1 string to match. 1402 if (Mnemonic[8] != '2') 1403 break; 1404 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmovq.f32" 1405 Mnemonic = "vmov.f32"; 1406 return; 1407 case '6': // 1 string to match. 1408 if (Mnemonic[8] != '4') 1409 break; 1410 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vmovq.f64" 1411 Mnemonic = "vmov.f64"; 1412 return; 1413 } 1414 break; 1415 } 1416 break; 1417 case 11: // 2 strings to match. 1418 if (memcmp(Mnemonic.data()+0, "vrecpeq.", 8) != 0) 1419 break; 1420 switch (Mnemonic[8]) { 1421 default: break; 1422 case 'f': // 1 string to match. 1423 if (memcmp(Mnemonic.data()+9, "32", 2) != 0) 1424 break; 1425 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vrecpeq.f32" 1426 Mnemonic = "vrecpe.f32"; 1427 return; 1428 case 'u': // 1 string to match. 1429 if (memcmp(Mnemonic.data()+9, "32", 2) != 0) 1430 break; 1431 if ((Features & Feature_HasNEON) == Feature_HasNEON) // "vrecpeq.u32" 1432 Mnemonic = "vrecpe.u32"; 1433 return; 1434 } 1435 break; 1436 } 1437} 1438 1439enum { 1440 Tie0_1_1, 1441 Tie0_2_2, 1442 Tie0_3_3, 1443 Tie0_4_4, 1444 Tie0_4_5, 1445 Tie1_1_1, 1446 Tie1_3_3, 1447 Tie1_4_4, 1448 Tie2_4_4, 1449}; 1450 1451static const uint8_t TiedAsmOperandTable[][3] = { 1452 /* Tie0_1_1 */ { 0, 1, 1 }, 1453 /* Tie0_2_2 */ { 0, 2, 2 }, 1454 /* Tie0_3_3 */ { 0, 3, 3 }, 1455 /* Tie0_4_4 */ { 0, 4, 4 }, 1456 /* Tie0_4_5 */ { 0, 4, 5 }, 1457 /* Tie1_1_1 */ { 1, 1, 1 }, 1458 /* Tie1_3_3 */ { 1, 3, 3 }, 1459 /* Tie1_4_4 */ { 1, 4, 4 }, 1460 /* Tie2_4_4 */ { 2, 4, 4 }, 1461}; 1462 1463namespace { 1464enum OperatorConversionKind { 1465 CVT_Done, 1466 CVT_Reg, 1467 CVT_Tied, 1468 CVT_95_Reg, 1469 CVT_95_addCCOutOperands, 1470 CVT_95_addCondCodeOperands, 1471 CVT_95_addRegShiftedRegOperands, 1472 CVT_95_addModImmOperands, 1473 CVT_95_addModImmNotOperands, 1474 CVT_95_addRegShiftedImmOperands, 1475 CVT_95_addImmOperands, 1476 CVT_95_addT2SOImmNotOperands, 1477 CVT_95_addImm0_95_508s4Operands, 1478 CVT_regSP, 1479 CVT_95_addImm0_95_508s4NegOperands, 1480 CVT_95_addImm0_95_4095NegOperands, 1481 CVT_95_addThumbModImmNeg8_95_255Operands, 1482 CVT_95_addT2SOImmNegOperands, 1483 CVT_95_addModImmNegOperands, 1484 CVT_95_addImm0_95_1020s4Operands, 1485 CVT_95_addThumbModImmNeg1_95_7Operands, 1486 CVT_95_addUnsignedOffset_95_b8s2Operands, 1487 CVT_95_addAdrLabelOperands, 1488 CVT_95_addARMBranchTargetOperands, 1489 CVT_cvtThumbBranches, 1490 CVT_95_addBitfieldOperands, 1491 CVT_imm_95_0, 1492 CVT_95_addThumbBranchTargetOperands, 1493 CVT_95_addCoprocNumOperands, 1494 CVT_95_addCoprocRegOperands, 1495 CVT_95_addProcIFlagsOperands, 1496 CVT_imm_95_20, 1497 CVT_imm_95_12, 1498 CVT_imm_95_15, 1499 CVT_95_addMemBarrierOptOperands, 1500 CVT_imm_95_16, 1501 CVT_95_addFPImmOperands, 1502 CVT_95_addDPRRegListOperands, 1503 CVT_imm_95_1, 1504 CVT_95_addInstSyncBarrierOptOperands, 1505 CVT_95_addITCondCodeOperands, 1506 CVT_95_addITMaskOperands, 1507 CVT_95_addMemNoOffsetOperands, 1508 CVT_95_addAddrMode5Operands, 1509 CVT_95_addCoprocOptionOperands, 1510 CVT_95_addPostIdxImm8s4Operands, 1511 CVT_95_addRegListOperands, 1512 CVT_95_addThumbMemPCOperands, 1513 CVT_95_addConstPoolAsmImmOperands, 1514 CVT_95_addMemThumbRIs4Operands, 1515 CVT_95_addMemThumbRROperands, 1516 CVT_95_addMemThumbSPIOperands, 1517 CVT_95_addMemImm12OffsetOperands, 1518 CVT_95_addMemNegImm8OffsetOperands, 1519 CVT_95_addMemRegOffsetOperands, 1520 CVT_95_addMemUImm12OffsetOperands, 1521 CVT_95_addT2MemRegOffsetOperands, 1522 CVT_95_addMemPCRelImm12Operands, 1523 CVT_95_addMemImm8OffsetOperands, 1524 CVT_95_addAM2OffsetImmOperands, 1525 CVT_95_addPostIdxRegShiftedOperands, 1526 CVT_95_addMemThumbRIs1Operands, 1527 CVT_95_addMemPosImm8OffsetOperands, 1528 CVT_95_addMemImm8s4OffsetOperands, 1529 CVT_95_addAddrMode3Operands, 1530 CVT_95_addAM3OffsetOperands, 1531 CVT_95_addMemImm0_95_1020s4OffsetOperands, 1532 CVT_95_addMemThumbRIs2Operands, 1533 CVT_95_addPostIdxRegOperands, 1534 CVT_95_addPostIdxImm8Operands, 1535 CVT_reg0, 1536 CVT_regCPSR, 1537 CVT_imm_95_14, 1538 CVT_95_addBankedRegOperands, 1539 CVT_95_addMSRMaskOperands, 1540 CVT_cvtThumbMultiply, 1541 CVT_regR8, 1542 CVT_regR0, 1543 CVT_95_addPKHASRImmOperands, 1544 CVT_95_addImm1_95_32Operands, 1545 CVT_imm_95_4, 1546 CVT_imm_95_5, 1547 CVT_95_addShifterImmOperands, 1548 CVT_95_addImm1_95_16Operands, 1549 CVT_95_addRotImmOperands, 1550 CVT_95_addMemTBBOperands, 1551 CVT_95_addMemTBHOperands, 1552 CVT_95_addTraceSyncBarrierOptOperands, 1553 CVT_95_addNEONi16splatNotOperands, 1554 CVT_95_addNEONi32splatNotOperands, 1555 CVT_95_addNEONi16splatOperands, 1556 CVT_95_addNEONi32splatOperands, 1557 CVT_95_addComplexRotationOddOperands, 1558 CVT_95_addComplexRotationEvenOperands, 1559 CVT_95_addVectorIndex64Operands, 1560 CVT_95_addVectorIndex32Operands, 1561 CVT_95_addFBits16Operands, 1562 CVT_95_addFBits32Operands, 1563 CVT_95_addVectorIndex16Operands, 1564 CVT_95_addVectorIndex8Operands, 1565 CVT_95_addVecListOperands, 1566 CVT_95_addDupAlignedMemory16Operands, 1567 CVT_95_addAlignedMemory64or128Operands, 1568 CVT_95_addAlignedMemory64or128or256Operands, 1569 CVT_95_addAlignedMemory64Operands, 1570 CVT_95_addVecListIndexedOperands, 1571 CVT_95_addAlignedMemory16Operands, 1572 CVT_95_addDupAlignedMemory32Operands, 1573 CVT_95_addAlignedMemory32Operands, 1574 CVT_95_addDupAlignedMemoryNoneOperands, 1575 CVT_95_addAlignedMemoryNoneOperands, 1576 CVT_95_addAlignedMemoryOperands, 1577 CVT_95_addDupAlignedMemory64Operands, 1578 CVT_95_addDupAlignedMemory64or128Operands, 1579 CVT_95_addSPRRegListOperands, 1580 CVT_95_addAddrMode5FP16Operands, 1581 CVT_95_addNEONi32vmovOperands, 1582 CVT_95_addNEONvmovi8ReplicateOperands, 1583 CVT_95_addNEONvmovi16ReplicateOperands, 1584 CVT_95_addNEONi32vmovNegOperands, 1585 CVT_95_addNEONvmovi32ReplicateOperands, 1586 CVT_95_addNEONi64splatOperands, 1587 CVT_95_addNEONi8splatOperands, 1588 CVT_95_addNEONinvi8ReplicateOperands, 1589 CVT_imm_95_2, 1590 CVT_imm_95_3, 1591 CVT_NUM_CONVERTERS 1592}; 1593 1594enum InstructionConversionKind { 1595 Convert_NoOperands, 1596 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, 1597 Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, 1598 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, 1599 Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, 1600 Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, 1601 Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, 1602 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, 1603 Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, 1604 Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, 1605 Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, 1606 Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, 1607 Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, 1608 Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, 1609 Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, 1610 Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, 1611 Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, 1612 Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, 1613 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, 1614 Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, 1615 Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, 1616 Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, 1617 Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, 1618 Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, 1619 Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, 1620 Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, 1621 Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, 1622 Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, 1623 Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, 1624 Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, 1625 Convert__Reg1_1__Imm0_40951_3__CondCode2_0, 1626 Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, 1627 Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, 1628 Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, 1629 Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, 1630 Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, 1631 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, 1632 Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, 1633 Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, 1634 Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, 1635 Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, 1636 Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, 1637 Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, 1638 Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, 1639 Convert__Reg1_1__Imm1_2__CondCode2_0, 1640 Convert__Reg1_1__AdrLabel1_2__CondCode2_0, 1641 Convert__Reg1_2__Imm1_3__CondCode2_0, 1642 Convert__Reg1_1__Tie0_1_1__Reg1_2, 1643 Convert__Reg1_1__Reg1_2, 1644 Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, 1645 Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, 1646 Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, 1647 Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, 1648 Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, 1649 Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, 1650 Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, 1651 Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, 1652 Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, 1653 Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, 1654 Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, 1655 Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, 1656 Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, 1657 Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, 1658 Convert__ARMBranchTarget1_1__CondCode2_0, 1659 ConvertCustom_cvtThumbBranches, 1660 Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, 1661 Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, 1662 Convert__imm_95_0, 1663 Convert__Imm0_2551_0, 1664 Convert__Imm0_655351_0, 1665 Convert__ARMBranchTarget1_0, 1666 Convert__CondCode2_0__ThumbBranchTarget1_1, 1667 Convert__Reg1_0, 1668 Convert__ThumbBranchTarget1_0, 1669 Convert__Reg1_1__CondCode2_0, 1670 Convert__CondCode2_0__Reg1_1, 1671 Convert__CondCode2_0__ARMBranchTarget1_1, 1672 Convert__CondCode2_0, 1673 Convert__Reg1_0__ThumbBranchTarget1_1, 1674 Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, 1675 Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, 1676 Convert__Reg1_1__Reg1_2__CondCode2_0, 1677 Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, 1678 Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, 1679 Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, 1680 Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, 1681 Convert__Reg1_1__T2SOImm1_2__CondCode2_0, 1682 Convert__Reg1_1__ModImm1_2__CondCode2_0, 1683 Convert__Reg1_2__Reg1_3__CondCode2_0, 1684 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, 1685 Convert__Reg1_2__T2SOImm1_3__CondCode2_0, 1686 Convert__Reg1_1__Imm0_2551_2__CondCode2_0, 1687 Convert__Imm0_311_0, 1688 Convert__Imm0_311_1, 1689 Convert__Imm1_0__ProcIFlags1_1, 1690 Convert__Imm1_0__ProcIFlags1_2, 1691 Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, 1692 Convert__Imm1_0__ProcIFlags1_1__Imm1_2, 1693 Convert__Imm1_0__ProcIFlags1_2__Imm1_3, 1694 Convert__Reg1_0__Reg1_1__Reg1_2, 1695 Convert__imm_95_20__CondCode2_0, 1696 Convert__Imm0_151_1__CondCode2_0, 1697 Convert__imm_95_12, 1698 Convert__imm_95_12__CondCode2_0, 1699 Convert__imm_95_15, 1700 Convert__imm_95_15__CondCode2_0, 1701 Convert__MemBarrierOpt1_0, 1702 Convert__MemBarrierOpt1_1__CondCode2_0, 1703 Convert__imm_95_0__CondCode2_0, 1704 Convert__imm_95_16__CondCode2_0, 1705 Convert__Reg1_1__FPImm1_2__CondCode2_0, 1706 Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, 1707 Convert__Reg1_1__CondCode2_0__DPRRegList1_2, 1708 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, 1709 Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, 1710 Convert__Imm0_2391_1__CondCode2_0, 1711 Convert__Imm0_2391_2__CondCode2_0, 1712 Convert__Imm0_631_0, 1713 Convert__Imm0_655351_1, 1714 Convert__InstSyncBarrierOpt1_0, 1715 Convert__InstSyncBarrierOpt1_1__CondCode2_0, 1716 Convert__ITCondCode1_1__ITMask1_0, 1717 Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, 1718 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, 1719 Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, 1720 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, 1721 Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, 1722 Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, 1723 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, 1724 Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, 1725 Convert__Reg1_1__CondCode2_0__RegList1_2, 1726 Convert__Reg1_2__CondCode2_0__RegList1_3, 1727 Convert__Reg1_1__CondCode2_0__RegList1_3, 1728 Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, 1729 Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, 1730 Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, 1731 Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, 1732 Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, 1733 Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, 1734 Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, 1735 Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, 1736 Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, 1737 Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, 1738 Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, 1739 Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, 1740 Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, 1741 Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, 1742 Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, 1743 Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, 1744 Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, 1745 Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, 1746 Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, 1747 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, 1748 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, 1749 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, 1750 Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, 1751 Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, 1752 Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, 1753 Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, 1754 Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, 1755 Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, 1756 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0, 1757 Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, 1758 Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, 1759 Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, 1760 Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, 1761 Convert__Reg1_1__AddrMode33_2__CondCode2_0, 1762 Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, 1763 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, 1764 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, 1765 Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, 1766 Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, 1767 Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, 1768 Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, 1769 Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, 1770 Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, 1771 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, 1772 Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, 1773 Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, 1774 Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, 1775 Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, 1776 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, 1777 Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, 1778 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, 1779 Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, 1780 Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, 1781 Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, 1782 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, 1783 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, 1784 Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, 1785 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, 1786 Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, 1787 Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, 1788 Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1, 1789 Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, 1790 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, 1791 Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, 1792 Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, 1793 Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, 1794 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, 1795 Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, 1796 Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, 1797 Convert__Reg1_0__Reg1_1, 1798 Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0, 1799 Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, 1800 Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, 1801 Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, 1802 Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, 1803 Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, 1804 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, 1805 Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, 1806 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, 1807 Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, 1808 Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, 1809 Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, 1810 Convert__Reg1_1__BankedReg1_2__CondCode2_0, 1811 Convert__Reg1_1__MSRMask1_2__CondCode2_0, 1812 Convert__BankedReg1_1__Reg1_2__CondCode2_0, 1813 Convert__MSRMask1_1__Reg1_2__CondCode2_0, 1814 Convert__MSRMask1_1__ModImm1_2__CondCode2_0, 1815 Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, 1816 ConvertCustom_cvtThumbMultiply, 1817 Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, 1818 Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, 1819 Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, 1820 Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, 1821 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, 1822 Convert__regR8__regR8__imm_95_14__imm_95_0, 1823 Convert__regR0__regR0__CondCode2_0__reg0, 1824 Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, 1825 Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, 1826 Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, 1827 Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, 1828 Convert__MemImm12Offset2_0, 1829 Convert__MemRegOffset3_0, 1830 Convert__Imm1_1__CondCode2_0, 1831 Convert__MemNegImm8Offset2_1__CondCode2_0, 1832 Convert__MemUImm12Offset2_1__CondCode2_0, 1833 Convert__T2MemRegOffset3_1__CondCode2_0, 1834 Convert__MemPCRelImm121_1__CondCode2_0, 1835 Convert__CondCode2_0__RegList1_1, 1836 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, 1837 Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, 1838 Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, 1839 Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0, 1840 Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, 1841 Convert__SetEndImm1_0, 1842 Convert__Imm0_11_0, 1843 Convert__imm_95_4__CondCode2_0, 1844 Convert__imm_95_5__CondCode2_0, 1845 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, 1846 Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, 1847 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, 1848 Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, 1849 Convert__Imm0_311_2, 1850 Convert__Imm0_311_1__CondCode2_0, 1851 Convert__Imm0_311_2__CondCode2_0, 1852 Convert__Imm0_311_3__CondCode2_0, 1853 Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, 1854 Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, 1855 Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, 1856 Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, 1857 Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, 1858 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, 1859 Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, 1860 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, 1861 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, 1862 Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, 1863 Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, 1864 Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, 1865 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0, 1866 Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, 1867 Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, 1868 Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, 1869 Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, 1870 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, 1871 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, 1872 Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, 1873 Convert__Imm0_2551_3__CondCode2_0, 1874 Convert__Imm0_2551_1__CondCode2_0, 1875 Convert__Imm24bit1_1__CondCode2_0, 1876 Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, 1877 Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, 1878 Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, 1879 Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, 1880 Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, 1881 Convert__MemTBB2_1__CondCode2_0, 1882 Convert__MemTBH2_1__CondCode2_0, 1883 Convert__TraceSyncBarrierOpt1_0, 1884 Convert__TraceSyncBarrierOpt1_1__CondCode2_0, 1885 Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, 1886 Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, 1887 Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, 1888 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, 1889 Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, 1890 Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, 1891 Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, 1892 Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, 1893 Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, 1894 Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, 1895 Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, 1896 Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, 1897 Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, 1898 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, 1899 Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, 1900 Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, 1901 Convert__Reg1_2__Reg1_2__CondCode2_0, 1902 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, 1903 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, 1904 Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, 1905 Convert__Reg1_2__CondCode2_0, 1906 Convert__Reg1_3__Reg1_4__CondCode2_0, 1907 Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, 1908 Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, 1909 Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, 1910 Convert__Reg1_2__Reg1_3, 1911 Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, 1912 Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, 1913 Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, 1914 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, 1915 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, 1916 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, 1917 Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, 1918 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, 1919 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, 1920 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, 1921 Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, 1922 Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, 1923 Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, 1924 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, 1925 Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, 1926 Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, 1927 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, 1928 Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, 1929 Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 1930 Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 1931 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, 1932 Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 1933 Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 1934 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 1935 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, 1936 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, 1937 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, 1938 Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 1939 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, 1940 Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, 1941 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, 1942 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, 1943 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, 1944 Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, 1945 Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, 1946 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, 1947 Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, 1948 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, 1949 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 1950 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, 1951 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 1952 Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 1953 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, 1954 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 1955 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, 1956 Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 1957 Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 1958 Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, 1959 Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, 1960 Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, 1961 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 1962 Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, 1963 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, 1964 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, 1965 Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 1966 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 1967 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 1968 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 1969 Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, 1970 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, 1971 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, 1972 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 1973 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, 1974 Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 1975 Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 1976 Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 1977 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, 1978 Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 1979 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, 1980 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 1981 Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 1982 Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 1983 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, 1984 Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, 1985 Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, 1986 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 1987 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 1988 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, 1989 Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, 1990 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 1991 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 1992 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 1993 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, 1994 Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 1995 Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 1996 Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 1997 Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, 1998 Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 1999 Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2000 Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2001 Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2002 Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, 2003 Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, 2004 Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, 2005 Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, 2006 Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, 2007 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2008 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2009 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, 2010 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, 2011 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, 2012 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, 2013 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, 2014 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, 2015 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, 2016 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2017 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, 2018 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, 2019 Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2020 Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, 2021 Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2022 Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, 2023 Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, 2024 Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, 2025 Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2026 Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2027 Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2028 Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, 2029 Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2030 Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, 2031 Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, 2032 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, 2033 Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, 2034 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, 2035 Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, 2036 Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, 2037 Convert__Reg1_1__CondCode2_0__SPRRegList1_2, 2038 Convert__Reg1_1__AddrMode52_2__CondCode2_0, 2039 Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, 2040 Convert__Reg1_2__AddrMode52_3__CondCode2_0, 2041 Convert__Reg1_1__Reg1_2__Reg1_3, 2042 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, 2043 Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, 2044 Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, 2045 Convert__Reg1_2__FPImm1_3__CondCode2_0, 2046 Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, 2047 Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, 2048 Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, 2049 Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, 2050 Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, 2051 Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, 2052 Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, 2053 Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, 2054 Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, 2055 Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, 2056 Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, 2057 Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, 2058 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, 2059 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, 2060 Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, 2061 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, 2062 Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, 2063 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, 2064 Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, 2065 Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, 2066 Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, 2067 Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, 2068 Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, 2069 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, 2070 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, 2071 Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, 2072 Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, 2073 Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, 2074 Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, 2075 Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, 2076 Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, 2077 Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, 2078 Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, 2079 Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, 2080 Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, 2081 Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, 2082 Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, 2083 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, 2084 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, 2085 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, 2086 Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, 2087 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, 2088 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, 2089 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, 2090 Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, 2091 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, 2092 Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, 2093 Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, 2094 Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, 2095 Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, 2096 Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, 2097 Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, 2098 Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, 2099 Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, 2100 Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, 2101 Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, 2102 Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, 2103 Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, 2104 Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, 2105 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, 2106 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, 2107 Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, 2108 Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, 2109 Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, 2110 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, 2111 Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, 2112 Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, 2113 Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, 2114 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, 2115 Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, 2116 Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, 2117 Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, 2118 Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, 2119 Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, 2120 Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, 2121 Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, 2122 Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, 2123 Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, 2124 Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, 2125 Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, 2126 Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, 2127 Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, 2128 Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, 2129 Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, 2130 Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, 2131 Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, 2132 Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, 2133 Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, 2134 Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, 2135 Convert__imm_95_2__CondCode2_0, 2136 Convert__imm_95_3__CondCode2_0, 2137 Convert__imm_95_1__CondCode2_0, 2138 CVT_NUM_SIGNATURES 2139}; 2140 2141} // end anonymous namespace 2142 2143static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][17] = { 2144 // Convert_NoOperands 2145 { CVT_Done }, 2146 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1 2147 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2148 // Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0 2149 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2150 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0 2151 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2152 // Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0 2153 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2154 // Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0 2155 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2156 // Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0 2157 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2158 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0 2159 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2160 // Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0 2161 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2162 // Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0 2163 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2164 // Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0 2165 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2166 // Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0 2167 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRegShiftedRegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2168 // Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0 2169 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2170 // Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0 2171 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2172 // Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0 2173 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2174 // Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0 2175 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addRegShiftedImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2176 // Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0 2177 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2178 // Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0 2179 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2180 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0 2181 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2182 // Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0 2183 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2184 // Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0 2185 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImm0_95_4095NegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2186 // Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1 2187 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2188 // Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1 2189 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2190 // Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1 2191 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_Tied, Tie0_3_3, CVT_95_addThumbModImmNeg8_95_255Operands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2192 // Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0 2193 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2194 // Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0 2195 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2196 // Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0 2197 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addModImmNegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2198 // Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0 2199 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2200 // Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0 2201 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addImm0_95_508s4NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2202 // Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0 2203 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_1020s4Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2204 // Convert__Reg1_1__Imm0_40951_3__CondCode2_0 2205 { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2206 // Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0 2207 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2208 // Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0 2209 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImm0_95_4095NegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2210 // Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0 2211 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2212 // Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0 2213 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2214 // Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1 2215 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2216 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1 2217 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2218 // Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1 2219 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addThumbModImmNeg1_95_7Operands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2220 // Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0 2221 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addT2SOImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2222 // Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0 2223 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addModImmNegOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2224 // Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0 2225 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2226 // Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0 2227 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNegOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2228 // Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0 2229 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addT2SOImmNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2230 // Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0 2231 { CVT_95_Reg, 2, CVT_95_addUnsignedOffset_95_b8s2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2232 // Convert__Reg1_1__Imm1_2__CondCode2_0 2233 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2234 // Convert__Reg1_1__AdrLabel1_2__CondCode2_0 2235 { CVT_95_Reg, 2, CVT_95_addAdrLabelOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2236 // Convert__Reg1_2__Imm1_3__CondCode2_0 2237 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2238 // Convert__Reg1_1__Tie0_1_1__Reg1_2 2239 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done }, 2240 // Convert__Reg1_1__Reg1_2 2241 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 2242 // Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0 2243 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2244 // Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0 2245 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2246 // Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0 2247 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2248 // Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0 2249 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2250 // Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0 2251 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addT2SOImmNotOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2252 // Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0 2253 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addT2SOImmNotOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2254 // Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1 2255 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2256 // Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0 2257 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2258 // Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0 2259 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2260 // Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0 2261 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2262 // Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1 2263 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2264 // Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0 2265 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2266 // Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0 2267 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2268 // Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0 2269 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2270 // Convert__ARMBranchTarget1_1__CondCode2_0 2271 { CVT_95_addARMBranchTargetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2272 // ConvertCustom_cvtThumbBranches 2273 { CVT_cvtThumbBranches, 0, CVT_Done }, 2274 // Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0 2275 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addBitfieldOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2276 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0 2277 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addBitfieldOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2278 // Convert__imm_95_0 2279 { CVT_imm_95_0, 0, CVT_Done }, 2280 // Convert__Imm0_2551_0 2281 { CVT_95_addImmOperands, 1, CVT_Done }, 2282 // Convert__Imm0_655351_0 2283 { CVT_95_addImmOperands, 1, CVT_Done }, 2284 // Convert__ARMBranchTarget1_0 2285 { CVT_95_addARMBranchTargetOperands, 1, CVT_Done }, 2286 // Convert__CondCode2_0__ThumbBranchTarget1_1 2287 { CVT_95_addCondCodeOperands, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done }, 2288 // Convert__Reg1_0 2289 { CVT_95_Reg, 1, CVT_Done }, 2290 // Convert__ThumbBranchTarget1_0 2291 { CVT_95_addThumbBranchTargetOperands, 1, CVT_Done }, 2292 // Convert__Reg1_1__CondCode2_0 2293 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2294 // Convert__CondCode2_0__Reg1_1 2295 { CVT_95_addCondCodeOperands, 1, CVT_95_Reg, 2, CVT_Done }, 2296 // Convert__CondCode2_0__ARMBranchTarget1_1 2297 { CVT_95_addCondCodeOperands, 1, CVT_95_addARMBranchTargetOperands, 2, CVT_Done }, 2298 // Convert__CondCode2_0 2299 { CVT_95_addCondCodeOperands, 1, CVT_Done }, 2300 // Convert__Reg1_0__ThumbBranchTarget1_1 2301 { CVT_95_Reg, 1, CVT_95_addThumbBranchTargetOperands, 2, CVT_Done }, 2302 // Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0 2303 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2304 // Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5 2305 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, 2306 // Convert__Reg1_1__Reg1_2__CondCode2_0 2307 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2308 // Convert__Reg1_1__ModImmNeg1_2__CondCode2_0 2309 { CVT_95_Reg, 2, CVT_95_addModImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2310 // Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0 2311 { CVT_95_Reg, 2, CVT_95_addT2SOImmNegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2312 // Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0 2313 { CVT_95_Reg, 2, CVT_95_addRegShiftedImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2314 // Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0 2315 { CVT_95_Reg, 2, CVT_95_addRegShiftedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2316 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0 2317 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2318 // Convert__Reg1_1__ModImm1_2__CondCode2_0 2319 { CVT_95_Reg, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2320 // Convert__Reg1_2__Reg1_3__CondCode2_0 2321 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2322 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0 2323 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2324 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0 2325 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2326 // Convert__Reg1_1__Imm0_2551_2__CondCode2_0 2327 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2328 // Convert__Imm0_311_0 2329 { CVT_95_addImmOperands, 1, CVT_Done }, 2330 // Convert__Imm0_311_1 2331 { CVT_95_addImmOperands, 2, CVT_Done }, 2332 // Convert__Imm1_0__ProcIFlags1_1 2333 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_Done }, 2334 // Convert__Imm1_0__ProcIFlags1_2 2335 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_Done }, 2336 // Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2 2337 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 2338 // Convert__Imm1_0__ProcIFlags1_1__Imm1_2 2339 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 2340 // Convert__Imm1_0__ProcIFlags1_2__Imm1_3 2341 { CVT_95_addImmOperands, 1, CVT_95_addProcIFlagsOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, 2342 // Convert__Reg1_0__Reg1_1__Reg1_2 2343 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 2344 // Convert__imm_95_20__CondCode2_0 2345 { CVT_imm_95_20, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2346 // Convert__Imm0_151_1__CondCode2_0 2347 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2348 // Convert__imm_95_12 2349 { CVT_imm_95_12, 0, CVT_Done }, 2350 // Convert__imm_95_12__CondCode2_0 2351 { CVT_imm_95_12, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2352 // Convert__imm_95_15 2353 { CVT_imm_95_15, 0, CVT_Done }, 2354 // Convert__imm_95_15__CondCode2_0 2355 { CVT_imm_95_15, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2356 // Convert__MemBarrierOpt1_0 2357 { CVT_95_addMemBarrierOptOperands, 1, CVT_Done }, 2358 // Convert__MemBarrierOpt1_1__CondCode2_0 2359 { CVT_95_addMemBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2360 // Convert__imm_95_0__CondCode2_0 2361 { CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2362 // Convert__imm_95_16__CondCode2_0 2363 { CVT_imm_95_16, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2364 // Convert__Reg1_1__FPImm1_2__CondCode2_0 2365 { CVT_95_Reg, 2, CVT_95_addFPImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2366 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3 2367 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 4, CVT_Done }, 2368 // Convert__Reg1_1__CondCode2_0__DPRRegList1_2 2369 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done }, 2370 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0 2371 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2372 // Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0 2373 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2374 // Convert__Imm0_2391_1__CondCode2_0 2375 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2376 // Convert__Imm0_2391_2__CondCode2_0 2377 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2378 // Convert__Imm0_631_0 2379 { CVT_95_addImmOperands, 1, CVT_Done }, 2380 // Convert__Imm0_655351_1 2381 { CVT_95_addImmOperands, 2, CVT_Done }, 2382 // Convert__InstSyncBarrierOpt1_0 2383 { CVT_95_addInstSyncBarrierOptOperands, 1, CVT_Done }, 2384 // Convert__InstSyncBarrierOpt1_1__CondCode2_0 2385 { CVT_95_addInstSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2386 // Convert__ITCondCode1_1__ITMask1_0 2387 { CVT_95_addITCondCodeOperands, 2, CVT_95_addITMaskOperands, 1, CVT_Done }, 2388 // Convert__Reg1_1__MemNoOffset1_2__CondCode2_0 2389 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2390 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0 2391 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2392 // Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0 2393 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2394 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0 2395 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addCoprocOptionOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2396 // Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0 2397 { CVT_95_addCoprocNumOperands, 2, CVT_95_addCoprocRegOperands, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_95_addPostIdxImm8s4Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2398 // Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2 2399 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addAddrMode5Operands, 3, CVT_Done }, 2400 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3 2401 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addCoprocOptionOperands, 4, CVT_Done }, 2402 // Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3 2403 { CVT_95_addCoprocNumOperands, 1, CVT_95_addCoprocRegOperands, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_95_addPostIdxImm8s4Operands, 4, CVT_Done }, 2404 // Convert__Reg1_1__CondCode2_0__RegList1_2 2405 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done }, 2406 // Convert__Reg1_2__CondCode2_0__RegList1_3 2407 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done }, 2408 // Convert__Reg1_1__CondCode2_0__RegList1_3 2409 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done }, 2410 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3 2411 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 4, CVT_Done }, 2412 // Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4 2413 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 5, CVT_Done }, 2414 // Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0 2415 { CVT_95_Reg, 2, CVT_95_addThumbMemPCOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2416 // Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0 2417 { CVT_95_Reg, 2, CVT_95_addConstPoolAsmImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2418 // Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0 2419 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs4Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2420 // Convert__Reg1_1__MemThumbRR2_2__CondCode2_0 2421 { CVT_95_Reg, 2, CVT_95_addMemThumbRROperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2422 // Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0 2423 { CVT_95_Reg, 2, CVT_95_addMemThumbSPIOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2424 // Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0 2425 { CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2426 // Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0 2427 { CVT_95_Reg, 2, CVT_95_addMemNegImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2428 // Convert__Reg1_1__MemRegOffset3_2__CondCode2_0 2429 { CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2430 // Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0 2431 { CVT_95_Reg, 2, CVT_95_addMemUImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2432 // Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0 2433 { CVT_95_Reg, 2, CVT_95_addT2MemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2434 // Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0 2435 { CVT_95_Reg, 2, CVT_95_addMemPCRelImm12Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2436 // Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0 2437 { CVT_95_Reg, 3, CVT_95_addConstPoolAsmImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2438 // Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0 2439 { CVT_95_Reg, 3, CVT_95_addMemUImm12OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2440 // Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0 2441 { CVT_95_Reg, 3, CVT_95_addT2MemRegOffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2442 // Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0 2443 { CVT_95_Reg, 3, CVT_95_addMemPCRelImm12Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2444 // Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0 2445 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2446 // Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0 2447 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2448 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0 2449 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2450 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0 2451 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2452 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0 2453 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2454 // Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0 2455 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2456 // Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0 2457 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs1Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2458 // Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0 2459 { CVT_95_Reg, 2, CVT_95_addMemPosImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2460 // Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0 2461 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2462 // Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0 2463 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2464 // Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0 2465 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2466 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0 2467 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2468 // Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0 2469 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2470 // Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0 2471 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemNoOffsetOperands, 4, CVT_Tied, Tie2_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2472 // Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0 2473 { CVT_95_Reg, 2, CVT_95_addMemImm0_95_1020s4OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2474 // Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0 2475 { CVT_95_Reg, 2, CVT_95_addMemThumbRIs2Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2476 // Convert__Reg1_1__AddrMode33_2__CondCode2_0 2477 { CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2478 // Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0 2479 { CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2480 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0 2481 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2482 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0 2483 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2484 // Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0 2485 { CVT_95_Reg, 2, CVT_95_addMemNoOffsetOperands, 3, CVT_Tied, Tie1_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2486 // Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1 2487 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2488 // Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0 2489 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2490 // Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0 2491 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2492 // Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0 2493 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2494 // Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1 2495 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2496 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0 2497 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2498 // Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0 2499 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2500 // Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0 2501 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2502 // Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0 2503 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2504 // Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0 2505 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2506 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0 2507 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2508 // Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0 2509 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2510 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0 2511 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done }, 2512 // Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5 2513 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, 2514 // Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0 2515 { CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2516 // Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4 2517 { CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocRegOperands, 5, CVT_Done }, 2518 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0 2519 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2520 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0 2521 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2522 // Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0 2523 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2524 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0 2525 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 2526 // Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0 2527 { CVT_95_Reg, 2, CVT_95_addT2SOImmNotOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 2528 // Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0 2529 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2530 // Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1 2531 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2532 // Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0 2533 { CVT_95_Reg, 3, CVT_95_addModImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2534 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0 2535 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2536 // Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0 2537 { CVT_95_Reg, 3, CVT_95_addModImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2538 // Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0 2539 { CVT_95_Reg, 3, CVT_95_addRegShiftedImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2540 // Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0 2541 { CVT_95_Reg, 3, CVT_95_addRegShiftedRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2542 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0 2543 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 2544 // Convert__Reg1_2__Reg1_3__CondCode2_0__reg0 2545 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 2546 // Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0 2547 { CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2548 // Convert__Reg1_0__Reg1_1 2549 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, 2550 // Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0 2551 { CVT_95_Reg, 1, CVT_regCPSR, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 2552 // Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR 2553 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 2554 // Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR 2555 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 2556 // Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR 2557 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 2558 // Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR 2559 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_regCPSR, 0, CVT_Done }, 2560 // Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0 2561 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2562 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0 2563 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2564 // Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0 2565 { CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 5, CVT_95_addCoprocRegOperands, 6, CVT_95_addImmOperands, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2566 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0 2567 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_imm_95_0, 0, CVT_Done }, 2568 // Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5 2569 { CVT_95_Reg, 3, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 4, CVT_95_addCoprocRegOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, 2570 // Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0 2571 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCoprocNumOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addCoprocRegOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2572 // Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4 2573 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCoprocNumOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addCoprocRegOperands, 5, CVT_Done }, 2574 // Convert__Reg1_1__BankedReg1_2__CondCode2_0 2575 { CVT_95_Reg, 2, CVT_95_addBankedRegOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2576 // Convert__Reg1_1__MSRMask1_2__CondCode2_0 2577 { CVT_95_Reg, 2, CVT_95_addMSRMaskOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2578 // Convert__BankedReg1_1__Reg1_2__CondCode2_0 2579 { CVT_95_addBankedRegOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2580 // Convert__MSRMask1_1__Reg1_2__CondCode2_0 2581 { CVT_95_addMSRMaskOperands, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2582 // Convert__MSRMask1_1__ModImm1_2__CondCode2_0 2583 { CVT_95_addMSRMaskOperands, 2, CVT_95_addModImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2584 // Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0 2585 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2586 // ConvertCustom_cvtThumbMultiply 2587 { CVT_cvtThumbMultiply, 0, CVT_Done }, 2588 // Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1 2589 { CVT_95_Reg, 3, CVT_95_addCCOutOperands, 1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 2, CVT_Done }, 2590 // Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0 2591 { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2592 // Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0 2593 { CVT_95_Reg, 3, CVT_95_addT2SOImmNotOperands, 4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2594 // Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0 2595 { CVT_95_Reg, 4, CVT_95_addRegShiftedImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2596 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0 2597 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2598 // Convert__regR8__regR8__imm_95_14__imm_95_0 2599 { CVT_regR8, 0, CVT_regR8, 0, CVT_imm_95_14, 0, CVT_imm_95_0, 0, CVT_Done }, 2600 // Convert__regR0__regR0__CondCode2_0__reg0 2601 { CVT_regR0, 0, CVT_regR0, 0, CVT_95_addCondCodeOperands, 1, CVT_reg0, 0, CVT_Done }, 2602 // Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0 2603 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2604 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0 2605 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2606 // Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0 2607 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2608 // Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0 2609 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addPKHASRImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2610 // Convert__MemImm12Offset2_0 2611 { CVT_95_addMemImm12OffsetOperands, 1, CVT_Done }, 2612 // Convert__MemRegOffset3_0 2613 { CVT_95_addMemRegOffsetOperands, 1, CVT_Done }, 2614 // Convert__Imm1_1__CondCode2_0 2615 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2616 // Convert__MemNegImm8Offset2_1__CondCode2_0 2617 { CVT_95_addMemNegImm8OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2618 // Convert__MemUImm12Offset2_1__CondCode2_0 2619 { CVT_95_addMemUImm12OffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2620 // Convert__T2MemRegOffset3_1__CondCode2_0 2621 { CVT_95_addT2MemRegOffsetOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2622 // Convert__MemPCRelImm121_1__CondCode2_0 2623 { CVT_95_addMemPCRelImm12Operands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2624 // Convert__CondCode2_0__RegList1_1 2625 { CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done }, 2626 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1 2627 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 2, CVT_Done }, 2628 // Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2 2629 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addRegListOperands, 3, CVT_Done }, 2630 // Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0 2631 { CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2632 // Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0 2633 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2634 // Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0 2635 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addImm1_95_32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2636 // Convert__SetEndImm1_0 2637 { CVT_95_addImmOperands, 1, CVT_Done }, 2638 // Convert__Imm0_11_0 2639 { CVT_95_addImmOperands, 1, CVT_Done }, 2640 // Convert__imm_95_4__CondCode2_0 2641 { CVT_imm_95_4, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2642 // Convert__imm_95_5__CondCode2_0 2643 { CVT_imm_95_5, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2644 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3 2645 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 2646 // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0 2647 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2648 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0 2649 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2650 // Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0 2651 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 2, CVT_95_addCCOutOperands, 1, CVT_Done }, 2652 // Convert__Imm0_311_2 2653 { CVT_95_addImmOperands, 3, CVT_Done }, 2654 // Convert__Imm0_311_1__CondCode2_0 2655 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2656 // Convert__Imm0_311_2__CondCode2_0 2657 { CVT_95_addImmOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2658 // Convert__Imm0_311_3__CondCode2_0 2659 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2660 // Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0 2661 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2662 // Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0 2663 { CVT_95_Reg, 2, CVT_95_addImm1_95_32Operands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2664 // Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0 2665 { CVT_95_Reg, 2, CVT_95_addImm1_95_16Operands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2666 // Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0 2667 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addMemNoOffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2668 // Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0 2669 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2670 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0 2671 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2672 // Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0 2673 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemImm12OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2674 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0 2675 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM2OffsetImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2676 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0 2677 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegShiftedOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2678 // Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0 2679 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addMemRegOffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2680 // Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0 2681 { CVT_95_Reg, 2, CVT_95_addMemImm8OffsetOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2682 // Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0 2683 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm8s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2684 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0 2685 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2686 // Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0 2687 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addAddrMode3Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2688 // Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0 2689 { CVT_95_addMemNoOffsetOperands, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_4_4, CVT_95_addAM3OffsetOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2690 // Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0 2691 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMemImm0_95_1020s4OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2692 // Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0 2693 { CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_95_addAddrMode3Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2694 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0 2695 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addAM3OffsetOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2696 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0 2697 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxImm8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2698 // Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0 2699 { CVT_95_addMemNoOffsetOperands, 3, CVT_95_Reg, 2, CVT_Tied, Tie0_3_3, CVT_95_addPostIdxRegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2700 // Convert__Imm0_2551_3__CondCode2_0 2701 { CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2702 // Convert__Imm0_2551_1__CondCode2_0 2703 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2704 // Convert__Imm24bit1_1__CondCode2_0 2705 { CVT_95_addImmOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2706 // Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0 2707 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2708 // Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0 2709 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2710 // Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0 2711 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2712 // Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0 2713 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRotImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2714 // Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0 2715 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addRotImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2716 // Convert__MemTBB2_1__CondCode2_0 2717 { CVT_95_addMemTBBOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2718 // Convert__MemTBH2_1__CondCode2_0 2719 { CVT_95_addMemTBHOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2720 // Convert__TraceSyncBarrierOpt1_0 2721 { CVT_95_addTraceSyncBarrierOptOperands, 1, CVT_Done }, 2722 // Convert__TraceSyncBarrierOpt1_1__CondCode2_0 2723 { CVT_95_addTraceSyncBarrierOptOperands, 2, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2724 // Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0 2725 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2726 // Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0 2727 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addShifterImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2728 // Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0 2729 { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2730 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0 2731 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2732 // Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0 2733 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2734 // Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0 2735 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2736 // Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0 2737 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2738 // Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0 2739 { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2740 // Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0 2741 { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2742 // Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0 2743 { CVT_95_Reg, 3, CVT_95_addNEONi16splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2744 // Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0 2745 { CVT_95_Reg, 3, CVT_95_addNEONi32splatNotOperands, 4, CVT_Tied, Tie0_3_3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2746 // Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0 2747 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2748 // Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0 2749 { CVT_95_Reg, 3, CVT_95_addNEONi32splatOperands, 4, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2750 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0 2751 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2752 // Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0 2753 { CVT_95_Reg, 3, CVT_Tied, Tie0_3_3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2754 // Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4 2755 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationOddOperands, 5, CVT_Done }, 2756 // Convert__Reg1_2__Reg1_2__CondCode2_0 2757 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2758 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4 2759 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addComplexRotationEvenOperands, 5, CVT_Done }, 2760 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5 2761 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex64Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done }, 2762 // Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5 2763 { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addComplexRotationEvenOperands, 6, CVT_Done }, 2764 // Convert__Reg1_2__CondCode2_0 2765 { CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2766 // Convert__Reg1_3__Reg1_4__CondCode2_0 2767 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2768 // Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0 2769 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2770 // Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0 2771 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2772 // Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0 2773 { CVT_95_Reg, 4, CVT_Tied, Tie0_4_5, CVT_95_addFBits32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2774 // Convert__Reg1_2__Reg1_3 2775 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 2776 // Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0 2777 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2778 // Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0 2779 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2780 // Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0 2781 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex8Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2782 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0 2783 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2784 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0 2785 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2786 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0 2787 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2788 // Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0 2789 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2790 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0 2791 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2792 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0 2793 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2794 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0 2795 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2796 // Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0 2797 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2798 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0 2799 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2800 // Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0 2801 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2802 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0 2803 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2804 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0 2805 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2806 // Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0 2807 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2808 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0 2809 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2810 // Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0 2811 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2812 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 2813 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2814 // Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 2815 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2816 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0 2817 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2818 // Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 2819 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2820 // Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 2821 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2822 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 2823 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2824 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0 2825 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2826 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0 2827 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2828 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0 2829 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2830 // Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 2831 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2832 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0 2833 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2834 // Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0 2835 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2836 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0 2837 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2838 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0 2839 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2840 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0 2841 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2842 // Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0 2843 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2844 // Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0 2845 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2846 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0 2847 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2848 // Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0 2849 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2850 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0 2851 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2852 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0 2853 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2854 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0 2855 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2856 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0 2857 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2858 // Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 2859 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2860 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0 2861 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2862 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 2863 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2864 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0 2865 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2866 // Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 2867 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2868 // Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 2869 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2870 // Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0 2871 { CVT_95_Reg, 4, CVT_95_addAlignedMemoryOperands, 9, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2872 // Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0 2873 { CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2874 // Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0 2875 { CVT_95_Reg, 4, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2876 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 2877 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2878 // Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0 2879 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2880 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0 2881 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2882 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0 2883 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2884 // Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 2885 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2886 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 2887 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2888 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0 2889 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2890 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0 2891 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2892 // Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0 2893 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2894 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0 2895 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2896 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0 2897 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2898 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0 2899 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2900 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0 2901 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2902 // Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 2903 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2904 // Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 2905 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2906 // Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 2907 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2908 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0 2909 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2910 // Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0 2911 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2912 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0 2913 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2914 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0 2915 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2916 // Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 2917 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2918 // Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 2919 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2920 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0 2921 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2922 // Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0 2923 { CVT_95_addVecListOperands, 3, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2924 // Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0 2925 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory16Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2926 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 2927 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2928 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 2929 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2930 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0 2931 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2932 // Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0 2933 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2934 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 2935 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2936 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 2937 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2938 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 2939 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2940 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0 2941 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2942 // Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 2943 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2944 // Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0 2945 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2946 // Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 2947 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2948 // Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0 2949 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2950 // Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0 2951 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2952 // Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 2953 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2954 // Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 2955 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2956 // Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 2957 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2958 // Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0 2959 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemoryNoneOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2960 // Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0 2961 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2962 // Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0 2963 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2964 // Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0 2965 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_addAlignedMemoryOperands, 14, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2966 // Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0 2967 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_imm_95_0, 0, CVT_95_addDupAlignedMemory64Operands, 14, CVT_95_addImmOperands, 15, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2968 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 2969 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2970 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0 2971 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2972 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0 2973 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2974 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0 2975 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2976 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0 2977 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2978 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0 2979 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2980 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0 2981 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2982 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0 2983 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2984 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0 2985 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2986 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 2987 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2988 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0 2989 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2990 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0 2991 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2992 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0 2993 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2994 // Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0 2995 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2996 // Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 2997 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 2998 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0 2999 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3000 // Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0 3001 { CVT_95_addVecListOperands, 3, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3002 // Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0 3003 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3004 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0 3005 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3006 // Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 3007 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3008 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0 3009 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3010 // Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0 3011 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3012 // Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3013 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3014 // Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0 3015 { CVT_95_addVecListIndexedOperands, 3, CVT_95_addAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3016 // Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0 3017 { CVT_95_addVecListOperands, 3, CVT_95_addDupAlignedMemory32Operands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3018 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0 3019 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3020 // Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0 3021 { CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3022 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0 3023 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3024 // Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0 3025 { CVT_95_Reg, 4, CVT_95_Reg, 7, CVT_95_Reg, 10, CVT_95_Reg, 13, CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 17, CVT_95_addImmOperands, 18, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3026 // Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3 3027 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 4, CVT_Done }, 3028 // Convert__Reg1_1__CondCode2_0__SPRRegList1_2 3029 { CVT_95_Reg, 2, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done }, 3030 // Convert__Reg1_1__AddrMode52_2__CondCode2_0 3031 { CVT_95_Reg, 2, CVT_95_addAddrMode5Operands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3032 // Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0 3033 { CVT_95_Reg, 3, CVT_95_addAddrMode5FP16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3034 // Convert__Reg1_2__AddrMode52_3__CondCode2_0 3035 { CVT_95_Reg, 3, CVT_95_addAddrMode5Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3036 // Convert__Reg1_1__Reg1_2__Reg1_3 3037 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3038 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0 3039 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3040 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0 3041 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3042 // Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0 3043 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3044 // Convert__Reg1_2__FPImm1_3__CondCode2_0 3045 { CVT_95_Reg, 3, CVT_95_addFPImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3046 // Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0 3047 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3048 // Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0 3049 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3050 // Convert__Reg1_2__NEONi16splat1_3__CondCode2_0 3051 { CVT_95_Reg, 3, CVT_95_addNEONi16splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3052 // Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0 3053 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3054 // Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0 3055 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3056 // Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0 3057 { CVT_95_Reg, 3, CVT_95_addNEONi32vmovNegOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3058 // Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0 3059 { CVT_95_Reg, 3, CVT_95_addNEONvmovi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3060 // Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0 3061 { CVT_95_Reg, 3, CVT_95_addNEONvmovi16ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3062 // Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0 3063 { CVT_95_Reg, 3, CVT_95_addNEONvmovi32ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3064 // Convert__Reg1_2__NEONi64splat1_3__CondCode2_0 3065 { CVT_95_Reg, 3, CVT_95_addNEONi64splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3066 // Convert__Reg1_2__NEONi8splat1_3__CondCode2_0 3067 { CVT_95_Reg, 3, CVT_95_addNEONi8splatOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3068 // Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0 3069 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3070 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0 3071 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3072 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0 3073 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3074 // Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0 3075 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 5, CVT_95_addVectorIndex8Operands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3076 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0 3077 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3078 // Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0 3079 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex16Operands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3080 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0 3081 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex32Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3082 // Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0 3083 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_addVectorIndex16Operands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3084 // Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0 3085 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3086 // Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0 3087 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3088 // Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0 3089 { CVT_95_Reg, 3, CVT_95_addNEONinvi8ReplicateOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3090 // Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0 3091 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3092 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1 3093 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 2, CVT_Done }, 3094 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1 3095 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 2, CVT_Done }, 3096 // Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2 3097 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addDPRRegListOperands, 3, CVT_Done }, 3098 // Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2 3099 { CVT_regSP, 0, CVT_Tied, Tie0_1_1, CVT_95_addCondCodeOperands, 1, CVT_95_addSPRRegListOperands, 3, CVT_Done }, 3100 // Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0 3101 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3102 // Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0 3103 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3104 // Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0 3105 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3106 // Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0 3107 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3108 // Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0 3109 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3110 // Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0 3111 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3112 // Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0 3113 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3114 // Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0 3115 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3116 // Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0 3117 { CVT_95_Reg, 3, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3118 // Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0 3119 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3120 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0 3121 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3122 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0 3123 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3124 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0 3125 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3126 // Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0 3127 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3128 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0 3129 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3130 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0 3131 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3132 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0 3133 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3134 // Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0 3135 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3136 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3 3137 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, 3138 // Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4 3139 { CVT_95_Reg, 2, CVT_Tied, Tie0_2_2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addVectorIndex32Operands, 5, CVT_Done }, 3140 // Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0 3141 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3142 // Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0 3143 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3144 // Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0 3145 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3146 // Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0 3147 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3148 // Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0 3149 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3150 // Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0 3151 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3152 // Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0 3153 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3154 // Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0 3155 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3156 // Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0 3157 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3158 // Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0 3159 { CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3160 // Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0 3161 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3162 // Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0 3163 { CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3164 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0 3165 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3166 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0 3167 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3168 // Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0 3169 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3170 // Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0 3171 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128or256Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3172 // Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0 3173 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3174 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0 3175 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3176 // Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0 3177 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3178 // Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0 3179 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3180 // Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0 3181 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3182 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0 3183 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3184 // Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0 3185 { CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3186 // Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0 3187 { CVT_imm_95_0, 0, CVT_95_Reg, 9, CVT_95_addImmOperands, 10, CVT_95_addImmOperands, 11, CVT_95_Reg, 4, CVT_95_addImmOperands, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3188 // Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0 3189 { CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3190 // Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0 3191 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3192 // Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0 3193 { CVT_imm_95_0, 0, CVT_95_addAlignedMemory64or128Operands, 4, CVT_95_Reg, 5, CVT_95_addVecListOperands, 3, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3194 // Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0 3195 { CVT_95_addAlignedMemoryOperands, 8, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3196 // Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0 3197 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 8, CVT_95_addImmOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3198 // Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0 3199 { CVT_95_addAlignedMemoryOperands, 9, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3200 // Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0 3201 { CVT_imm_95_0, 0, CVT_95_addAlignedMemoryOperands, 9, CVT_95_addImmOperands, 10, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3202 // Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0 3203 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3204 // Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0 3205 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_3_3, CVT_Tied, Tie1_4_4, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3206 // Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0 3207 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3208 // Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0 3209 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3210 // Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0 3211 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3212 // Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0 3213 { CVT_95_Reg, 3, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3214 // Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0 3215 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3216 // Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0 3217 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3218 // Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0 3219 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3220 // Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0 3221 { CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_95_addVecListOperands, 4, CVT_95_Reg, 5, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3222 // Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0 3223 { CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3224 // Convert__imm_95_2__CondCode2_0 3225 { CVT_imm_95_2, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3226 // Convert__imm_95_3__CondCode2_0 3227 { CVT_imm_95_3, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3228 // Convert__imm_95_1__CondCode2_0 3229 { CVT_imm_95_1, 0, CVT_95_addCondCodeOperands, 1, CVT_Done }, 3230}; 3231 3232void ARMAsmParser:: 3233convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 3234 const OperandVector &Operands) { 3235 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 3236 const uint8_t *Converter = ConversionTable[Kind]; 3237 unsigned OpIdx; 3238 Inst.setOpcode(Opcode); 3239 for (const uint8_t *p = Converter; *p; p+= 2) { 3240 OpIdx = *(p + 1); 3241 switch (*p) { 3242 default: llvm_unreachable("invalid conversion entry!"); 3243 case CVT_Reg: 3244 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 3245 break; 3246 case CVT_Tied: { 3247 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 3248 std::begin(TiedAsmOperandTable)) && 3249 "Tied operand not found"); 3250 unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; 3251 if (TiedResOpnd != (uint8_t) -1) 3252 Inst.addOperand(Inst.getOperand(TiedResOpnd)); 3253 break; 3254 } 3255 case CVT_95_Reg: 3256 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 3257 break; 3258 case CVT_95_addCCOutOperands: 3259 static_cast<ARMOperand&>(*Operands[OpIdx]).addCCOutOperands(Inst, 1); 3260 break; 3261 case CVT_95_addCondCodeOperands: 3262 static_cast<ARMOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 2); 3263 break; 3264 case CVT_95_addRegShiftedRegOperands: 3265 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedRegOperands(Inst, 3); 3266 break; 3267 case CVT_95_addModImmOperands: 3268 static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmOperands(Inst, 1); 3269 break; 3270 case CVT_95_addModImmNotOperands: 3271 static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNotOperands(Inst, 1); 3272 break; 3273 case CVT_95_addRegShiftedImmOperands: 3274 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegShiftedImmOperands(Inst, 2); 3275 break; 3276 case CVT_95_addImmOperands: 3277 static_cast<ARMOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1); 3278 break; 3279 case CVT_95_addT2SOImmNotOperands: 3280 static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNotOperands(Inst, 1); 3281 break; 3282 case CVT_95_addImm0_95_508s4Operands: 3283 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4Operands(Inst, 1); 3284 break; 3285 case CVT_regSP: 3286 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3287 break; 3288 case CVT_95_addImm0_95_508s4NegOperands: 3289 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_508s4NegOperands(Inst, 1); 3290 break; 3291 case CVT_95_addImm0_95_4095NegOperands: 3292 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_4095NegOperands(Inst, 1); 3293 break; 3294 case CVT_95_addThumbModImmNeg8_95_255Operands: 3295 static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg8_255Operands(Inst, 1); 3296 break; 3297 case CVT_95_addT2SOImmNegOperands: 3298 static_cast<ARMOperand&>(*Operands[OpIdx]).addT2SOImmNegOperands(Inst, 1); 3299 break; 3300 case CVT_95_addModImmNegOperands: 3301 static_cast<ARMOperand&>(*Operands[OpIdx]).addModImmNegOperands(Inst, 1); 3302 break; 3303 case CVT_95_addImm0_95_1020s4Operands: 3304 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm0_1020s4Operands(Inst, 1); 3305 break; 3306 case CVT_95_addThumbModImmNeg1_95_7Operands: 3307 static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbModImmNeg1_7Operands(Inst, 1); 3308 break; 3309 case CVT_95_addUnsignedOffset_95_b8s2Operands: 3310 static_cast<ARMOperand&>(*Operands[OpIdx]).addUnsignedOffset_b8s2Operands(Inst, 1); 3311 break; 3312 case CVT_95_addAdrLabelOperands: 3313 static_cast<ARMOperand&>(*Operands[OpIdx]).addAdrLabelOperands(Inst, 1); 3314 break; 3315 case CVT_95_addARMBranchTargetOperands: 3316 static_cast<ARMOperand&>(*Operands[OpIdx]).addARMBranchTargetOperands(Inst, 1); 3317 break; 3318 case CVT_cvtThumbBranches: 3319 cvtThumbBranches(Inst, Operands); 3320 break; 3321 case CVT_95_addBitfieldOperands: 3322 static_cast<ARMOperand&>(*Operands[OpIdx]).addBitfieldOperands(Inst, 1); 3323 break; 3324 case CVT_imm_95_0: 3325 Inst.addOperand(MCOperand::createImm(0)); 3326 break; 3327 case CVT_95_addThumbBranchTargetOperands: 3328 static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbBranchTargetOperands(Inst, 1); 3329 break; 3330 case CVT_95_addCoprocNumOperands: 3331 static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocNumOperands(Inst, 1); 3332 break; 3333 case CVT_95_addCoprocRegOperands: 3334 static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocRegOperands(Inst, 1); 3335 break; 3336 case CVT_95_addProcIFlagsOperands: 3337 static_cast<ARMOperand&>(*Operands[OpIdx]).addProcIFlagsOperands(Inst, 1); 3338 break; 3339 case CVT_imm_95_20: 3340 Inst.addOperand(MCOperand::createImm(20)); 3341 break; 3342 case CVT_imm_95_12: 3343 Inst.addOperand(MCOperand::createImm(12)); 3344 break; 3345 case CVT_imm_95_15: 3346 Inst.addOperand(MCOperand::createImm(15)); 3347 break; 3348 case CVT_95_addMemBarrierOptOperands: 3349 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemBarrierOptOperands(Inst, 1); 3350 break; 3351 case CVT_imm_95_16: 3352 Inst.addOperand(MCOperand::createImm(16)); 3353 break; 3354 case CVT_95_addFPImmOperands: 3355 static_cast<ARMOperand&>(*Operands[OpIdx]).addFPImmOperands(Inst, 1); 3356 break; 3357 case CVT_95_addDPRRegListOperands: 3358 static_cast<ARMOperand&>(*Operands[OpIdx]).addDPRRegListOperands(Inst, 1); 3359 break; 3360 case CVT_imm_95_1: 3361 Inst.addOperand(MCOperand::createImm(1)); 3362 break; 3363 case CVT_95_addInstSyncBarrierOptOperands: 3364 static_cast<ARMOperand&>(*Operands[OpIdx]).addInstSyncBarrierOptOperands(Inst, 1); 3365 break; 3366 case CVT_95_addITCondCodeOperands: 3367 static_cast<ARMOperand&>(*Operands[OpIdx]).addITCondCodeOperands(Inst, 1); 3368 break; 3369 case CVT_95_addITMaskOperands: 3370 static_cast<ARMOperand&>(*Operands[OpIdx]).addITMaskOperands(Inst, 1); 3371 break; 3372 case CVT_95_addMemNoOffsetOperands: 3373 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNoOffsetOperands(Inst, 1); 3374 break; 3375 case CVT_95_addAddrMode5Operands: 3376 static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5Operands(Inst, 2); 3377 break; 3378 case CVT_95_addCoprocOptionOperands: 3379 static_cast<ARMOperand&>(*Operands[OpIdx]).addCoprocOptionOperands(Inst, 1); 3380 break; 3381 case CVT_95_addPostIdxImm8s4Operands: 3382 static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8s4Operands(Inst, 1); 3383 break; 3384 case CVT_95_addRegListOperands: 3385 static_cast<ARMOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1); 3386 break; 3387 case CVT_95_addThumbMemPCOperands: 3388 static_cast<ARMOperand&>(*Operands[OpIdx]).addThumbMemPCOperands(Inst, 1); 3389 break; 3390 case CVT_95_addConstPoolAsmImmOperands: 3391 static_cast<ARMOperand&>(*Operands[OpIdx]).addConstPoolAsmImmOperands(Inst, 1); 3392 break; 3393 case CVT_95_addMemThumbRIs4Operands: 3394 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs4Operands(Inst, 2); 3395 break; 3396 case CVT_95_addMemThumbRROperands: 3397 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRROperands(Inst, 2); 3398 break; 3399 case CVT_95_addMemThumbSPIOperands: 3400 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbSPIOperands(Inst, 2); 3401 break; 3402 case CVT_95_addMemImm12OffsetOperands: 3403 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm12OffsetOperands(Inst, 2); 3404 break; 3405 case CVT_95_addMemNegImm8OffsetOperands: 3406 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemNegImm8OffsetOperands(Inst, 2); 3407 break; 3408 case CVT_95_addMemRegOffsetOperands: 3409 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemRegOffsetOperands(Inst, 3); 3410 break; 3411 case CVT_95_addMemUImm12OffsetOperands: 3412 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemUImm12OffsetOperands(Inst, 2); 3413 break; 3414 case CVT_95_addT2MemRegOffsetOperands: 3415 static_cast<ARMOperand&>(*Operands[OpIdx]).addT2MemRegOffsetOperands(Inst, 3); 3416 break; 3417 case CVT_95_addMemPCRelImm12Operands: 3418 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPCRelImm12Operands(Inst, 1); 3419 break; 3420 case CVT_95_addMemImm8OffsetOperands: 3421 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8OffsetOperands(Inst, 2); 3422 break; 3423 case CVT_95_addAM2OffsetImmOperands: 3424 static_cast<ARMOperand&>(*Operands[OpIdx]).addAM2OffsetImmOperands(Inst, 2); 3425 break; 3426 case CVT_95_addPostIdxRegShiftedOperands: 3427 static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegShiftedOperands(Inst, 2); 3428 break; 3429 case CVT_95_addMemThumbRIs1Operands: 3430 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs1Operands(Inst, 2); 3431 break; 3432 case CVT_95_addMemPosImm8OffsetOperands: 3433 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemPosImm8OffsetOperands(Inst, 2); 3434 break; 3435 case CVT_95_addMemImm8s4OffsetOperands: 3436 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm8s4OffsetOperands(Inst, 2); 3437 break; 3438 case CVT_95_addAddrMode3Operands: 3439 static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode3Operands(Inst, 3); 3440 break; 3441 case CVT_95_addAM3OffsetOperands: 3442 static_cast<ARMOperand&>(*Operands[OpIdx]).addAM3OffsetOperands(Inst, 2); 3443 break; 3444 case CVT_95_addMemImm0_95_1020s4OffsetOperands: 3445 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemImm0_1020s4OffsetOperands(Inst, 2); 3446 break; 3447 case CVT_95_addMemThumbRIs2Operands: 3448 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemThumbRIs2Operands(Inst, 2); 3449 break; 3450 case CVT_95_addPostIdxRegOperands: 3451 static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxRegOperands(Inst, 2); 3452 break; 3453 case CVT_95_addPostIdxImm8Operands: 3454 static_cast<ARMOperand&>(*Operands[OpIdx]).addPostIdxImm8Operands(Inst, 1); 3455 break; 3456 case CVT_reg0: 3457 Inst.addOperand(MCOperand::createReg(0)); 3458 break; 3459 case CVT_regCPSR: 3460 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 3461 break; 3462 case CVT_imm_95_14: 3463 Inst.addOperand(MCOperand::createImm(14)); 3464 break; 3465 case CVT_95_addBankedRegOperands: 3466 static_cast<ARMOperand&>(*Operands[OpIdx]).addBankedRegOperands(Inst, 1); 3467 break; 3468 case CVT_95_addMSRMaskOperands: 3469 static_cast<ARMOperand&>(*Operands[OpIdx]).addMSRMaskOperands(Inst, 1); 3470 break; 3471 case CVT_cvtThumbMultiply: 3472 cvtThumbMultiply(Inst, Operands); 3473 break; 3474 case CVT_regR8: 3475 Inst.addOperand(MCOperand::createReg(ARM::R8)); 3476 break; 3477 case CVT_regR0: 3478 Inst.addOperand(MCOperand::createReg(ARM::R0)); 3479 break; 3480 case CVT_95_addPKHASRImmOperands: 3481 static_cast<ARMOperand&>(*Operands[OpIdx]).addPKHASRImmOperands(Inst, 1); 3482 break; 3483 case CVT_95_addImm1_95_32Operands: 3484 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_32Operands(Inst, 1); 3485 break; 3486 case CVT_imm_95_4: 3487 Inst.addOperand(MCOperand::createImm(4)); 3488 break; 3489 case CVT_imm_95_5: 3490 Inst.addOperand(MCOperand::createImm(5)); 3491 break; 3492 case CVT_95_addShifterImmOperands: 3493 static_cast<ARMOperand&>(*Operands[OpIdx]).addShifterImmOperands(Inst, 1); 3494 break; 3495 case CVT_95_addImm1_95_16Operands: 3496 static_cast<ARMOperand&>(*Operands[OpIdx]).addImm1_16Operands(Inst, 1); 3497 break; 3498 case CVT_95_addRotImmOperands: 3499 static_cast<ARMOperand&>(*Operands[OpIdx]).addRotImmOperands(Inst, 1); 3500 break; 3501 case CVT_95_addMemTBBOperands: 3502 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBBOperands(Inst, 2); 3503 break; 3504 case CVT_95_addMemTBHOperands: 3505 static_cast<ARMOperand&>(*Operands[OpIdx]).addMemTBHOperands(Inst, 2); 3506 break; 3507 case CVT_95_addTraceSyncBarrierOptOperands: 3508 static_cast<ARMOperand&>(*Operands[OpIdx]).addTraceSyncBarrierOptOperands(Inst, 1); 3509 break; 3510 case CVT_95_addNEONi16splatNotOperands: 3511 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatNotOperands(Inst, 1); 3512 break; 3513 case CVT_95_addNEONi32splatNotOperands: 3514 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatNotOperands(Inst, 1); 3515 break; 3516 case CVT_95_addNEONi16splatOperands: 3517 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi16splatOperands(Inst, 1); 3518 break; 3519 case CVT_95_addNEONi32splatOperands: 3520 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32splatOperands(Inst, 1); 3521 break; 3522 case CVT_95_addComplexRotationOddOperands: 3523 static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationOddOperands(Inst, 1); 3524 break; 3525 case CVT_95_addComplexRotationEvenOperands: 3526 static_cast<ARMOperand&>(*Operands[OpIdx]).addComplexRotationEvenOperands(Inst, 1); 3527 break; 3528 case CVT_95_addVectorIndex64Operands: 3529 static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex64Operands(Inst, 1); 3530 break; 3531 case CVT_95_addVectorIndex32Operands: 3532 static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex32Operands(Inst, 1); 3533 break; 3534 case CVT_95_addFBits16Operands: 3535 static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits16Operands(Inst, 1); 3536 break; 3537 case CVT_95_addFBits32Operands: 3538 static_cast<ARMOperand&>(*Operands[OpIdx]).addFBits32Operands(Inst, 1); 3539 break; 3540 case CVT_95_addVectorIndex16Operands: 3541 static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex16Operands(Inst, 1); 3542 break; 3543 case CVT_95_addVectorIndex8Operands: 3544 static_cast<ARMOperand&>(*Operands[OpIdx]).addVectorIndex8Operands(Inst, 1); 3545 break; 3546 case CVT_95_addVecListOperands: 3547 static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListOperands(Inst, 1); 3548 break; 3549 case CVT_95_addDupAlignedMemory16Operands: 3550 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory16Operands(Inst, 2); 3551 break; 3552 case CVT_95_addAlignedMemory64or128Operands: 3553 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128Operands(Inst, 2); 3554 break; 3555 case CVT_95_addAlignedMemory64or128or256Operands: 3556 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64or128or256Operands(Inst, 2); 3557 break; 3558 case CVT_95_addAlignedMemory64Operands: 3559 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory64Operands(Inst, 2); 3560 break; 3561 case CVT_95_addVecListIndexedOperands: 3562 static_cast<ARMOperand&>(*Operands[OpIdx]).addVecListIndexedOperands(Inst, 2); 3563 break; 3564 case CVT_95_addAlignedMemory16Operands: 3565 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory16Operands(Inst, 2); 3566 break; 3567 case CVT_95_addDupAlignedMemory32Operands: 3568 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory32Operands(Inst, 2); 3569 break; 3570 case CVT_95_addAlignedMemory32Operands: 3571 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemory32Operands(Inst, 2); 3572 break; 3573 case CVT_95_addDupAlignedMemoryNoneOperands: 3574 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemoryNoneOperands(Inst, 2); 3575 break; 3576 case CVT_95_addAlignedMemoryNoneOperands: 3577 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryNoneOperands(Inst, 2); 3578 break; 3579 case CVT_95_addAlignedMemoryOperands: 3580 static_cast<ARMOperand&>(*Operands[OpIdx]).addAlignedMemoryOperands(Inst, 2); 3581 break; 3582 case CVT_95_addDupAlignedMemory64Operands: 3583 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64Operands(Inst, 2); 3584 break; 3585 case CVT_95_addDupAlignedMemory64or128Operands: 3586 static_cast<ARMOperand&>(*Operands[OpIdx]).addDupAlignedMemory64or128Operands(Inst, 2); 3587 break; 3588 case CVT_95_addSPRRegListOperands: 3589 static_cast<ARMOperand&>(*Operands[OpIdx]).addSPRRegListOperands(Inst, 1); 3590 break; 3591 case CVT_95_addAddrMode5FP16Operands: 3592 static_cast<ARMOperand&>(*Operands[OpIdx]).addAddrMode5FP16Operands(Inst, 2); 3593 break; 3594 case CVT_95_addNEONi32vmovOperands: 3595 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovOperands(Inst, 1); 3596 break; 3597 case CVT_95_addNEONvmovi8ReplicateOperands: 3598 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi8ReplicateOperands(Inst, 1); 3599 break; 3600 case CVT_95_addNEONvmovi16ReplicateOperands: 3601 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi16ReplicateOperands(Inst, 1); 3602 break; 3603 case CVT_95_addNEONi32vmovNegOperands: 3604 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi32vmovNegOperands(Inst, 1); 3605 break; 3606 case CVT_95_addNEONvmovi32ReplicateOperands: 3607 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONvmovi32ReplicateOperands(Inst, 1); 3608 break; 3609 case CVT_95_addNEONi64splatOperands: 3610 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi64splatOperands(Inst, 1); 3611 break; 3612 case CVT_95_addNEONi8splatOperands: 3613 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONi8splatOperands(Inst, 1); 3614 break; 3615 case CVT_95_addNEONinvi8ReplicateOperands: 3616 static_cast<ARMOperand&>(*Operands[OpIdx]).addNEONinvi8ReplicateOperands(Inst, 1); 3617 break; 3618 case CVT_imm_95_2: 3619 Inst.addOperand(MCOperand::createImm(2)); 3620 break; 3621 case CVT_imm_95_3: 3622 Inst.addOperand(MCOperand::createImm(3)); 3623 break; 3624 } 3625 } 3626} 3627 3628void ARMAsmParser:: 3629convertToMapAndConstraints(unsigned Kind, 3630 const OperandVector &Operands) { 3631 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 3632 unsigned NumMCOperands = 0; 3633 const uint8_t *Converter = ConversionTable[Kind]; 3634 for (const uint8_t *p = Converter; *p; p+= 2) { 3635 switch (*p) { 3636 default: llvm_unreachable("invalid conversion entry!"); 3637 case CVT_Reg: 3638 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3639 Operands[*(p + 1)]->setConstraint("r"); 3640 ++NumMCOperands; 3641 break; 3642 case CVT_Tied: 3643 ++NumMCOperands; 3644 break; 3645 case CVT_95_Reg: 3646 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3647 Operands[*(p + 1)]->setConstraint("r"); 3648 NumMCOperands += 1; 3649 break; 3650 case CVT_95_addCCOutOperands: 3651 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3652 Operands[*(p + 1)]->setConstraint("m"); 3653 NumMCOperands += 1; 3654 break; 3655 case CVT_95_addCondCodeOperands: 3656 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3657 Operands[*(p + 1)]->setConstraint("m"); 3658 NumMCOperands += 2; 3659 break; 3660 case CVT_95_addRegShiftedRegOperands: 3661 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3662 Operands[*(p + 1)]->setConstraint("m"); 3663 NumMCOperands += 3; 3664 break; 3665 case CVT_95_addModImmOperands: 3666 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3667 Operands[*(p + 1)]->setConstraint("m"); 3668 NumMCOperands += 1; 3669 break; 3670 case CVT_95_addModImmNotOperands: 3671 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3672 Operands[*(p + 1)]->setConstraint("m"); 3673 NumMCOperands += 1; 3674 break; 3675 case CVT_95_addRegShiftedImmOperands: 3676 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3677 Operands[*(p + 1)]->setConstraint("m"); 3678 NumMCOperands += 2; 3679 break; 3680 case CVT_95_addImmOperands: 3681 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3682 Operands[*(p + 1)]->setConstraint("m"); 3683 NumMCOperands += 1; 3684 break; 3685 case CVT_95_addT2SOImmNotOperands: 3686 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3687 Operands[*(p + 1)]->setConstraint("m"); 3688 NumMCOperands += 1; 3689 break; 3690 case CVT_95_addImm0_95_508s4Operands: 3691 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3692 Operands[*(p + 1)]->setConstraint("m"); 3693 NumMCOperands += 1; 3694 break; 3695 case CVT_regSP: 3696 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3697 Operands[*(p + 1)]->setConstraint("m"); 3698 ++NumMCOperands; 3699 break; 3700 case CVT_95_addImm0_95_508s4NegOperands: 3701 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3702 Operands[*(p + 1)]->setConstraint("m"); 3703 NumMCOperands += 1; 3704 break; 3705 case CVT_95_addImm0_95_4095NegOperands: 3706 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3707 Operands[*(p + 1)]->setConstraint("m"); 3708 NumMCOperands += 1; 3709 break; 3710 case CVT_95_addThumbModImmNeg8_95_255Operands: 3711 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3712 Operands[*(p + 1)]->setConstraint("m"); 3713 NumMCOperands += 1; 3714 break; 3715 case CVT_95_addT2SOImmNegOperands: 3716 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3717 Operands[*(p + 1)]->setConstraint("m"); 3718 NumMCOperands += 1; 3719 break; 3720 case CVT_95_addModImmNegOperands: 3721 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3722 Operands[*(p + 1)]->setConstraint("m"); 3723 NumMCOperands += 1; 3724 break; 3725 case CVT_95_addImm0_95_1020s4Operands: 3726 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3727 Operands[*(p + 1)]->setConstraint("m"); 3728 NumMCOperands += 1; 3729 break; 3730 case CVT_95_addThumbModImmNeg1_95_7Operands: 3731 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3732 Operands[*(p + 1)]->setConstraint("m"); 3733 NumMCOperands += 1; 3734 break; 3735 case CVT_95_addUnsignedOffset_95_b8s2Operands: 3736 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3737 Operands[*(p + 1)]->setConstraint("m"); 3738 NumMCOperands += 1; 3739 break; 3740 case CVT_95_addAdrLabelOperands: 3741 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3742 Operands[*(p + 1)]->setConstraint("m"); 3743 NumMCOperands += 1; 3744 break; 3745 case CVT_95_addARMBranchTargetOperands: 3746 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3747 Operands[*(p + 1)]->setConstraint("m"); 3748 NumMCOperands += 1; 3749 break; 3750 case CVT_95_addBitfieldOperands: 3751 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3752 Operands[*(p + 1)]->setConstraint("m"); 3753 NumMCOperands += 1; 3754 break; 3755 case CVT_imm_95_0: 3756 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3757 Operands[*(p + 1)]->setConstraint(""); 3758 ++NumMCOperands; 3759 break; 3760 case CVT_95_addThumbBranchTargetOperands: 3761 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3762 Operands[*(p + 1)]->setConstraint("m"); 3763 NumMCOperands += 1; 3764 break; 3765 case CVT_95_addCoprocNumOperands: 3766 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3767 Operands[*(p + 1)]->setConstraint("m"); 3768 NumMCOperands += 1; 3769 break; 3770 case CVT_95_addCoprocRegOperands: 3771 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3772 Operands[*(p + 1)]->setConstraint("m"); 3773 NumMCOperands += 1; 3774 break; 3775 case CVT_95_addProcIFlagsOperands: 3776 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3777 Operands[*(p + 1)]->setConstraint("m"); 3778 NumMCOperands += 1; 3779 break; 3780 case CVT_imm_95_20: 3781 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3782 Operands[*(p + 1)]->setConstraint(""); 3783 ++NumMCOperands; 3784 break; 3785 case CVT_imm_95_12: 3786 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3787 Operands[*(p + 1)]->setConstraint(""); 3788 ++NumMCOperands; 3789 break; 3790 case CVT_imm_95_15: 3791 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3792 Operands[*(p + 1)]->setConstraint(""); 3793 ++NumMCOperands; 3794 break; 3795 case CVT_95_addMemBarrierOptOperands: 3796 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3797 Operands[*(p + 1)]->setConstraint("m"); 3798 NumMCOperands += 1; 3799 break; 3800 case CVT_imm_95_16: 3801 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3802 Operands[*(p + 1)]->setConstraint(""); 3803 ++NumMCOperands; 3804 break; 3805 case CVT_95_addFPImmOperands: 3806 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3807 Operands[*(p + 1)]->setConstraint("m"); 3808 NumMCOperands += 1; 3809 break; 3810 case CVT_95_addDPRRegListOperands: 3811 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3812 Operands[*(p + 1)]->setConstraint("m"); 3813 NumMCOperands += 1; 3814 break; 3815 case CVT_imm_95_1: 3816 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3817 Operands[*(p + 1)]->setConstraint(""); 3818 ++NumMCOperands; 3819 break; 3820 case CVT_95_addInstSyncBarrierOptOperands: 3821 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3822 Operands[*(p + 1)]->setConstraint("m"); 3823 NumMCOperands += 1; 3824 break; 3825 case CVT_95_addITCondCodeOperands: 3826 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3827 Operands[*(p + 1)]->setConstraint("m"); 3828 NumMCOperands += 1; 3829 break; 3830 case CVT_95_addITMaskOperands: 3831 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3832 Operands[*(p + 1)]->setConstraint("m"); 3833 NumMCOperands += 1; 3834 break; 3835 case CVT_95_addMemNoOffsetOperands: 3836 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3837 Operands[*(p + 1)]->setConstraint("m"); 3838 NumMCOperands += 1; 3839 break; 3840 case CVT_95_addAddrMode5Operands: 3841 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3842 Operands[*(p + 1)]->setConstraint("m"); 3843 NumMCOperands += 2; 3844 break; 3845 case CVT_95_addCoprocOptionOperands: 3846 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3847 Operands[*(p + 1)]->setConstraint("m"); 3848 NumMCOperands += 1; 3849 break; 3850 case CVT_95_addPostIdxImm8s4Operands: 3851 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3852 Operands[*(p + 1)]->setConstraint("m"); 3853 NumMCOperands += 1; 3854 break; 3855 case CVT_95_addRegListOperands: 3856 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3857 Operands[*(p + 1)]->setConstraint("m"); 3858 NumMCOperands += 1; 3859 break; 3860 case CVT_95_addThumbMemPCOperands: 3861 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3862 Operands[*(p + 1)]->setConstraint("m"); 3863 NumMCOperands += 1; 3864 break; 3865 case CVT_95_addConstPoolAsmImmOperands: 3866 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3867 Operands[*(p + 1)]->setConstraint("m"); 3868 NumMCOperands += 1; 3869 break; 3870 case CVT_95_addMemThumbRIs4Operands: 3871 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3872 Operands[*(p + 1)]->setConstraint("m"); 3873 NumMCOperands += 2; 3874 break; 3875 case CVT_95_addMemThumbRROperands: 3876 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3877 Operands[*(p + 1)]->setConstraint("m"); 3878 NumMCOperands += 2; 3879 break; 3880 case CVT_95_addMemThumbSPIOperands: 3881 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3882 Operands[*(p + 1)]->setConstraint("m"); 3883 NumMCOperands += 2; 3884 break; 3885 case CVT_95_addMemImm12OffsetOperands: 3886 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3887 Operands[*(p + 1)]->setConstraint("m"); 3888 NumMCOperands += 2; 3889 break; 3890 case CVT_95_addMemNegImm8OffsetOperands: 3891 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3892 Operands[*(p + 1)]->setConstraint("m"); 3893 NumMCOperands += 2; 3894 break; 3895 case CVT_95_addMemRegOffsetOperands: 3896 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3897 Operands[*(p + 1)]->setConstraint("m"); 3898 NumMCOperands += 3; 3899 break; 3900 case CVT_95_addMemUImm12OffsetOperands: 3901 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3902 Operands[*(p + 1)]->setConstraint("m"); 3903 NumMCOperands += 2; 3904 break; 3905 case CVT_95_addT2MemRegOffsetOperands: 3906 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3907 Operands[*(p + 1)]->setConstraint("m"); 3908 NumMCOperands += 3; 3909 break; 3910 case CVT_95_addMemPCRelImm12Operands: 3911 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3912 Operands[*(p + 1)]->setConstraint("m"); 3913 NumMCOperands += 1; 3914 break; 3915 case CVT_95_addMemImm8OffsetOperands: 3916 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3917 Operands[*(p + 1)]->setConstraint("m"); 3918 NumMCOperands += 2; 3919 break; 3920 case CVT_95_addAM2OffsetImmOperands: 3921 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3922 Operands[*(p + 1)]->setConstraint("m"); 3923 NumMCOperands += 2; 3924 break; 3925 case CVT_95_addPostIdxRegShiftedOperands: 3926 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3927 Operands[*(p + 1)]->setConstraint("m"); 3928 NumMCOperands += 2; 3929 break; 3930 case CVT_95_addMemThumbRIs1Operands: 3931 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3932 Operands[*(p + 1)]->setConstraint("m"); 3933 NumMCOperands += 2; 3934 break; 3935 case CVT_95_addMemPosImm8OffsetOperands: 3936 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3937 Operands[*(p + 1)]->setConstraint("m"); 3938 NumMCOperands += 2; 3939 break; 3940 case CVT_95_addMemImm8s4OffsetOperands: 3941 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3942 Operands[*(p + 1)]->setConstraint("m"); 3943 NumMCOperands += 2; 3944 break; 3945 case CVT_95_addAddrMode3Operands: 3946 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3947 Operands[*(p + 1)]->setConstraint("m"); 3948 NumMCOperands += 3; 3949 break; 3950 case CVT_95_addAM3OffsetOperands: 3951 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3952 Operands[*(p + 1)]->setConstraint("m"); 3953 NumMCOperands += 2; 3954 break; 3955 case CVT_95_addMemImm0_95_1020s4OffsetOperands: 3956 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3957 Operands[*(p + 1)]->setConstraint("m"); 3958 NumMCOperands += 2; 3959 break; 3960 case CVT_95_addMemThumbRIs2Operands: 3961 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3962 Operands[*(p + 1)]->setConstraint("m"); 3963 NumMCOperands += 2; 3964 break; 3965 case CVT_95_addPostIdxRegOperands: 3966 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3967 Operands[*(p + 1)]->setConstraint("m"); 3968 NumMCOperands += 2; 3969 break; 3970 case CVT_95_addPostIdxImm8Operands: 3971 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3972 Operands[*(p + 1)]->setConstraint("m"); 3973 NumMCOperands += 1; 3974 break; 3975 case CVT_reg0: 3976 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3977 Operands[*(p + 1)]->setConstraint("m"); 3978 ++NumMCOperands; 3979 break; 3980 case CVT_regCPSR: 3981 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3982 Operands[*(p + 1)]->setConstraint("m"); 3983 ++NumMCOperands; 3984 break; 3985 case CVT_imm_95_14: 3986 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3987 Operands[*(p + 1)]->setConstraint(""); 3988 ++NumMCOperands; 3989 break; 3990 case CVT_95_addBankedRegOperands: 3991 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3992 Operands[*(p + 1)]->setConstraint("m"); 3993 NumMCOperands += 1; 3994 break; 3995 case CVT_95_addMSRMaskOperands: 3996 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 3997 Operands[*(p + 1)]->setConstraint("m"); 3998 NumMCOperands += 1; 3999 break; 4000 case CVT_regR8: 4001 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4002 Operands[*(p + 1)]->setConstraint("m"); 4003 ++NumMCOperands; 4004 break; 4005 case CVT_regR0: 4006 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4007 Operands[*(p + 1)]->setConstraint("m"); 4008 ++NumMCOperands; 4009 break; 4010 case CVT_95_addPKHASRImmOperands: 4011 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4012 Operands[*(p + 1)]->setConstraint("m"); 4013 NumMCOperands += 1; 4014 break; 4015 case CVT_95_addImm1_95_32Operands: 4016 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4017 Operands[*(p + 1)]->setConstraint("m"); 4018 NumMCOperands += 1; 4019 break; 4020 case CVT_imm_95_4: 4021 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4022 Operands[*(p + 1)]->setConstraint(""); 4023 ++NumMCOperands; 4024 break; 4025 case CVT_imm_95_5: 4026 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4027 Operands[*(p + 1)]->setConstraint(""); 4028 ++NumMCOperands; 4029 break; 4030 case CVT_95_addShifterImmOperands: 4031 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4032 Operands[*(p + 1)]->setConstraint("m"); 4033 NumMCOperands += 1; 4034 break; 4035 case CVT_95_addImm1_95_16Operands: 4036 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4037 Operands[*(p + 1)]->setConstraint("m"); 4038 NumMCOperands += 1; 4039 break; 4040 case CVT_95_addRotImmOperands: 4041 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4042 Operands[*(p + 1)]->setConstraint("m"); 4043 NumMCOperands += 1; 4044 break; 4045 case CVT_95_addMemTBBOperands: 4046 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4047 Operands[*(p + 1)]->setConstraint("m"); 4048 NumMCOperands += 2; 4049 break; 4050 case CVT_95_addMemTBHOperands: 4051 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4052 Operands[*(p + 1)]->setConstraint("m"); 4053 NumMCOperands += 2; 4054 break; 4055 case CVT_95_addTraceSyncBarrierOptOperands: 4056 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4057 Operands[*(p + 1)]->setConstraint("m"); 4058 NumMCOperands += 1; 4059 break; 4060 case CVT_95_addNEONi16splatNotOperands: 4061 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4062 Operands[*(p + 1)]->setConstraint("m"); 4063 NumMCOperands += 1; 4064 break; 4065 case CVT_95_addNEONi32splatNotOperands: 4066 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4067 Operands[*(p + 1)]->setConstraint("m"); 4068 NumMCOperands += 1; 4069 break; 4070 case CVT_95_addNEONi16splatOperands: 4071 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4072 Operands[*(p + 1)]->setConstraint("m"); 4073 NumMCOperands += 1; 4074 break; 4075 case CVT_95_addNEONi32splatOperands: 4076 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4077 Operands[*(p + 1)]->setConstraint("m"); 4078 NumMCOperands += 1; 4079 break; 4080 case CVT_95_addComplexRotationOddOperands: 4081 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4082 Operands[*(p + 1)]->setConstraint("m"); 4083 NumMCOperands += 1; 4084 break; 4085 case CVT_95_addComplexRotationEvenOperands: 4086 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4087 Operands[*(p + 1)]->setConstraint("m"); 4088 NumMCOperands += 1; 4089 break; 4090 case CVT_95_addVectorIndex64Operands: 4091 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4092 Operands[*(p + 1)]->setConstraint("m"); 4093 NumMCOperands += 1; 4094 break; 4095 case CVT_95_addVectorIndex32Operands: 4096 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4097 Operands[*(p + 1)]->setConstraint("m"); 4098 NumMCOperands += 1; 4099 break; 4100 case CVT_95_addFBits16Operands: 4101 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4102 Operands[*(p + 1)]->setConstraint("m"); 4103 NumMCOperands += 1; 4104 break; 4105 case CVT_95_addFBits32Operands: 4106 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4107 Operands[*(p + 1)]->setConstraint("m"); 4108 NumMCOperands += 1; 4109 break; 4110 case CVT_95_addVectorIndex16Operands: 4111 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4112 Operands[*(p + 1)]->setConstraint("m"); 4113 NumMCOperands += 1; 4114 break; 4115 case CVT_95_addVectorIndex8Operands: 4116 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4117 Operands[*(p + 1)]->setConstraint("m"); 4118 NumMCOperands += 1; 4119 break; 4120 case CVT_95_addVecListOperands: 4121 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4122 Operands[*(p + 1)]->setConstraint("m"); 4123 NumMCOperands += 1; 4124 break; 4125 case CVT_95_addDupAlignedMemory16Operands: 4126 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4127 Operands[*(p + 1)]->setConstraint("m"); 4128 NumMCOperands += 2; 4129 break; 4130 case CVT_95_addAlignedMemory64or128Operands: 4131 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4132 Operands[*(p + 1)]->setConstraint("m"); 4133 NumMCOperands += 2; 4134 break; 4135 case CVT_95_addAlignedMemory64or128or256Operands: 4136 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4137 Operands[*(p + 1)]->setConstraint("m"); 4138 NumMCOperands += 2; 4139 break; 4140 case CVT_95_addAlignedMemory64Operands: 4141 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4142 Operands[*(p + 1)]->setConstraint("m"); 4143 NumMCOperands += 2; 4144 break; 4145 case CVT_95_addVecListIndexedOperands: 4146 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4147 Operands[*(p + 1)]->setConstraint("m"); 4148 NumMCOperands += 2; 4149 break; 4150 case CVT_95_addAlignedMemory16Operands: 4151 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4152 Operands[*(p + 1)]->setConstraint("m"); 4153 NumMCOperands += 2; 4154 break; 4155 case CVT_95_addDupAlignedMemory32Operands: 4156 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4157 Operands[*(p + 1)]->setConstraint("m"); 4158 NumMCOperands += 2; 4159 break; 4160 case CVT_95_addAlignedMemory32Operands: 4161 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4162 Operands[*(p + 1)]->setConstraint("m"); 4163 NumMCOperands += 2; 4164 break; 4165 case CVT_95_addDupAlignedMemoryNoneOperands: 4166 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4167 Operands[*(p + 1)]->setConstraint("m"); 4168 NumMCOperands += 2; 4169 break; 4170 case CVT_95_addAlignedMemoryNoneOperands: 4171 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4172 Operands[*(p + 1)]->setConstraint("m"); 4173 NumMCOperands += 2; 4174 break; 4175 case CVT_95_addAlignedMemoryOperands: 4176 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4177 Operands[*(p + 1)]->setConstraint("m"); 4178 NumMCOperands += 2; 4179 break; 4180 case CVT_95_addDupAlignedMemory64Operands: 4181 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4182 Operands[*(p + 1)]->setConstraint("m"); 4183 NumMCOperands += 2; 4184 break; 4185 case CVT_95_addDupAlignedMemory64or128Operands: 4186 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4187 Operands[*(p + 1)]->setConstraint("m"); 4188 NumMCOperands += 2; 4189 break; 4190 case CVT_95_addSPRRegListOperands: 4191 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4192 Operands[*(p + 1)]->setConstraint("m"); 4193 NumMCOperands += 1; 4194 break; 4195 case CVT_95_addAddrMode5FP16Operands: 4196 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4197 Operands[*(p + 1)]->setConstraint("m"); 4198 NumMCOperands += 2; 4199 break; 4200 case CVT_95_addNEONi32vmovOperands: 4201 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4202 Operands[*(p + 1)]->setConstraint("m"); 4203 NumMCOperands += 1; 4204 break; 4205 case CVT_95_addNEONvmovi8ReplicateOperands: 4206 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4207 Operands[*(p + 1)]->setConstraint("m"); 4208 NumMCOperands += 1; 4209 break; 4210 case CVT_95_addNEONvmovi16ReplicateOperands: 4211 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4212 Operands[*(p + 1)]->setConstraint("m"); 4213 NumMCOperands += 1; 4214 break; 4215 case CVT_95_addNEONi32vmovNegOperands: 4216 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4217 Operands[*(p + 1)]->setConstraint("m"); 4218 NumMCOperands += 1; 4219 break; 4220 case CVT_95_addNEONvmovi32ReplicateOperands: 4221 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4222 Operands[*(p + 1)]->setConstraint("m"); 4223 NumMCOperands += 1; 4224 break; 4225 case CVT_95_addNEONi64splatOperands: 4226 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4227 Operands[*(p + 1)]->setConstraint("m"); 4228 NumMCOperands += 1; 4229 break; 4230 case CVT_95_addNEONi8splatOperands: 4231 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4232 Operands[*(p + 1)]->setConstraint("m"); 4233 NumMCOperands += 1; 4234 break; 4235 case CVT_95_addNEONinvi8ReplicateOperands: 4236 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4237 Operands[*(p + 1)]->setConstraint("m"); 4238 NumMCOperands += 1; 4239 break; 4240 case CVT_imm_95_2: 4241 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4242 Operands[*(p + 1)]->setConstraint(""); 4243 ++NumMCOperands; 4244 break; 4245 case CVT_imm_95_3: 4246 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 4247 Operands[*(p + 1)]->setConstraint(""); 4248 ++NumMCOperands; 4249 break; 4250 } 4251 } 4252} 4253 4254namespace { 4255 4256/// MatchClassKind - The kinds of classes which participate in 4257/// instruction matching. 4258enum MatchClassKind { 4259 InvalidMatchClass = 0, 4260 OptionalMatchClass = 1, 4261 MCK__DOT_d, // '.d' 4262 MCK__DOT_f, // '.f' 4263 MCK__DOT_s16, // '.s16' 4264 MCK__DOT_s32, // '.s32' 4265 MCK__DOT_s64, // '.s64' 4266 MCK__DOT_s8, // '.s8' 4267 MCK__DOT_u16, // '.u16' 4268 MCK__DOT_u32, // '.u32' 4269 MCK__DOT_u64, // '.u64' 4270 MCK__DOT_u8, // '.u8' 4271 MCK__DOT_f32, // '.f32' 4272 MCK__DOT_f64, // '.f64' 4273 MCK__DOT_i16, // '.i16' 4274 MCK__DOT_i32, // '.i32' 4275 MCK__DOT_i64, // '.i64' 4276 MCK__DOT_i8, // '.i8' 4277 MCK__DOT_p16, // '.p16' 4278 MCK__DOT_p8, // '.p8' 4279 MCK__EXCLAIM_, // '!' 4280 MCK__35_0, // '#0' 4281 MCK__DOT_16, // '.16' 4282 MCK__DOT_32, // '.32' 4283 MCK__DOT_64, // '.64' 4284 MCK__DOT_8, // '.8' 4285 MCK__DOT_f16, // '.f16' 4286 MCK__DOT_p64, // '.p64' 4287 MCK__DOT_w, // '.w' 4288 MCK__91_, // '[' 4289 MCK__93_, // ']' 4290 MCK__94_, // '^' 4291 MCK__123_, // '{' 4292 MCK__125_, // '}' 4293 MCK_LAST_TOKEN = MCK__125_, 4294 MCK_Reg11, // derived register class 4295 MCK_Reg59, // derived register class 4296 MCK_Reg75, // derived register class 4297 MCK_APSR, // register class 'APSR' 4298 MCK_APSR_NZCV, // register class 'APSR_NZCV' 4299 MCK_CCR, // register class 'CCR,CPSR' 4300 MCK_FPEXC, // register class 'FPEXC' 4301 MCK_FPINST, // register class 'FPINST' 4302 MCK_FPINST2, // register class 'FPINST2' 4303 MCK_FPSCR, // register class 'FPSCR' 4304 MCK_FPSID, // register class 'FPSID' 4305 MCK_GPRsp, // register class 'GPRsp,SP' 4306 MCK_LR, // register class 'LR' 4307 MCK_MVFR0, // register class 'MVFR0' 4308 MCK_MVFR1, // register class 'MVFR1' 4309 MCK_MVFR2, // register class 'MVFR2' 4310 MCK_PC, // register class 'PC' 4311 MCK_SPSR, // register class 'SPSR' 4312 MCK_Reg60, // derived register class 4313 MCK_Reg68, // derived register class 4314 MCK_Reg73, // derived register class 4315 MCK_Reg100, // derived register class 4316 MCK_Reg45, // derived register class 4317 MCK_Reg61, // derived register class 4318 MCK_Reg72, // derived register class 4319 MCK_Reg74, // derived register class 4320 MCK_Reg83, // derived register class 4321 MCK_Reg88, // derived register class 4322 MCK_Reg101, // derived register class 4323 MCK_Reg0, // derived register class 4324 MCK_Reg46, // derived register class 4325 MCK_Reg62, // derived register class 4326 MCK_Reg69, // derived register class 4327 MCK_Reg84, // derived register class 4328 MCK_Reg89, // derived register class 4329 MCK_Reg93, // derived register class 4330 MCK_Reg102, // derived register class 4331 MCK_QPR_8, // register class 'QPR_8' 4332 MCK_Reg57, // derived register class 4333 MCK_Reg63, // derived register class 4334 MCK_tcGPR, // register class 'tcGPR' 4335 MCK_Reg10, // derived register class 4336 MCK_Reg40, // derived register class 4337 MCK_Reg58, // derived register class 4338 MCK_Reg64, // derived register class 4339 MCK_Reg70, // derived register class 4340 MCK_Reg76, // derived register class 4341 MCK_Reg94, // derived register class 4342 MCK_Reg103, // derived register class 4343 MCK_Reg8, // derived register class 4344 MCK_Reg26, // derived register class 4345 MCK_Reg47, // derived register class 4346 MCK_Reg55, // derived register class 4347 MCK_Reg65, // derived register class 4348 MCK_Reg77, // derived register class 4349 MCK_Reg85, // derived register class 4350 MCK_Reg90, // derived register class 4351 MCK_Reg104, // derived register class 4352 MCK_GPRPair, // register class 'GPRPair' 4353 MCK_Reg27, // derived register class 4354 MCK_Reg41, // derived register class 4355 MCK_Reg48, // derived register class 4356 MCK_Reg56, // derived register class 4357 MCK_Reg66, // derived register class 4358 MCK_Reg78, // derived register class 4359 MCK_Reg86, // derived register class 4360 MCK_Reg91, // derived register class 4361 MCK_Reg95, // derived register class 4362 MCK_Reg105, // derived register class 4363 MCK_DPR_8, // register class 'DPR_8' 4364 MCK_QPR_VFP2, // register class 'QPR_VFP2' 4365 MCK_hGPR, // register class 'hGPR' 4366 MCK_tGPR, // register class 'tGPR' 4367 MCK_tGPRwithpc, // register class 'tGPRwithpc' 4368 MCK_Reg96, // derived register class 4369 MCK_Reg53, // derived register class 4370 MCK_QQQQPR, // register class 'QQQQPR' 4371 MCK_Reg42, // derived register class 4372 MCK_Reg54, // derived register class 4373 MCK_Reg79, // derived register class 4374 MCK_Reg97, // derived register class 4375 MCK_Reg106, // derived register class 4376 MCK_rGPR, // register class 'rGPR' 4377 MCK_Reg24, // derived register class 4378 MCK_Reg51, // derived register class 4379 MCK_Reg80, // derived register class 4380 MCK_Reg87, // derived register class 4381 MCK_Reg92, // derived register class 4382 MCK_GPRnopc, // register class 'GPRnopc' 4383 MCK_QQPR, // register class 'QQPR' 4384 MCK_Reg25, // derived register class 4385 MCK_Reg43, // derived register class 4386 MCK_Reg52, // derived register class 4387 MCK_Reg81, // derived register class 4388 MCK_Reg98, // derived register class 4389 MCK_DPR_VFP2, // register class 'DPR_VFP2' 4390 MCK_GPR, // register class 'GPR' 4391 MCK_GPRwithAPSR, // register class 'GPRwithAPSR' 4392 MCK_QPR, // register class 'QPR' 4393 MCK_SPR_8, // register class 'SPR_8' 4394 MCK_DTripleSpc, // register class 'DTripleSpc,DQuadSpc' 4395 MCK_DQuad, // register class 'DQuad' 4396 MCK_DPairSpc, // register class 'DPairSpc' 4397 MCK_DTriple, // register class 'DTriple' 4398 MCK_DPair, // register class 'DPair' 4399 MCK_DPR, // register class 'DPR' 4400 MCK_HPR, // register class 'HPR,SPR' 4401 MCK_LAST_REGISTER = MCK_HPR, 4402 MCK_AM2OffsetImm, // user defined class 'AM2OffsetImmAsmOperand' 4403 MCK_AM3Offset, // user defined class 'AM3OffsetAsmOperand' 4404 MCK_ARMBranchTarget, // user defined class 'ARMBranchTarget' 4405 MCK_AddrMode3, // user defined class 'AddrMode3AsmOperand' 4406 MCK_AddrMode5, // user defined class 'AddrMode5AsmOperand' 4407 MCK_AddrMode5FP16, // user defined class 'AddrMode5FP16AsmOperand' 4408 MCK_AlignedMemory16, // user defined class 'AddrMode6Align16AsmOperand' 4409 MCK_AlignedMemory32, // user defined class 'AddrMode6Align32AsmOperand' 4410 MCK_AlignedMemory64, // user defined class 'AddrMode6Align64AsmOperand' 4411 MCK_AlignedMemory64or128, // user defined class 'AddrMode6Align64or128AsmOperand' 4412 MCK_AlignedMemory64or128or256, // user defined class 'AddrMode6Align64or128or256AsmOperand' 4413 MCK_AlignedMemoryNone, // user defined class 'AddrMode6AlignNoneAsmOperand' 4414 MCK_AlignedMemory, // user defined class 'AddrMode6AsmOperand' 4415 MCK_DupAlignedMemory16, // user defined class 'AddrMode6dupAlign16AsmOperand' 4416 MCK_DupAlignedMemory32, // user defined class 'AddrMode6dupAlign32AsmOperand' 4417 MCK_DupAlignedMemory64, // user defined class 'AddrMode6dupAlign64AsmOperand' 4418 MCK_DupAlignedMemory64or128, // user defined class 'AddrMode6dupAlign64or128AsmOperand' 4419 MCK_DupAlignedMemoryNone, // user defined class 'AddrMode6dupAlignNoneAsmOperand' 4420 MCK_AdrLabel, // user defined class 'AdrLabelAsmOperand' 4421 MCK_BankedReg, // user defined class 'BankedRegOperand' 4422 MCK_Bitfield, // user defined class 'BitfieldAsmOperand' 4423 MCK_CCOut, // user defined class 'CCOutOperand' 4424 MCK_CondCode, // user defined class 'CondCodeOperand' 4425 MCK_CoprocNum, // user defined class 'CoprocNumAsmOperand' 4426 MCK_CoprocOption, // user defined class 'CoprocOptionAsmOperand' 4427 MCK_CoprocReg, // user defined class 'CoprocRegAsmOperand' 4428 MCK_DPRRegList, // user defined class 'DPRRegListAsmOperand' 4429 MCK_FPImm, // user defined class 'FPImmOperand' 4430 MCK_Imm0_15, // user defined class 'Imm0_15AsmOperand' 4431 MCK_Imm0_1, // user defined class 'Imm0_1AsmOperand' 4432 MCK_Imm0_239, // user defined class 'Imm0_239AsmOperand' 4433 MCK_Imm0_255, // user defined class 'Imm0_255AsmOperand' 4434 MCK_Imm0_31, // user defined class 'Imm0_31AsmOperand' 4435 MCK_Imm0_32, // user defined class 'Imm0_32AsmOperand' 4436 MCK_Imm0_3, // user defined class 'Imm0_3AsmOperand' 4437 MCK_Imm0_63, // user defined class 'Imm0_63AsmOperand' 4438 MCK_Imm0_65535, // user defined class 'Imm0_65535AsmOperand' 4439 MCK_Imm0_65535Expr, // user defined class 'Imm0_65535ExprAsmOperand' 4440 MCK_Imm0_7, // user defined class 'Imm0_7AsmOperand' 4441 MCK_Imm16, // user defined class 'Imm16AsmOperand' 4442 MCK_Imm1_15, // user defined class 'Imm1_15AsmOperand' 4443 MCK_Imm1_16, // user defined class 'Imm1_16AsmOperand' 4444 MCK_Imm1_31, // user defined class 'Imm1_31AsmOperand' 4445 MCK_Imm1_32, // user defined class 'Imm1_32AsmOperand' 4446 MCK_Imm1_7, // user defined class 'Imm1_7AsmOperand' 4447 MCK_Imm24bit, // user defined class 'Imm24bitAsmOperand' 4448 MCK_Imm256_65535Expr, // user defined class 'Imm256_65535ExprAsmOperand' 4449 MCK_Imm32, // user defined class 'Imm32AsmOperand' 4450 MCK_Imm8, // user defined class 'Imm8AsmOperand' 4451 MCK_Imm8_255, // user defined class 'Imm8_255AsmOperand' 4452 MCK_Imm, // user defined class 'ImmAsmOperand' 4453 MCK_InstSyncBarrierOpt, // user defined class 'InstSyncBarrierOptOperand' 4454 MCK_MSRMask, // user defined class 'MSRMaskOperand' 4455 MCK_MemBarrierOpt, // user defined class 'MemBarrierOptOperand' 4456 MCK_MemImm0_1020s4Offset, // user defined class 'MemImm0_1020s4OffsetAsmOperand' 4457 MCK_MemImm12Offset, // user defined class 'MemImm12OffsetAsmOperand' 4458 MCK_MemImm8Offset, // user defined class 'MemImm8OffsetAsmOperand' 4459 MCK_MemImm8s4Offset, // user defined class 'MemImm8s4OffsetAsmOperand' 4460 MCK_MemNegImm8Offset, // user defined class 'MemNegImm8OffsetAsmOperand' 4461 MCK_MemNoOffset, // user defined class 'MemNoOffsetAsmOperand' 4462 MCK_MemPosImm8Offset, // user defined class 'MemPosImm8OffsetAsmOperand' 4463 MCK_MemRegOffset, // user defined class 'MemRegOffsetAsmOperand' 4464 MCK_ModImm, // user defined class 'ModImmAsmOperand' 4465 MCK_ModImmNeg, // user defined class 'ModImmNegAsmOperand' 4466 MCK_ModImmNot, // user defined class 'ModImmNotAsmOperand' 4467 MCK_PKHASRImm, // user defined class 'PKHASRAsmOperand' 4468 MCK_PKHLSLImm, // user defined class 'PKHLSLAsmOperand' 4469 MCK_PostIdxImm8, // user defined class 'PostIdxImm8AsmOperand' 4470 MCK_PostIdxImm8s4, // user defined class 'PostIdxImm8s4AsmOperand' 4471 MCK_PostIdxReg, // user defined class 'PostIdxRegAsmOperand' 4472 MCK_PostIdxRegShifted, // user defined class 'PostIdxRegShiftedAsmOperand' 4473 MCK_ProcIFlags, // user defined class 'ProcIFlagsOperand' 4474 MCK_RegList, // user defined class 'RegListAsmOperand' 4475 MCK_RotImm, // user defined class 'RotImmAsmOperand' 4476 MCK_SPRRegList, // user defined class 'SPRRegListAsmOperand' 4477 MCK_SetEndImm, // user defined class 'SetEndAsmOperand' 4478 MCK_RegShiftedImm, // user defined class 'ShiftedImmAsmOperand' 4479 MCK_RegShiftedReg, // user defined class 'ShiftedRegAsmOperand' 4480 MCK_ShifterImm, // user defined class 'ShifterImmAsmOperand' 4481 MCK_ThumbBranchTarget, // user defined class 'ThumbBranchTarget' 4482 MCK_ThumbMemPC, // user defined class 'ThumbMemPC' 4483 MCK_ThumbModImmNeg1_7, // user defined class 'ThumbModImmNeg1_7AsmOperand' 4484 MCK_ThumbModImmNeg8_255, // user defined class 'ThumbModImmNeg8_255AsmOperand' 4485 MCK_ImmThumbSR, // user defined class 'ThumbSRImmAsmOperand' 4486 MCK_TraceSyncBarrierOpt, // user defined class 'TraceSyncBarrierOptOperand' 4487 MCK_UnsignedOffset_b8s2, // user defined class 'UnsignedOffset_b8s2' 4488 MCK_VecListDPairAllLanes, // user defined class 'VecListDPairAllLanesAsmOperand' 4489 MCK_VecListDPair, // user defined class 'VecListDPairAsmOperand' 4490 MCK_VecListDPairSpacedAllLanes, // user defined class 'VecListDPairSpacedAllLanesAsmOperand' 4491 MCK_VecListDPairSpaced, // user defined class 'VecListDPairSpacedAsmOperand' 4492 MCK_VecListFourDAllLanes, // user defined class 'VecListFourDAllLanesAsmOperand' 4493 MCK_VecListFourD, // user defined class 'VecListFourDAsmOperand' 4494 MCK_VecListFourDByteIndexed, // user defined class 'VecListFourDByteIndexAsmOperand' 4495 MCK_VecListFourDHWordIndexed, // user defined class 'VecListFourDHWordIndexAsmOperand' 4496 MCK_VecListFourDWordIndexed, // user defined class 'VecListFourDWordIndexAsmOperand' 4497 MCK_VecListFourQAllLanes, // user defined class 'VecListFourQAllLanesAsmOperand' 4498 MCK_VecListFourQ, // user defined class 'VecListFourQAsmOperand' 4499 MCK_VecListFourQHWordIndexed, // user defined class 'VecListFourQHWordIndexAsmOperand' 4500 MCK_VecListFourQWordIndexed, // user defined class 'VecListFourQWordIndexAsmOperand' 4501 MCK_VecListOneDAllLanes, // user defined class 'VecListOneDAllLanesAsmOperand' 4502 MCK_VecListOneD, // user defined class 'VecListOneDAsmOperand' 4503 MCK_VecListOneDByteIndexed, // user defined class 'VecListOneDByteIndexAsmOperand' 4504 MCK_VecListOneDHWordIndexed, // user defined class 'VecListOneDHWordIndexAsmOperand' 4505 MCK_VecListOneDWordIndexed, // user defined class 'VecListOneDWordIndexAsmOperand' 4506 MCK_VecListThreeDAllLanes, // user defined class 'VecListThreeDAllLanesAsmOperand' 4507 MCK_VecListThreeD, // user defined class 'VecListThreeDAsmOperand' 4508 MCK_VecListThreeDByteIndexed, // user defined class 'VecListThreeDByteIndexAsmOperand' 4509 MCK_VecListThreeDHWordIndexed, // user defined class 'VecListThreeDHWordIndexAsmOperand' 4510 MCK_VecListThreeDWordIndexed, // user defined class 'VecListThreeDWordIndexAsmOperand' 4511 MCK_VecListThreeQAllLanes, // user defined class 'VecListThreeQAllLanesAsmOperand' 4512 MCK_VecListThreeQ, // user defined class 'VecListThreeQAsmOperand' 4513 MCK_VecListThreeQHWordIndexed, // user defined class 'VecListThreeQHWordIndexAsmOperand' 4514 MCK_VecListThreeQWordIndexed, // user defined class 'VecListThreeQWordIndexAsmOperand' 4515 MCK_VecListTwoDByteIndexed, // user defined class 'VecListTwoDByteIndexAsmOperand' 4516 MCK_VecListTwoDHWordIndexed, // user defined class 'VecListTwoDHWordIndexAsmOperand' 4517 MCK_VecListTwoDWordIndexed, // user defined class 'VecListTwoDWordIndexAsmOperand' 4518 MCK_VecListTwoQHWordIndexed, // user defined class 'VecListTwoQHWordIndexAsmOperand' 4519 MCK_VecListTwoQWordIndexed, // user defined class 'VecListTwoQWordIndexAsmOperand' 4520 MCK_VectorIndex16, // user defined class 'VectorIndex16Operand' 4521 MCK_VectorIndex32, // user defined class 'VectorIndex32Operand' 4522 MCK_VectorIndex64, // user defined class 'VectorIndex64Operand' 4523 MCK_VectorIndex8, // user defined class 'VectorIndex8Operand' 4524 MCK_MemTBB, // user defined class 'addrmode_tbb_asmoperand' 4525 MCK_MemTBH, // user defined class 'addrmode_tbh_asmoperand' 4526 MCK_ComplexRotationEven, // user defined class 'anonymous_3111' 4527 MCK_ComplexRotationOdd, // user defined class 'anonymous_3112' 4528 MCK_NEONi16vmovi8Replicate, // user defined class 'anonymous_4141' 4529 MCK_NEONi16invi8Replicate, // user defined class 'anonymous_4143' 4530 MCK_NEONi32vmovi8Replicate, // user defined class 'anonymous_4146' 4531 MCK_NEONi32invi8Replicate, // user defined class 'anonymous_4148' 4532 MCK_NEONi64vmovi8Replicate, // user defined class 'anonymous_4155' 4533 MCK_NEONi64invi8Replicate, // user defined class 'anonymous_4157' 4534 MCK_NEONi32vmovi16Replicate, // user defined class 'anonymous_4168' 4535 MCK_NEONi64vmovi16Replicate, // user defined class 'anonymous_4171' 4536 MCK_NEONi64vmovi32Replicate, // user defined class 'anonymous_4178' 4537 MCK_ConstPoolAsmImm, // user defined class 'const_pool_asm_operand' 4538 MCK_FBits16, // user defined class 'fbits16_asm_operand' 4539 MCK_FBits32, // user defined class 'fbits32_asm_operand' 4540 MCK_Imm0_4095, // user defined class 'imm0_4095_asmoperand' 4541 MCK_Imm0_4095Neg, // user defined class 'imm0_4095_neg_asmoperand' 4542 MCK_ITMask, // user defined class 'it_mask_asmoperand' 4543 MCK_ITCondCode, // user defined class 'it_pred_asmoperand' 4544 MCK_NEONi16splat, // user defined class 'nImmSplatI16AsmOperand' 4545 MCK_NEONi32splat, // user defined class 'nImmSplatI32AsmOperand' 4546 MCK_NEONi64splat, // user defined class 'nImmSplatI64AsmOperand' 4547 MCK_NEONi8splat, // user defined class 'nImmSplatI8AsmOperand' 4548 MCK_NEONi16splatNot, // user defined class 'nImmSplatNotI16AsmOperand' 4549 MCK_NEONi32splatNot, // user defined class 'nImmSplatNotI32AsmOperand' 4550 MCK_NEONi32vmov, // user defined class 'nImmVMOVI32AsmOperand' 4551 MCK_NEONi32vmovNeg, // user defined class 'nImmVMOVI32NegAsmOperand' 4552 MCK_ShrImm16, // user defined class 'shr_imm16_asm_operand' 4553 MCK_ShrImm32, // user defined class 'shr_imm32_asm_operand' 4554 MCK_ShrImm64, // user defined class 'shr_imm64_asm_operand' 4555 MCK_ShrImm8, // user defined class 'shr_imm8_asm_operand' 4556 MCK_T2SOImm, // user defined class 't2_so_imm_asmoperand' 4557 MCK_T2SOImmNeg, // user defined class 't2_so_imm_neg_asmoperand' 4558 MCK_T2SOImmNot, // user defined class 't2_so_imm_not_asmoperand' 4559 MCK_MemUImm12Offset, // user defined class 't2addrmode_imm12_asmoperand' 4560 MCK_T2MemRegOffset, // user defined class 't2addrmode_so_reg_asmoperand' 4561 MCK_Imm8s4, // user defined class 't2am_imm8s4_offset_asmoperand' 4562 MCK_MemPCRelImm12, // user defined class 't2ldr_pcrel_imm12_asmoperand' 4563 MCK_MemThumbRIs1, // user defined class 't_addrmode_is1_asm_operand' 4564 MCK_MemThumbRIs2, // user defined class 't_addrmode_is2_asm_operand' 4565 MCK_MemThumbRIs4, // user defined class 't_addrmode_is4_asm_operand' 4566 MCK_MemThumbRR, // user defined class 't_addrmode_rr_asm_operand' 4567 MCK_MemThumbSPI, // user defined class 't_addrmode_sp_asm_operand' 4568 MCK_Imm0_1020s4, // user defined class 't_imm0_1020s4_asmoperand' 4569 MCK_Imm0_508s4, // user defined class 't_imm0_508s4_asmoperand' 4570 MCK_Imm0_508s4Neg, // user defined class 't_imm0_508s4_neg_asmoperand' 4571 NumMatchClassKinds 4572}; 4573 4574} 4575 4576static const char *getMatchKindDiag(ARMAsmParser::ARMMatchResultTy MatchResult) { 4577 switch (MatchResult) { 4578 case ARMAsmParser::Match_GPRsp: 4579 return "operand must be a register sp"; 4580 case ARMAsmParser::Match_QPR_8: 4581 return "operand must be a register in range [q0, q3]"; 4582 case ARMAsmParser::Match_DPR_8: 4583 return "operand must be a register in range [d0, d7]"; 4584 case ARMAsmParser::Match_QPR_VFP2: 4585 return "operand must be a register in range [q0, q7]"; 4586 case ARMAsmParser::Match_hGPR: 4587 return "operand must be a register in range [r8, r15]"; 4588 case ARMAsmParser::Match_tGPR: 4589 return "operand must be a register in range [r0, r7]"; 4590 case ARMAsmParser::Match_GPRnopc: 4591 return "operand must be a register in range [r0, r14]"; 4592 case ARMAsmParser::Match_DPR_VFP2: 4593 return "operand must be a register in range [d0, d15]"; 4594 case ARMAsmParser::Match_GPR: 4595 return "operand must be a register in range [r0, r15]"; 4596 case ARMAsmParser::Match_GPRwithAPSR: 4597 return "operand must be a register in range [r0, r14] or apsr_nzcv"; 4598 case ARMAsmParser::Match_QPR: 4599 return "operand must be a register in range [q0, q15]"; 4600 case ARMAsmParser::Match_SPR_8: 4601 return "operand must be a register in range [s0, s15]"; 4602 case ARMAsmParser::Match_SPR: 4603 return "operand must be a register in range [s0, s31]"; 4604 case ARMAsmParser::Match_AlignedMemory16: 4605 return "alignment must be 16 or omitted"; 4606 case ARMAsmParser::Match_AlignedMemory32: 4607 return "alignment must be 32 or omitted"; 4608 case ARMAsmParser::Match_AlignedMemory64: 4609 return "alignment must be 64 or omitted"; 4610 case ARMAsmParser::Match_AlignedMemory64or128: 4611 return "alignment must be 64, 128 or omitted"; 4612 case ARMAsmParser::Match_AlignedMemory64or128or256: 4613 return "alignment must be 64, 128, 256 or omitted"; 4614 case ARMAsmParser::Match_AlignedMemoryNone: 4615 return "alignment must be omitted"; 4616 case ARMAsmParser::Match_DupAlignedMemory16: 4617 return "alignment must be 16 or omitted"; 4618 case ARMAsmParser::Match_DupAlignedMemory32: 4619 return "alignment must be 32 or omitted"; 4620 case ARMAsmParser::Match_DupAlignedMemory64: 4621 return "alignment must be 64 or omitted"; 4622 case ARMAsmParser::Match_DupAlignedMemory64or128: 4623 return "alignment must be 64, 128 or omitted"; 4624 case ARMAsmParser::Match_DupAlignedMemoryNone: 4625 return "alignment must be omitted"; 4626 case ARMAsmParser::Match_Imm0_15: 4627 return "operand must be an immediate in the range [0,15]"; 4628 case ARMAsmParser::Match_Imm0_1: 4629 return "operand must be an immediate in the range [0,1]"; 4630 case ARMAsmParser::Match_Imm0_239: 4631 return "operand must be an immediate in the range [0,239]"; 4632 case ARMAsmParser::Match_Imm0_255: 4633 return "operand must be an immediate in the range [0,255]"; 4634 case ARMAsmParser::Match_Imm0_31: 4635 return "operand must be an immediate in the range [0,31]"; 4636 case ARMAsmParser::Match_Imm0_32: 4637 return "operand must be an immediate in the range [0,32]"; 4638 case ARMAsmParser::Match_Imm0_3: 4639 return "operand must be an immediate in the range [0,3]"; 4640 case ARMAsmParser::Match_Imm0_63: 4641 return "operand must be an immediate in the range [0,63]"; 4642 case ARMAsmParser::Match_Imm0_65535: 4643 return "operand must be an immediate in the range [0,65535]"; 4644 case ARMAsmParser::Match_Imm0_65535Expr: 4645 return "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 4646 case ARMAsmParser::Match_Imm0_7: 4647 return "operand must be an immediate in the range [0,7]"; 4648 case ARMAsmParser::Match_Imm16: 4649 return "operand must be an immediate in the range [16,16]"; 4650 case ARMAsmParser::Match_Imm1_15: 4651 return "operand must be an immediate in the range [1,15]"; 4652 case ARMAsmParser::Match_ImmRange1_16: 4653 return "operand must be an immediate in the range [1,16]"; 4654 case ARMAsmParser::Match_Imm1_31: 4655 return "operand must be an immediate in the range [1,31]"; 4656 case ARMAsmParser::Match_ImmRange1_32: 4657 return "operand must be an immediate in the range [1,32]"; 4658 case ARMAsmParser::Match_Imm1_7: 4659 return "operand must be an immediate in the range [1,7]"; 4660 case ARMAsmParser::Match_Imm24bit: 4661 return "operand must be an immediate in the range [0,0xffffff]"; 4662 case ARMAsmParser::Match_Imm256_65535Expr: 4663 return "operand must be an immediate in the range [256,65535]"; 4664 case ARMAsmParser::Match_Imm32: 4665 return "operand must be an immediate in the range [32,32]"; 4666 case ARMAsmParser::Match_Imm8: 4667 return "operand must be an immediate in the range [8,8]"; 4668 case ARMAsmParser::Match_Imm8_255: 4669 return "operand must be an immediate in the range [8,255]"; 4670 case ARMAsmParser::Match_PKHLSLImm: 4671 return "operand must be an immediate in the range [0,31]"; 4672 case ARMAsmParser::Match_SPRRegList: 4673 return "operand must be a list of registers in range [s0, s31]"; 4674 case ARMAsmParser::Match_SetEndImm: 4675 return "operand must be an immediate in the range [0,1]"; 4676 case ARMAsmParser::Match_ImmThumbSR: 4677 return "operand must be an immediate in the range [1,32]"; 4678 case ARMAsmParser::Match_ComplexRotationEven: 4679 return "complex rotation must be 0, 90, 180 or 270"; 4680 case ARMAsmParser::Match_ComplexRotationOdd: 4681 return "complex rotation must be 90 or 270"; 4682 case ARMAsmParser::Match_Imm0_4095: 4683 return "operand must be an immediate in the range [0,4095]"; 4684 case ARMAsmParser::Match_ShrImm16: 4685 return "operand must be an immediate in the range [1,16]"; 4686 case ARMAsmParser::Match_ShrImm32: 4687 return "operand must be an immediate in the range [1,32]"; 4688 case ARMAsmParser::Match_ShrImm64: 4689 return "operand must be an immediate in the range [1,64]"; 4690 case ARMAsmParser::Match_ShrImm8: 4691 return "operand must be an immediate in the range [1,8]"; 4692 default: 4693 return nullptr; 4694 } 4695} 4696 4697static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { 4698 switch (RegisterClass) { 4699 case MCK_GPRsp: 4700 return ARMAsmParser::Match_GPRsp; 4701 case MCK_QPR_8: 4702 return ARMAsmParser::Match_QPR_8; 4703 case MCK_DPR_8: 4704 return ARMAsmParser::Match_DPR_8; 4705 case MCK_QPR_VFP2: 4706 return ARMAsmParser::Match_QPR_VFP2; 4707 case MCK_hGPR: 4708 return ARMAsmParser::Match_hGPR; 4709 case MCK_tGPR: 4710 return ARMAsmParser::Match_tGPR; 4711 case MCK_rGPR: 4712 return ARMAsmParser::Match_rGPR; 4713 case MCK_GPRnopc: 4714 return ARMAsmParser::Match_GPRnopc; 4715 case MCK_DPR_VFP2: 4716 return ARMAsmParser::Match_DPR_VFP2; 4717 case MCK_GPR: 4718 return ARMAsmParser::Match_GPR; 4719 case MCK_GPRwithAPSR: 4720 return ARMAsmParser::Match_GPRwithAPSR; 4721 case MCK_QPR: 4722 return ARMAsmParser::Match_QPR; 4723 case MCK_SPR_8: 4724 return ARMAsmParser::Match_SPR_8; 4725 case MCK_DPR: 4726 return ARMAsmParser::Match_DPR; 4727 case MCK_HPR: 4728 return ARMAsmParser::Match_SPR; 4729 default: 4730 return MCTargetAsmParser::Match_InvalidOperand; 4731 } 4732} 4733 4734static MatchClassKind matchTokenString(StringRef Name) { 4735 switch (Name.size()) { 4736 default: break; 4737 case 1: // 6 strings to match. 4738 switch (Name[0]) { 4739 default: break; 4740 case '!': // 1 string to match. 4741 return MCK__EXCLAIM_; // "!" 4742 case '[': // 1 string to match. 4743 return MCK__91_; // "[" 4744 case ']': // 1 string to match. 4745 return MCK__93_; // "]" 4746 case '^': // 1 string to match. 4747 return MCK__94_; // "^" 4748 case '{': // 1 string to match. 4749 return MCK__123_; // "{" 4750 case '}': // 1 string to match. 4751 return MCK__125_; // "}" 4752 } 4753 break; 4754 case 2: // 5 strings to match. 4755 switch (Name[0]) { 4756 default: break; 4757 case '#': // 1 string to match. 4758 if (Name[1] != '0') 4759 break; 4760 return MCK__35_0; // "#0" 4761 case '.': // 4 strings to match. 4762 switch (Name[1]) { 4763 default: break; 4764 case '8': // 1 string to match. 4765 return MCK__DOT_8; // ".8" 4766 case 'd': // 1 string to match. 4767 return MCK__DOT_d; // ".d" 4768 case 'f': // 1 string to match. 4769 return MCK__DOT_f; // ".f" 4770 case 'w': // 1 string to match. 4771 return MCK__DOT_w; // ".w" 4772 } 4773 break; 4774 } 4775 break; 4776 case 3: // 7 strings to match. 4777 if (Name[0] != '.') 4778 break; 4779 switch (Name[1]) { 4780 default: break; 4781 case '1': // 1 string to match. 4782 if (Name[2] != '6') 4783 break; 4784 return MCK__DOT_16; // ".16" 4785 case '3': // 1 string to match. 4786 if (Name[2] != '2') 4787 break; 4788 return MCK__DOT_32; // ".32" 4789 case '6': // 1 string to match. 4790 if (Name[2] != '4') 4791 break; 4792 return MCK__DOT_64; // ".64" 4793 case 'i': // 1 string to match. 4794 if (Name[2] != '8') 4795 break; 4796 return MCK__DOT_i8; // ".i8" 4797 case 'p': // 1 string to match. 4798 if (Name[2] != '8') 4799 break; 4800 return MCK__DOT_p8; // ".p8" 4801 case 's': // 1 string to match. 4802 if (Name[2] != '8') 4803 break; 4804 return MCK__DOT_s8; // ".s8" 4805 case 'u': // 1 string to match. 4806 if (Name[2] != '8') 4807 break; 4808 return MCK__DOT_u8; // ".u8" 4809 } 4810 break; 4811 case 4: // 14 strings to match. 4812 if (Name[0] != '.') 4813 break; 4814 switch (Name[1]) { 4815 default: break; 4816 case 'f': // 3 strings to match. 4817 switch (Name[2]) { 4818 default: break; 4819 case '1': // 1 string to match. 4820 if (Name[3] != '6') 4821 break; 4822 return MCK__DOT_f16; // ".f16" 4823 case '3': // 1 string to match. 4824 if (Name[3] != '2') 4825 break; 4826 return MCK__DOT_f32; // ".f32" 4827 case '6': // 1 string to match. 4828 if (Name[3] != '4') 4829 break; 4830 return MCK__DOT_f64; // ".f64" 4831 } 4832 break; 4833 case 'i': // 3 strings to match. 4834 switch (Name[2]) { 4835 default: break; 4836 case '1': // 1 string to match. 4837 if (Name[3] != '6') 4838 break; 4839 return MCK__DOT_i16; // ".i16" 4840 case '3': // 1 string to match. 4841 if (Name[3] != '2') 4842 break; 4843 return MCK__DOT_i32; // ".i32" 4844 case '6': // 1 string to match. 4845 if (Name[3] != '4') 4846 break; 4847 return MCK__DOT_i64; // ".i64" 4848 } 4849 break; 4850 case 'p': // 2 strings to match. 4851 switch (Name[2]) { 4852 default: break; 4853 case '1': // 1 string to match. 4854 if (Name[3] != '6') 4855 break; 4856 return MCK__DOT_p16; // ".p16" 4857 case '6': // 1 string to match. 4858 if (Name[3] != '4') 4859 break; 4860 return MCK__DOT_p64; // ".p64" 4861 } 4862 break; 4863 case 's': // 3 strings to match. 4864 switch (Name[2]) { 4865 default: break; 4866 case '1': // 1 string to match. 4867 if (Name[3] != '6') 4868 break; 4869 return MCK__DOT_s16; // ".s16" 4870 case '3': // 1 string to match. 4871 if (Name[3] != '2') 4872 break; 4873 return MCK__DOT_s32; // ".s32" 4874 case '6': // 1 string to match. 4875 if (Name[3] != '4') 4876 break; 4877 return MCK__DOT_s64; // ".s64" 4878 } 4879 break; 4880 case 'u': // 3 strings to match. 4881 switch (Name[2]) { 4882 default: break; 4883 case '1': // 1 string to match. 4884 if (Name[3] != '6') 4885 break; 4886 return MCK__DOT_u16; // ".u16" 4887 case '3': // 1 string to match. 4888 if (Name[3] != '2') 4889 break; 4890 return MCK__DOT_u32; // ".u32" 4891 case '6': // 1 string to match. 4892 if (Name[3] != '4') 4893 break; 4894 return MCK__DOT_u64; // ".u64" 4895 } 4896 break; 4897 } 4898 break; 4899 } 4900 return InvalidMatchClass; 4901} 4902 4903/// isSubclass - Compute whether \p A is a subclass of \p B. 4904static bool isSubclass(MatchClassKind A, MatchClassKind B) { 4905 if (A == B) 4906 return true; 4907 4908 switch (A) { 4909 default: 4910 return false; 4911 4912 case MCK__DOT_d: 4913 switch (B) { 4914 default: return false; 4915 case MCK__DOT_f64: return true; 4916 case MCK__DOT_64: return true; 4917 } 4918 4919 case MCK__DOT_f: 4920 switch (B) { 4921 default: return false; 4922 case MCK__DOT_f32: return true; 4923 case MCK__DOT_32: return true; 4924 } 4925 4926 case MCK__DOT_s16: 4927 switch (B) { 4928 default: return false; 4929 case MCK__DOT_i16: return true; 4930 case MCK__DOT_16: return true; 4931 } 4932 4933 case MCK__DOT_s32: 4934 switch (B) { 4935 default: return false; 4936 case MCK__DOT_i32: return true; 4937 case MCK__DOT_32: return true; 4938 } 4939 4940 case MCK__DOT_s64: 4941 switch (B) { 4942 default: return false; 4943 case MCK__DOT_i64: return true; 4944 case MCK__DOT_64: return true; 4945 } 4946 4947 case MCK__DOT_s8: 4948 switch (B) { 4949 default: return false; 4950 case MCK__DOT_i8: return true; 4951 case MCK__DOT_8: return true; 4952 } 4953 4954 case MCK__DOT_u16: 4955 switch (B) { 4956 default: return false; 4957 case MCK__DOT_i16: return true; 4958 case MCK__DOT_16: return true; 4959 } 4960 4961 case MCK__DOT_u32: 4962 switch (B) { 4963 default: return false; 4964 case MCK__DOT_i32: return true; 4965 case MCK__DOT_32: return true; 4966 } 4967 4968 case MCK__DOT_u64: 4969 switch (B) { 4970 default: return false; 4971 case MCK__DOT_i64: return true; 4972 case MCK__DOT_64: return true; 4973 } 4974 4975 case MCK__DOT_u8: 4976 switch (B) { 4977 default: return false; 4978 case MCK__DOT_i8: return true; 4979 case MCK__DOT_8: return true; 4980 } 4981 4982 case MCK__DOT_f32: 4983 return B == MCK__DOT_32; 4984 4985 case MCK__DOT_f64: 4986 return B == MCK__DOT_64; 4987 4988 case MCK__DOT_i16: 4989 return B == MCK__DOT_16; 4990 4991 case MCK__DOT_i32: 4992 return B == MCK__DOT_32; 4993 4994 case MCK__DOT_i64: 4995 return B == MCK__DOT_64; 4996 4997 case MCK__DOT_i8: 4998 return B == MCK__DOT_8; 4999 5000 case MCK__DOT_p16: 5001 return B == MCK__DOT_16; 5002 5003 case MCK__DOT_p8: 5004 return B == MCK__DOT_8; 5005 5006 case MCK_Reg11: 5007 switch (B) { 5008 default: return false; 5009 case MCK_tcGPR: return true; 5010 case MCK_Reg10: return true; 5011 case MCK_Reg8: return true; 5012 case MCK_hGPR: return true; 5013 case MCK_rGPR: return true; 5014 case MCK_GPRnopc: return true; 5015 case MCK_GPR: return true; 5016 case MCK_GPRwithAPSR: return true; 5017 } 5018 5019 case MCK_Reg59: 5020 switch (B) { 5021 default: return false; 5022 case MCK_Reg60: return true; 5023 case MCK_Reg61: return true; 5024 case MCK_Reg62: return true; 5025 case MCK_Reg63: return true; 5026 case MCK_Reg64: return true; 5027 case MCK_Reg65: return true; 5028 case MCK_Reg66: return true; 5029 case MCK_QQQQPR: return true; 5030 } 5031 5032 case MCK_Reg75: 5033 switch (B) { 5034 default: return false; 5035 case MCK_Reg72: return true; 5036 case MCK_Reg74: return true; 5037 case MCK_GPRPair: return true; 5038 } 5039 5040 case MCK_APSR_NZCV: 5041 return B == MCK_GPRwithAPSR; 5042 5043 case MCK_GPRsp: 5044 switch (B) { 5045 default: return false; 5046 case MCK_Reg8: return true; 5047 case MCK_hGPR: return true; 5048 case MCK_GPRnopc: return true; 5049 case MCK_GPR: return true; 5050 case MCK_GPRwithAPSR: return true; 5051 } 5052 5053 case MCK_LR: 5054 switch (B) { 5055 default: return false; 5056 case MCK_Reg10: return true; 5057 case MCK_Reg8: return true; 5058 case MCK_hGPR: return true; 5059 case MCK_rGPR: return true; 5060 case MCK_GPRnopc: return true; 5061 case MCK_GPR: return true; 5062 case MCK_GPRwithAPSR: return true; 5063 } 5064 5065 case MCK_PC: 5066 switch (B) { 5067 default: return false; 5068 case MCK_hGPR: return true; 5069 case MCK_tGPRwithpc: return true; 5070 case MCK_GPR: return true; 5071 } 5072 5073 case MCK_Reg60: 5074 switch (B) { 5075 default: return false; 5076 case MCK_Reg61: return true; 5077 case MCK_Reg62: return true; 5078 case MCK_Reg63: return true; 5079 case MCK_Reg64: return true; 5080 case MCK_Reg65: return true; 5081 case MCK_Reg66: return true; 5082 case MCK_QQQQPR: return true; 5083 } 5084 5085 case MCK_Reg68: 5086 switch (B) { 5087 default: return false; 5088 case MCK_Reg72: return true; 5089 case MCK_Reg69: return true; 5090 case MCK_Reg70: return true; 5091 case MCK_GPRPair: return true; 5092 } 5093 5094 case MCK_Reg73: 5095 switch (B) { 5096 default: return false; 5097 case MCK_Reg74: return true; 5098 case MCK_Reg70: return true; 5099 case MCK_GPRPair: return true; 5100 } 5101 5102 case MCK_Reg100: 5103 switch (B) { 5104 default: return false; 5105 case MCK_Reg101: return true; 5106 case MCK_Reg102: return true; 5107 case MCK_Reg57: return true; 5108 case MCK_Reg58: return true; 5109 case MCK_Reg103: return true; 5110 case MCK_Reg55: return true; 5111 case MCK_Reg104: return true; 5112 case MCK_Reg56: return true; 5113 case MCK_Reg105: return true; 5114 case MCK_Reg53: return true; 5115 case MCK_Reg54: return true; 5116 case MCK_Reg106: return true; 5117 case MCK_Reg51: return true; 5118 case MCK_Reg52: return true; 5119 case MCK_DQuad: return true; 5120 } 5121 5122 case MCK_Reg45: 5123 switch (B) { 5124 default: return false; 5125 case MCK_Reg46: return true; 5126 case MCK_Reg57: return true; 5127 case MCK_Reg58: return true; 5128 case MCK_Reg47: return true; 5129 case MCK_Reg55: return true; 5130 case MCK_Reg48: return true; 5131 case MCK_Reg56: return true; 5132 case MCK_Reg53: return true; 5133 case MCK_Reg54: return true; 5134 case MCK_Reg51: return true; 5135 case MCK_QQPR: return true; 5136 case MCK_Reg52: return true; 5137 case MCK_DQuad: return true; 5138 } 5139 5140 case MCK_Reg61: 5141 switch (B) { 5142 default: return false; 5143 case MCK_Reg62: return true; 5144 case MCK_Reg63: return true; 5145 case MCK_Reg64: return true; 5146 case MCK_Reg65: return true; 5147 case MCK_Reg66: return true; 5148 case MCK_QQQQPR: return true; 5149 } 5150 5151 case MCK_Reg72: 5152 return B == MCK_GPRPair; 5153 5154 case MCK_Reg74: 5155 return B == MCK_GPRPair; 5156 5157 case MCK_Reg83: 5158 switch (B) { 5159 default: return false; 5160 case MCK_Reg84: return true; 5161 case MCK_Reg76: return true; 5162 case MCK_Reg77: return true; 5163 case MCK_Reg85: return true; 5164 case MCK_Reg78: return true; 5165 case MCK_Reg86: return true; 5166 case MCK_Reg79: return true; 5167 case MCK_Reg80: return true; 5168 case MCK_Reg87: return true; 5169 case MCK_Reg81: return true; 5170 case MCK_DTriple: return true; 5171 } 5172 5173 case MCK_Reg88: 5174 switch (B) { 5175 default: return false; 5176 case MCK_Reg89: return true; 5177 case MCK_Reg76: return true; 5178 case MCK_Reg77: return true; 5179 case MCK_Reg90: return true; 5180 case MCK_Reg78: return true; 5181 case MCK_Reg91: return true; 5182 case MCK_Reg79: return true; 5183 case MCK_Reg80: return true; 5184 case MCK_Reg92: return true; 5185 case MCK_Reg81: return true; 5186 case MCK_DTriple: return true; 5187 } 5188 5189 case MCK_Reg101: 5190 switch (B) { 5191 default: return false; 5192 case MCK_Reg102: return true; 5193 case MCK_Reg58: return true; 5194 case MCK_Reg103: return true; 5195 case MCK_Reg55: return true; 5196 case MCK_Reg104: return true; 5197 case MCK_Reg56: return true; 5198 case MCK_Reg105: return true; 5199 case MCK_Reg53: return true; 5200 case MCK_Reg54: return true; 5201 case MCK_Reg106: return true; 5202 case MCK_Reg51: return true; 5203 case MCK_Reg52: return true; 5204 case MCK_DQuad: return true; 5205 } 5206 5207 case MCK_Reg0: 5208 switch (B) { 5209 default: return false; 5210 case MCK_tcGPR: return true; 5211 case MCK_tGPR: return true; 5212 case MCK_tGPRwithpc: return true; 5213 case MCK_rGPR: return true; 5214 case MCK_GPRnopc: return true; 5215 case MCK_GPR: return true; 5216 case MCK_GPRwithAPSR: return true; 5217 } 5218 5219 case MCK_Reg46: 5220 switch (B) { 5221 default: return false; 5222 case MCK_Reg47: return true; 5223 case MCK_Reg55: return true; 5224 case MCK_Reg48: return true; 5225 case MCK_Reg56: return true; 5226 case MCK_Reg53: return true; 5227 case MCK_Reg54: return true; 5228 case MCK_Reg51: return true; 5229 case MCK_QQPR: return true; 5230 case MCK_Reg52: return true; 5231 case MCK_DQuad: return true; 5232 } 5233 5234 case MCK_Reg62: 5235 switch (B) { 5236 default: return false; 5237 case MCK_Reg63: return true; 5238 case MCK_Reg64: return true; 5239 case MCK_Reg65: return true; 5240 case MCK_Reg66: return true; 5241 case MCK_QQQQPR: return true; 5242 } 5243 5244 case MCK_Reg69: 5245 switch (B) { 5246 default: return false; 5247 case MCK_Reg70: return true; 5248 case MCK_GPRPair: return true; 5249 } 5250 5251 case MCK_Reg84: 5252 switch (B) { 5253 default: return false; 5254 case MCK_Reg77: return true; 5255 case MCK_Reg85: return true; 5256 case MCK_Reg78: return true; 5257 case MCK_Reg86: return true; 5258 case MCK_Reg79: return true; 5259 case MCK_Reg80: return true; 5260 case MCK_Reg87: return true; 5261 case MCK_Reg81: return true; 5262 case MCK_DTriple: return true; 5263 } 5264 5265 case MCK_Reg89: 5266 switch (B) { 5267 default: return false; 5268 case MCK_Reg90: return true; 5269 case MCK_Reg78: return true; 5270 case MCK_Reg91: return true; 5271 case MCK_Reg79: return true; 5272 case MCK_Reg80: return true; 5273 case MCK_Reg92: return true; 5274 case MCK_Reg81: return true; 5275 case MCK_DTriple: return true; 5276 } 5277 5278 case MCK_Reg93: 5279 switch (B) { 5280 default: return false; 5281 case MCK_Reg94: return true; 5282 case MCK_Reg95: return true; 5283 case MCK_Reg96: return true; 5284 case MCK_Reg97: return true; 5285 case MCK_Reg98: return true; 5286 case MCK_DTripleSpc: return true; 5287 } 5288 5289 case MCK_Reg102: 5290 switch (B) { 5291 default: return false; 5292 case MCK_Reg103: return true; 5293 case MCK_Reg104: return true; 5294 case MCK_Reg56: return true; 5295 case MCK_Reg105: return true; 5296 case MCK_Reg53: return true; 5297 case MCK_Reg54: return true; 5298 case MCK_Reg106: return true; 5299 case MCK_Reg51: return true; 5300 case MCK_Reg52: return true; 5301 case MCK_DQuad: return true; 5302 } 5303 5304 case MCK_QPR_8: 5305 switch (B) { 5306 default: return false; 5307 case MCK_Reg26: return true; 5308 case MCK_Reg27: return true; 5309 case MCK_QPR_VFP2: return true; 5310 case MCK_Reg24: return true; 5311 case MCK_Reg25: return true; 5312 case MCK_QPR: return true; 5313 case MCK_DPair: return true; 5314 } 5315 5316 case MCK_Reg57: 5317 switch (B) { 5318 default: return false; 5319 case MCK_Reg58: return true; 5320 case MCK_Reg55: return true; 5321 case MCK_Reg56: return true; 5322 case MCK_Reg53: return true; 5323 case MCK_Reg54: return true; 5324 case MCK_Reg51: return true; 5325 case MCK_Reg52: return true; 5326 case MCK_DQuad: return true; 5327 } 5328 5329 case MCK_Reg63: 5330 switch (B) { 5331 default: return false; 5332 case MCK_Reg64: return true; 5333 case MCK_Reg65: return true; 5334 case MCK_Reg66: return true; 5335 case MCK_QQQQPR: return true; 5336 } 5337 5338 case MCK_tcGPR: 5339 switch (B) { 5340 default: return false; 5341 case MCK_rGPR: return true; 5342 case MCK_GPRnopc: return true; 5343 case MCK_GPR: return true; 5344 case MCK_GPRwithAPSR: return true; 5345 } 5346 5347 case MCK_Reg10: 5348 switch (B) { 5349 default: return false; 5350 case MCK_Reg8: return true; 5351 case MCK_hGPR: return true; 5352 case MCK_rGPR: return true; 5353 case MCK_GPRnopc: return true; 5354 case MCK_GPR: return true; 5355 case MCK_GPRwithAPSR: return true; 5356 } 5357 5358 case MCK_Reg40: 5359 switch (B) { 5360 default: return false; 5361 case MCK_Reg41: return true; 5362 case MCK_Reg42: return true; 5363 case MCK_Reg43: return true; 5364 case MCK_DPairSpc: return true; 5365 } 5366 5367 case MCK_Reg58: 5368 switch (B) { 5369 default: return false; 5370 case MCK_Reg55: return true; 5371 case MCK_Reg56: return true; 5372 case MCK_Reg53: return true; 5373 case MCK_Reg54: return true; 5374 case MCK_Reg51: return true; 5375 case MCK_Reg52: return true; 5376 case MCK_DQuad: return true; 5377 } 5378 5379 case MCK_Reg64: 5380 switch (B) { 5381 default: return false; 5382 case MCK_Reg65: return true; 5383 case MCK_Reg66: return true; 5384 case MCK_QQQQPR: return true; 5385 } 5386 5387 case MCK_Reg70: 5388 return B == MCK_GPRPair; 5389 5390 case MCK_Reg76: 5391 switch (B) { 5392 default: return false; 5393 case MCK_Reg77: return true; 5394 case MCK_Reg78: return true; 5395 case MCK_Reg79: return true; 5396 case MCK_Reg80: return true; 5397 case MCK_Reg81: return true; 5398 case MCK_DTriple: return true; 5399 } 5400 5401 case MCK_Reg94: 5402 switch (B) { 5403 default: return false; 5404 case MCK_Reg95: return true; 5405 case MCK_Reg96: return true; 5406 case MCK_Reg97: return true; 5407 case MCK_Reg98: return true; 5408 case MCK_DTripleSpc: return true; 5409 } 5410 5411 case MCK_Reg103: 5412 switch (B) { 5413 default: return false; 5414 case MCK_Reg104: return true; 5415 case MCK_Reg105: return true; 5416 case MCK_Reg53: return true; 5417 case MCK_Reg54: return true; 5418 case MCK_Reg106: return true; 5419 case MCK_Reg51: return true; 5420 case MCK_Reg52: return true; 5421 case MCK_DQuad: return true; 5422 } 5423 5424 case MCK_Reg8: 5425 switch (B) { 5426 default: return false; 5427 case MCK_hGPR: return true; 5428 case MCK_GPRnopc: return true; 5429 case MCK_GPR: return true; 5430 case MCK_GPRwithAPSR: return true; 5431 } 5432 5433 case MCK_Reg26: 5434 switch (B) { 5435 default: return false; 5436 case MCK_Reg27: return true; 5437 case MCK_Reg24: return true; 5438 case MCK_Reg25: return true; 5439 case MCK_DPair: return true; 5440 } 5441 5442 case MCK_Reg47: 5443 switch (B) { 5444 default: return false; 5445 case MCK_Reg48: return true; 5446 case MCK_Reg53: return true; 5447 case MCK_Reg54: return true; 5448 case MCK_Reg51: return true; 5449 case MCK_QQPR: return true; 5450 case MCK_Reg52: return true; 5451 case MCK_DQuad: return true; 5452 } 5453 5454 case MCK_Reg55: 5455 switch (B) { 5456 default: return false; 5457 case MCK_Reg56: return true; 5458 case MCK_Reg53: return true; 5459 case MCK_Reg54: return true; 5460 case MCK_Reg51: return true; 5461 case MCK_Reg52: return true; 5462 case MCK_DQuad: return true; 5463 } 5464 5465 case MCK_Reg65: 5466 switch (B) { 5467 default: return false; 5468 case MCK_Reg66: return true; 5469 case MCK_QQQQPR: return true; 5470 } 5471 5472 case MCK_Reg77: 5473 switch (B) { 5474 default: return false; 5475 case MCK_Reg78: return true; 5476 case MCK_Reg79: return true; 5477 case MCK_Reg80: return true; 5478 case MCK_Reg81: return true; 5479 case MCK_DTriple: return true; 5480 } 5481 5482 case MCK_Reg85: 5483 switch (B) { 5484 default: return false; 5485 case MCK_Reg86: return true; 5486 case MCK_Reg79: return true; 5487 case MCK_Reg80: return true; 5488 case MCK_Reg87: return true; 5489 case MCK_Reg81: return true; 5490 case MCK_DTriple: return true; 5491 } 5492 5493 case MCK_Reg90: 5494 switch (B) { 5495 default: return false; 5496 case MCK_Reg91: return true; 5497 case MCK_Reg79: return true; 5498 case MCK_Reg80: return true; 5499 case MCK_Reg92: return true; 5500 case MCK_Reg81: return true; 5501 case MCK_DTriple: return true; 5502 } 5503 5504 case MCK_Reg104: 5505 switch (B) { 5506 default: return false; 5507 case MCK_Reg105: return true; 5508 case MCK_Reg54: return true; 5509 case MCK_Reg106: return true; 5510 case MCK_Reg51: return true; 5511 case MCK_Reg52: return true; 5512 case MCK_DQuad: return true; 5513 } 5514 5515 case MCK_Reg27: 5516 switch (B) { 5517 default: return false; 5518 case MCK_Reg24: return true; 5519 case MCK_Reg25: return true; 5520 case MCK_DPair: return true; 5521 } 5522 5523 case MCK_Reg41: 5524 switch (B) { 5525 default: return false; 5526 case MCK_Reg42: return true; 5527 case MCK_Reg43: return true; 5528 case MCK_DPairSpc: return true; 5529 } 5530 5531 case MCK_Reg48: 5532 switch (B) { 5533 default: return false; 5534 case MCK_Reg51: return true; 5535 case MCK_QQPR: return true; 5536 case MCK_Reg52: return true; 5537 case MCK_DQuad: return true; 5538 } 5539 5540 case MCK_Reg56: 5541 switch (B) { 5542 default: return false; 5543 case MCK_Reg53: return true; 5544 case MCK_Reg54: return true; 5545 case MCK_Reg51: return true; 5546 case MCK_Reg52: return true; 5547 case MCK_DQuad: return true; 5548 } 5549 5550 case MCK_Reg66: 5551 return B == MCK_QQQQPR; 5552 5553 case MCK_Reg78: 5554 switch (B) { 5555 default: return false; 5556 case MCK_Reg79: return true; 5557 case MCK_Reg80: return true; 5558 case MCK_Reg81: return true; 5559 case MCK_DTriple: return true; 5560 } 5561 5562 case MCK_Reg86: 5563 switch (B) { 5564 default: return false; 5565 case MCK_Reg80: return true; 5566 case MCK_Reg87: return true; 5567 case MCK_Reg81: return true; 5568 case MCK_DTriple: return true; 5569 } 5570 5571 case MCK_Reg91: 5572 switch (B) { 5573 default: return false; 5574 case MCK_Reg92: return true; 5575 case MCK_Reg81: return true; 5576 case MCK_DTriple: return true; 5577 } 5578 5579 case MCK_Reg95: 5580 switch (B) { 5581 default: return false; 5582 case MCK_Reg96: return true; 5583 case MCK_Reg97: return true; 5584 case MCK_Reg98: return true; 5585 case MCK_DTripleSpc: return true; 5586 } 5587 5588 case MCK_Reg105: 5589 switch (B) { 5590 default: return false; 5591 case MCK_Reg106: return true; 5592 case MCK_Reg52: return true; 5593 case MCK_DQuad: return true; 5594 } 5595 5596 case MCK_DPR_8: 5597 switch (B) { 5598 default: return false; 5599 case MCK_DPR_VFP2: return true; 5600 case MCK_DPR: return true; 5601 } 5602 5603 case MCK_QPR_VFP2: 5604 switch (B) { 5605 default: return false; 5606 case MCK_Reg24: return true; 5607 case MCK_Reg25: return true; 5608 case MCK_QPR: return true; 5609 case MCK_DPair: return true; 5610 } 5611 5612 case MCK_hGPR: 5613 return B == MCK_GPR; 5614 5615 case MCK_tGPR: 5616 switch (B) { 5617 default: return false; 5618 case MCK_tGPRwithpc: return true; 5619 case MCK_rGPR: return true; 5620 case MCK_GPRnopc: return true; 5621 case MCK_GPR: return true; 5622 case MCK_GPRwithAPSR: return true; 5623 } 5624 5625 case MCK_tGPRwithpc: 5626 return B == MCK_GPR; 5627 5628 case MCK_Reg96: 5629 switch (B) { 5630 default: return false; 5631 case MCK_Reg97: return true; 5632 case MCK_Reg98: return true; 5633 case MCK_DTripleSpc: return true; 5634 } 5635 5636 case MCK_Reg53: 5637 switch (B) { 5638 default: return false; 5639 case MCK_Reg54: return true; 5640 case MCK_Reg51: return true; 5641 case MCK_Reg52: return true; 5642 case MCK_DQuad: return true; 5643 } 5644 5645 case MCK_Reg42: 5646 switch (B) { 5647 default: return false; 5648 case MCK_Reg43: return true; 5649 case MCK_DPairSpc: return true; 5650 } 5651 5652 case MCK_Reg54: 5653 switch (B) { 5654 default: return false; 5655 case MCK_Reg51: return true; 5656 case MCK_Reg52: return true; 5657 case MCK_DQuad: return true; 5658 } 5659 5660 case MCK_Reg79: 5661 switch (B) { 5662 default: return false; 5663 case MCK_Reg80: return true; 5664 case MCK_Reg81: return true; 5665 case MCK_DTriple: return true; 5666 } 5667 5668 case MCK_Reg97: 5669 switch (B) { 5670 default: return false; 5671 case MCK_Reg98: return true; 5672 case MCK_DTripleSpc: return true; 5673 } 5674 5675 case MCK_Reg106: 5676 return B == MCK_DQuad; 5677 5678 case MCK_rGPR: 5679 switch (B) { 5680 default: return false; 5681 case MCK_GPRnopc: return true; 5682 case MCK_GPR: return true; 5683 case MCK_GPRwithAPSR: return true; 5684 } 5685 5686 case MCK_Reg24: 5687 switch (B) { 5688 default: return false; 5689 case MCK_Reg25: return true; 5690 case MCK_DPair: return true; 5691 } 5692 5693 case MCK_Reg51: 5694 switch (B) { 5695 default: return false; 5696 case MCK_Reg52: return true; 5697 case MCK_DQuad: return true; 5698 } 5699 5700 case MCK_Reg80: 5701 switch (B) { 5702 default: return false; 5703 case MCK_Reg81: return true; 5704 case MCK_DTriple: return true; 5705 } 5706 5707 case MCK_Reg87: 5708 return B == MCK_DTriple; 5709 5710 case MCK_Reg92: 5711 return B == MCK_DTriple; 5712 5713 case MCK_GPRnopc: 5714 switch (B) { 5715 default: return false; 5716 case MCK_GPR: return true; 5717 case MCK_GPRwithAPSR: return true; 5718 } 5719 5720 case MCK_QQPR: 5721 return B == MCK_DQuad; 5722 5723 case MCK_Reg25: 5724 return B == MCK_DPair; 5725 5726 case MCK_Reg43: 5727 return B == MCK_DPairSpc; 5728 5729 case MCK_Reg52: 5730 return B == MCK_DQuad; 5731 5732 case MCK_Reg81: 5733 return B == MCK_DTriple; 5734 5735 case MCK_Reg98: 5736 return B == MCK_DTripleSpc; 5737 5738 case MCK_DPR_VFP2: 5739 return B == MCK_DPR; 5740 5741 case MCK_QPR: 5742 return B == MCK_DPair; 5743 5744 case MCK_SPR_8: 5745 return B == MCK_HPR; 5746 } 5747} 5748 5749static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { 5750 ARMOperand &Operand = (ARMOperand&)GOp; 5751 if (Kind == InvalidMatchClass) 5752 return MCTargetAsmParser::Match_InvalidOperand; 5753 5754 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN) 5755 return isSubclass(matchTokenString(Operand.getToken()), Kind) ? 5756 MCTargetAsmParser::Match_Success : 5757 MCTargetAsmParser::Match_InvalidOperand; 5758 5759 switch (Kind) { 5760 default: break; 5761 // 'AM2OffsetImm' class 5762 case MCK_AM2OffsetImm: { 5763 DiagnosticPredicate DP(Operand.isAM2OffsetImm()); 5764 if (DP.isMatch()) 5765 return MCTargetAsmParser::Match_Success; 5766 break; 5767 } 5768 // 'AM3Offset' class 5769 case MCK_AM3Offset: { 5770 DiagnosticPredicate DP(Operand.isAM3Offset()); 5771 if (DP.isMatch()) 5772 return MCTargetAsmParser::Match_Success; 5773 break; 5774 } 5775 // 'ARMBranchTarget' class 5776 case MCK_ARMBranchTarget: { 5777 DiagnosticPredicate DP(Operand.isARMBranchTarget()); 5778 if (DP.isMatch()) 5779 return MCTargetAsmParser::Match_Success; 5780 break; 5781 } 5782 // 'AddrMode3' class 5783 case MCK_AddrMode3: { 5784 DiagnosticPredicate DP(Operand.isAddrMode3()); 5785 if (DP.isMatch()) 5786 return MCTargetAsmParser::Match_Success; 5787 break; 5788 } 5789 // 'AddrMode5' class 5790 case MCK_AddrMode5: { 5791 DiagnosticPredicate DP(Operand.isAddrMode5()); 5792 if (DP.isMatch()) 5793 return MCTargetAsmParser::Match_Success; 5794 break; 5795 } 5796 // 'AddrMode5FP16' class 5797 case MCK_AddrMode5FP16: { 5798 DiagnosticPredicate DP(Operand.isAddrMode5FP16()); 5799 if (DP.isMatch()) 5800 return MCTargetAsmParser::Match_Success; 5801 break; 5802 } 5803 // 'AlignedMemory16' class 5804 case MCK_AlignedMemory16: { 5805 DiagnosticPredicate DP(Operand.isAlignedMemory16()); 5806 if (DP.isMatch()) 5807 return MCTargetAsmParser::Match_Success; 5808 if (DP.isNearMatch()) 5809 return ARMAsmParser::Match_AlignedMemory16; 5810 break; 5811 } 5812 // 'AlignedMemory32' class 5813 case MCK_AlignedMemory32: { 5814 DiagnosticPredicate DP(Operand.isAlignedMemory32()); 5815 if (DP.isMatch()) 5816 return MCTargetAsmParser::Match_Success; 5817 if (DP.isNearMatch()) 5818 return ARMAsmParser::Match_AlignedMemory32; 5819 break; 5820 } 5821 // 'AlignedMemory64' class 5822 case MCK_AlignedMemory64: { 5823 DiagnosticPredicate DP(Operand.isAlignedMemory64()); 5824 if (DP.isMatch()) 5825 return MCTargetAsmParser::Match_Success; 5826 if (DP.isNearMatch()) 5827 return ARMAsmParser::Match_AlignedMemory64; 5828 break; 5829 } 5830 // 'AlignedMemory64or128' class 5831 case MCK_AlignedMemory64or128: { 5832 DiagnosticPredicate DP(Operand.isAlignedMemory64or128()); 5833 if (DP.isMatch()) 5834 return MCTargetAsmParser::Match_Success; 5835 if (DP.isNearMatch()) 5836 return ARMAsmParser::Match_AlignedMemory64or128; 5837 break; 5838 } 5839 // 'AlignedMemory64or128or256' class 5840 case MCK_AlignedMemory64or128or256: { 5841 DiagnosticPredicate DP(Operand.isAlignedMemory64or128or256()); 5842 if (DP.isMatch()) 5843 return MCTargetAsmParser::Match_Success; 5844 if (DP.isNearMatch()) 5845 return ARMAsmParser::Match_AlignedMemory64or128or256; 5846 break; 5847 } 5848 // 'AlignedMemoryNone' class 5849 case MCK_AlignedMemoryNone: { 5850 DiagnosticPredicate DP(Operand.isAlignedMemoryNone()); 5851 if (DP.isMatch()) 5852 return MCTargetAsmParser::Match_Success; 5853 if (DP.isNearMatch()) 5854 return ARMAsmParser::Match_AlignedMemoryNone; 5855 break; 5856 } 5857 // 'AlignedMemory' class 5858 case MCK_AlignedMemory: { 5859 DiagnosticPredicate DP(Operand.isAlignedMemory()); 5860 if (DP.isMatch()) 5861 return MCTargetAsmParser::Match_Success; 5862 break; 5863 } 5864 // 'DupAlignedMemory16' class 5865 case MCK_DupAlignedMemory16: { 5866 DiagnosticPredicate DP(Operand.isDupAlignedMemory16()); 5867 if (DP.isMatch()) 5868 return MCTargetAsmParser::Match_Success; 5869 if (DP.isNearMatch()) 5870 return ARMAsmParser::Match_DupAlignedMemory16; 5871 break; 5872 } 5873 // 'DupAlignedMemory32' class 5874 case MCK_DupAlignedMemory32: { 5875 DiagnosticPredicate DP(Operand.isDupAlignedMemory32()); 5876 if (DP.isMatch()) 5877 return MCTargetAsmParser::Match_Success; 5878 if (DP.isNearMatch()) 5879 return ARMAsmParser::Match_DupAlignedMemory32; 5880 break; 5881 } 5882 // 'DupAlignedMemory64' class 5883 case MCK_DupAlignedMemory64: { 5884 DiagnosticPredicate DP(Operand.isDupAlignedMemory64()); 5885 if (DP.isMatch()) 5886 return MCTargetAsmParser::Match_Success; 5887 if (DP.isNearMatch()) 5888 return ARMAsmParser::Match_DupAlignedMemory64; 5889 break; 5890 } 5891 // 'DupAlignedMemory64or128' class 5892 case MCK_DupAlignedMemory64or128: { 5893 DiagnosticPredicate DP(Operand.isDupAlignedMemory64or128()); 5894 if (DP.isMatch()) 5895 return MCTargetAsmParser::Match_Success; 5896 if (DP.isNearMatch()) 5897 return ARMAsmParser::Match_DupAlignedMemory64or128; 5898 break; 5899 } 5900 // 'DupAlignedMemoryNone' class 5901 case MCK_DupAlignedMemoryNone: { 5902 DiagnosticPredicate DP(Operand.isDupAlignedMemoryNone()); 5903 if (DP.isMatch()) 5904 return MCTargetAsmParser::Match_Success; 5905 if (DP.isNearMatch()) 5906 return ARMAsmParser::Match_DupAlignedMemoryNone; 5907 break; 5908 } 5909 // 'AdrLabel' class 5910 case MCK_AdrLabel: { 5911 DiagnosticPredicate DP(Operand.isAdrLabel()); 5912 if (DP.isMatch()) 5913 return MCTargetAsmParser::Match_Success; 5914 break; 5915 } 5916 // 'BankedReg' class 5917 case MCK_BankedReg: { 5918 DiagnosticPredicate DP(Operand.isBankedReg()); 5919 if (DP.isMatch()) 5920 return MCTargetAsmParser::Match_Success; 5921 break; 5922 } 5923 // 'Bitfield' class 5924 case MCK_Bitfield: { 5925 DiagnosticPredicate DP(Operand.isBitfield()); 5926 if (DP.isMatch()) 5927 return MCTargetAsmParser::Match_Success; 5928 break; 5929 } 5930 // 'CCOut' class 5931 case MCK_CCOut: { 5932 DiagnosticPredicate DP(Operand.isCCOut()); 5933 if (DP.isMatch()) 5934 return MCTargetAsmParser::Match_Success; 5935 break; 5936 } 5937 // 'CondCode' class 5938 case MCK_CondCode: { 5939 DiagnosticPredicate DP(Operand.isCondCode()); 5940 if (DP.isMatch()) 5941 return MCTargetAsmParser::Match_Success; 5942 break; 5943 } 5944 // 'CoprocNum' class 5945 case MCK_CoprocNum: { 5946 DiagnosticPredicate DP(Operand.isCoprocNum()); 5947 if (DP.isMatch()) 5948 return MCTargetAsmParser::Match_Success; 5949 break; 5950 } 5951 // 'CoprocOption' class 5952 case MCK_CoprocOption: { 5953 DiagnosticPredicate DP(Operand.isCoprocOption()); 5954 if (DP.isMatch()) 5955 return MCTargetAsmParser::Match_Success; 5956 break; 5957 } 5958 // 'CoprocReg' class 5959 case MCK_CoprocReg: { 5960 DiagnosticPredicate DP(Operand.isCoprocReg()); 5961 if (DP.isMatch()) 5962 return MCTargetAsmParser::Match_Success; 5963 break; 5964 } 5965 // 'DPRRegList' class 5966 case MCK_DPRRegList: { 5967 DiagnosticPredicate DP(Operand.isDPRRegList()); 5968 if (DP.isMatch()) 5969 return MCTargetAsmParser::Match_Success; 5970 if (DP.isNearMatch()) 5971 return ARMAsmParser::Match_DPR_RegList; 5972 break; 5973 } 5974 // 'FPImm' class 5975 case MCK_FPImm: { 5976 DiagnosticPredicate DP(Operand.isFPImm()); 5977 if (DP.isMatch()) 5978 return MCTargetAsmParser::Match_Success; 5979 break; 5980 } 5981 // 'Imm0_15' class 5982 case MCK_Imm0_15: { 5983 DiagnosticPredicate DP(Operand.isImmediate<0,15>()); 5984 if (DP.isMatch()) 5985 return MCTargetAsmParser::Match_Success; 5986 if (DP.isNearMatch()) 5987 return ARMAsmParser::Match_Imm0_15; 5988 break; 5989 } 5990 // 'Imm0_1' class 5991 case MCK_Imm0_1: { 5992 DiagnosticPredicate DP(Operand.isImmediate<0,1>()); 5993 if (DP.isMatch()) 5994 return MCTargetAsmParser::Match_Success; 5995 if (DP.isNearMatch()) 5996 return ARMAsmParser::Match_Imm0_1; 5997 break; 5998 } 5999 // 'Imm0_239' class 6000 case MCK_Imm0_239: { 6001 DiagnosticPredicate DP(Operand.isImmediate<0,239>()); 6002 if (DP.isMatch()) 6003 return MCTargetAsmParser::Match_Success; 6004 if (DP.isNearMatch()) 6005 return ARMAsmParser::Match_Imm0_239; 6006 break; 6007 } 6008 // 'Imm0_255' class 6009 case MCK_Imm0_255: { 6010 DiagnosticPredicate DP(Operand.isImmediate<0,255>()); 6011 if (DP.isMatch()) 6012 return MCTargetAsmParser::Match_Success; 6013 if (DP.isNearMatch()) 6014 return ARMAsmParser::Match_Imm0_255; 6015 break; 6016 } 6017 // 'Imm0_31' class 6018 case MCK_Imm0_31: { 6019 DiagnosticPredicate DP(Operand.isImmediate<0,31>()); 6020 if (DP.isMatch()) 6021 return MCTargetAsmParser::Match_Success; 6022 if (DP.isNearMatch()) 6023 return ARMAsmParser::Match_Imm0_31; 6024 break; 6025 } 6026 // 'Imm0_32' class 6027 case MCK_Imm0_32: { 6028 DiagnosticPredicate DP(Operand.isImmediate<0,32>()); 6029 if (DP.isMatch()) 6030 return MCTargetAsmParser::Match_Success; 6031 if (DP.isNearMatch()) 6032 return ARMAsmParser::Match_Imm0_32; 6033 break; 6034 } 6035 // 'Imm0_3' class 6036 case MCK_Imm0_3: { 6037 DiagnosticPredicate DP(Operand.isImmediate<0,3>()); 6038 if (DP.isMatch()) 6039 return MCTargetAsmParser::Match_Success; 6040 if (DP.isNearMatch()) 6041 return ARMAsmParser::Match_Imm0_3; 6042 break; 6043 } 6044 // 'Imm0_63' class 6045 case MCK_Imm0_63: { 6046 DiagnosticPredicate DP(Operand.isImmediate<0,63>()); 6047 if (DP.isMatch()) 6048 return MCTargetAsmParser::Match_Success; 6049 if (DP.isNearMatch()) 6050 return ARMAsmParser::Match_Imm0_63; 6051 break; 6052 } 6053 // 'Imm0_65535' class 6054 case MCK_Imm0_65535: { 6055 DiagnosticPredicate DP(Operand.isImmediate<0,65535>()); 6056 if (DP.isMatch()) 6057 return MCTargetAsmParser::Match_Success; 6058 if (DP.isNearMatch()) 6059 return ARMAsmParser::Match_Imm0_65535; 6060 break; 6061 } 6062 // 'Imm0_65535Expr' class 6063 case MCK_Imm0_65535Expr: { 6064 DiagnosticPredicate DP(Operand.isImm0_65535Expr()); 6065 if (DP.isMatch()) 6066 return MCTargetAsmParser::Match_Success; 6067 if (DP.isNearMatch()) 6068 return ARMAsmParser::Match_Imm0_65535Expr; 6069 break; 6070 } 6071 // 'Imm0_7' class 6072 case MCK_Imm0_7: { 6073 DiagnosticPredicate DP(Operand.isImmediate<0,7>()); 6074 if (DP.isMatch()) 6075 return MCTargetAsmParser::Match_Success; 6076 if (DP.isNearMatch()) 6077 return ARMAsmParser::Match_Imm0_7; 6078 break; 6079 } 6080 // 'Imm16' class 6081 case MCK_Imm16: { 6082 DiagnosticPredicate DP(Operand.isImmediate<16,16>()); 6083 if (DP.isMatch()) 6084 return MCTargetAsmParser::Match_Success; 6085 if (DP.isNearMatch()) 6086 return ARMAsmParser::Match_Imm16; 6087 break; 6088 } 6089 // 'Imm1_15' class 6090 case MCK_Imm1_15: { 6091 DiagnosticPredicate DP(Operand.isImmediate<1,15>()); 6092 if (DP.isMatch()) 6093 return MCTargetAsmParser::Match_Success; 6094 if (DP.isNearMatch()) 6095 return ARMAsmParser::Match_Imm1_15; 6096 break; 6097 } 6098 // 'Imm1_16' class 6099 case MCK_Imm1_16: { 6100 DiagnosticPredicate DP(Operand.isImmediate<1,16>()); 6101 if (DP.isMatch()) 6102 return MCTargetAsmParser::Match_Success; 6103 if (DP.isNearMatch()) 6104 return ARMAsmParser::Match_ImmRange1_16; 6105 break; 6106 } 6107 // 'Imm1_31' class 6108 case MCK_Imm1_31: { 6109 DiagnosticPredicate DP(Operand.isImmediate<1,31>()); 6110 if (DP.isMatch()) 6111 return MCTargetAsmParser::Match_Success; 6112 if (DP.isNearMatch()) 6113 return ARMAsmParser::Match_Imm1_31; 6114 break; 6115 } 6116 // 'Imm1_32' class 6117 case MCK_Imm1_32: { 6118 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 6119 if (DP.isMatch()) 6120 return MCTargetAsmParser::Match_Success; 6121 if (DP.isNearMatch()) 6122 return ARMAsmParser::Match_ImmRange1_32; 6123 break; 6124 } 6125 // 'Imm1_7' class 6126 case MCK_Imm1_7: { 6127 DiagnosticPredicate DP(Operand.isImmediate<1,7>()); 6128 if (DP.isMatch()) 6129 return MCTargetAsmParser::Match_Success; 6130 if (DP.isNearMatch()) 6131 return ARMAsmParser::Match_Imm1_7; 6132 break; 6133 } 6134 // 'Imm24bit' class 6135 case MCK_Imm24bit: { 6136 DiagnosticPredicate DP(Operand.isImmediate<0,16777215>()); 6137 if (DP.isMatch()) 6138 return MCTargetAsmParser::Match_Success; 6139 if (DP.isNearMatch()) 6140 return ARMAsmParser::Match_Imm24bit; 6141 break; 6142 } 6143 // 'Imm256_65535Expr' class 6144 case MCK_Imm256_65535Expr: { 6145 DiagnosticPredicate DP(Operand.isImmediate<256,65535>()); 6146 if (DP.isMatch()) 6147 return MCTargetAsmParser::Match_Success; 6148 if (DP.isNearMatch()) 6149 return ARMAsmParser::Match_Imm256_65535Expr; 6150 break; 6151 } 6152 // 'Imm32' class 6153 case MCK_Imm32: { 6154 DiagnosticPredicate DP(Operand.isImmediate<32,32>()); 6155 if (DP.isMatch()) 6156 return MCTargetAsmParser::Match_Success; 6157 if (DP.isNearMatch()) 6158 return ARMAsmParser::Match_Imm32; 6159 break; 6160 } 6161 // 'Imm8' class 6162 case MCK_Imm8: { 6163 DiagnosticPredicate DP(Operand.isImmediate<8,8>()); 6164 if (DP.isMatch()) 6165 return MCTargetAsmParser::Match_Success; 6166 if (DP.isNearMatch()) 6167 return ARMAsmParser::Match_Imm8; 6168 break; 6169 } 6170 // 'Imm8_255' class 6171 case MCK_Imm8_255: { 6172 DiagnosticPredicate DP(Operand.isImmediate<8,255>()); 6173 if (DP.isMatch()) 6174 return MCTargetAsmParser::Match_Success; 6175 if (DP.isNearMatch()) 6176 return ARMAsmParser::Match_Imm8_255; 6177 break; 6178 } 6179 // 'Imm' class 6180 case MCK_Imm: { 6181 DiagnosticPredicate DP(Operand.isImm()); 6182 if (DP.isMatch()) 6183 return MCTargetAsmParser::Match_Success; 6184 break; 6185 } 6186 // 'InstSyncBarrierOpt' class 6187 case MCK_InstSyncBarrierOpt: { 6188 DiagnosticPredicate DP(Operand.isInstSyncBarrierOpt()); 6189 if (DP.isMatch()) 6190 return MCTargetAsmParser::Match_Success; 6191 break; 6192 } 6193 // 'MSRMask' class 6194 case MCK_MSRMask: { 6195 DiagnosticPredicate DP(Operand.isMSRMask()); 6196 if (DP.isMatch()) 6197 return MCTargetAsmParser::Match_Success; 6198 break; 6199 } 6200 // 'MemBarrierOpt' class 6201 case MCK_MemBarrierOpt: { 6202 DiagnosticPredicate DP(Operand.isMemBarrierOpt()); 6203 if (DP.isMatch()) 6204 return MCTargetAsmParser::Match_Success; 6205 break; 6206 } 6207 // 'MemImm0_1020s4Offset' class 6208 case MCK_MemImm0_1020s4Offset: { 6209 DiagnosticPredicate DP(Operand.isMemImm0_1020s4Offset()); 6210 if (DP.isMatch()) 6211 return MCTargetAsmParser::Match_Success; 6212 break; 6213 } 6214 // 'MemImm12Offset' class 6215 case MCK_MemImm12Offset: { 6216 DiagnosticPredicate DP(Operand.isMemImm12Offset()); 6217 if (DP.isMatch()) 6218 return MCTargetAsmParser::Match_Success; 6219 break; 6220 } 6221 // 'MemImm8Offset' class 6222 case MCK_MemImm8Offset: { 6223 DiagnosticPredicate DP(Operand.isMemImm8Offset()); 6224 if (DP.isMatch()) 6225 return MCTargetAsmParser::Match_Success; 6226 break; 6227 } 6228 // 'MemImm8s4Offset' class 6229 case MCK_MemImm8s4Offset: { 6230 DiagnosticPredicate DP(Operand.isMemImm8s4Offset()); 6231 if (DP.isMatch()) 6232 return MCTargetAsmParser::Match_Success; 6233 break; 6234 } 6235 // 'MemNegImm8Offset' class 6236 case MCK_MemNegImm8Offset: { 6237 DiagnosticPredicate DP(Operand.isMemNegImm8Offset()); 6238 if (DP.isMatch()) 6239 return MCTargetAsmParser::Match_Success; 6240 break; 6241 } 6242 // 'MemNoOffset' class 6243 case MCK_MemNoOffset: { 6244 DiagnosticPredicate DP(Operand.isMemNoOffset()); 6245 if (DP.isMatch()) 6246 return MCTargetAsmParser::Match_Success; 6247 break; 6248 } 6249 // 'MemPosImm8Offset' class 6250 case MCK_MemPosImm8Offset: { 6251 DiagnosticPredicate DP(Operand.isMemPosImm8Offset()); 6252 if (DP.isMatch()) 6253 return MCTargetAsmParser::Match_Success; 6254 break; 6255 } 6256 // 'MemRegOffset' class 6257 case MCK_MemRegOffset: { 6258 DiagnosticPredicate DP(Operand.isMemRegOffset()); 6259 if (DP.isMatch()) 6260 return MCTargetAsmParser::Match_Success; 6261 break; 6262 } 6263 // 'ModImm' class 6264 case MCK_ModImm: { 6265 DiagnosticPredicate DP(Operand.isModImm()); 6266 if (DP.isMatch()) 6267 return MCTargetAsmParser::Match_Success; 6268 break; 6269 } 6270 // 'ModImmNeg' class 6271 case MCK_ModImmNeg: { 6272 DiagnosticPredicate DP(Operand.isModImmNeg()); 6273 if (DP.isMatch()) 6274 return MCTargetAsmParser::Match_Success; 6275 break; 6276 } 6277 // 'ModImmNot' class 6278 case MCK_ModImmNot: { 6279 DiagnosticPredicate DP(Operand.isModImmNot()); 6280 if (DP.isMatch()) 6281 return MCTargetAsmParser::Match_Success; 6282 break; 6283 } 6284 // 'PKHASRImm' class 6285 case MCK_PKHASRImm: { 6286 DiagnosticPredicate DP(Operand.isPKHASRImm()); 6287 if (DP.isMatch()) 6288 return MCTargetAsmParser::Match_Success; 6289 break; 6290 } 6291 // 'PKHLSLImm' class 6292 case MCK_PKHLSLImm: { 6293 DiagnosticPredicate DP(Operand.isImmediate<0,31>()); 6294 if (DP.isMatch()) 6295 return MCTargetAsmParser::Match_Success; 6296 if (DP.isNearMatch()) 6297 return ARMAsmParser::Match_PKHLSLImm; 6298 break; 6299 } 6300 // 'PostIdxImm8' class 6301 case MCK_PostIdxImm8: { 6302 DiagnosticPredicate DP(Operand.isPostIdxImm8()); 6303 if (DP.isMatch()) 6304 return MCTargetAsmParser::Match_Success; 6305 break; 6306 } 6307 // 'PostIdxImm8s4' class 6308 case MCK_PostIdxImm8s4: { 6309 DiagnosticPredicate DP(Operand.isPostIdxImm8s4()); 6310 if (DP.isMatch()) 6311 return MCTargetAsmParser::Match_Success; 6312 break; 6313 } 6314 // 'PostIdxReg' class 6315 case MCK_PostIdxReg: { 6316 DiagnosticPredicate DP(Operand.isPostIdxReg()); 6317 if (DP.isMatch()) 6318 return MCTargetAsmParser::Match_Success; 6319 break; 6320 } 6321 // 'PostIdxRegShifted' class 6322 case MCK_PostIdxRegShifted: { 6323 DiagnosticPredicate DP(Operand.isPostIdxRegShifted()); 6324 if (DP.isMatch()) 6325 return MCTargetAsmParser::Match_Success; 6326 break; 6327 } 6328 // 'ProcIFlags' class 6329 case MCK_ProcIFlags: { 6330 DiagnosticPredicate DP(Operand.isProcIFlags()); 6331 if (DP.isMatch()) 6332 return MCTargetAsmParser::Match_Success; 6333 break; 6334 } 6335 // 'RegList' class 6336 case MCK_RegList: { 6337 DiagnosticPredicate DP(Operand.isRegList()); 6338 if (DP.isMatch()) 6339 return MCTargetAsmParser::Match_Success; 6340 break; 6341 } 6342 // 'RotImm' class 6343 case MCK_RotImm: { 6344 DiagnosticPredicate DP(Operand.isRotImm()); 6345 if (DP.isMatch()) 6346 return MCTargetAsmParser::Match_Success; 6347 break; 6348 } 6349 // 'SPRRegList' class 6350 case MCK_SPRRegList: { 6351 DiagnosticPredicate DP(Operand.isSPRRegList()); 6352 if (DP.isMatch()) 6353 return MCTargetAsmParser::Match_Success; 6354 if (DP.isNearMatch()) 6355 return ARMAsmParser::Match_SPRRegList; 6356 break; 6357 } 6358 // 'SetEndImm' class 6359 case MCK_SetEndImm: { 6360 DiagnosticPredicate DP(Operand.isImmediate<0,1>()); 6361 if (DP.isMatch()) 6362 return MCTargetAsmParser::Match_Success; 6363 if (DP.isNearMatch()) 6364 return ARMAsmParser::Match_SetEndImm; 6365 break; 6366 } 6367 // 'RegShiftedImm' class 6368 case MCK_RegShiftedImm: { 6369 DiagnosticPredicate DP(Operand.isRegShiftedImm()); 6370 if (DP.isMatch()) 6371 return MCTargetAsmParser::Match_Success; 6372 break; 6373 } 6374 // 'RegShiftedReg' class 6375 case MCK_RegShiftedReg: { 6376 DiagnosticPredicate DP(Operand.isRegShiftedReg()); 6377 if (DP.isMatch()) 6378 return MCTargetAsmParser::Match_Success; 6379 break; 6380 } 6381 // 'ShifterImm' class 6382 case MCK_ShifterImm: { 6383 DiagnosticPredicate DP(Operand.isShifterImm()); 6384 if (DP.isMatch()) 6385 return MCTargetAsmParser::Match_Success; 6386 break; 6387 } 6388 // 'ThumbBranchTarget' class 6389 case MCK_ThumbBranchTarget: { 6390 DiagnosticPredicate DP(Operand.isThumbBranchTarget()); 6391 if (DP.isMatch()) 6392 return MCTargetAsmParser::Match_Success; 6393 break; 6394 } 6395 // 'ThumbMemPC' class 6396 case MCK_ThumbMemPC: { 6397 DiagnosticPredicate DP(Operand.isThumbMemPC()); 6398 if (DP.isMatch()) 6399 return MCTargetAsmParser::Match_Success; 6400 break; 6401 } 6402 // 'ThumbModImmNeg1_7' class 6403 case MCK_ThumbModImmNeg1_7: { 6404 DiagnosticPredicate DP(Operand.isThumbModImmNeg1_7()); 6405 if (DP.isMatch()) 6406 return MCTargetAsmParser::Match_Success; 6407 break; 6408 } 6409 // 'ThumbModImmNeg8_255' class 6410 case MCK_ThumbModImmNeg8_255: { 6411 DiagnosticPredicate DP(Operand.isThumbModImmNeg8_255()); 6412 if (DP.isMatch()) 6413 return MCTargetAsmParser::Match_Success; 6414 break; 6415 } 6416 // 'ImmThumbSR' class 6417 case MCK_ImmThumbSR: { 6418 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 6419 if (DP.isMatch()) 6420 return MCTargetAsmParser::Match_Success; 6421 if (DP.isNearMatch()) 6422 return ARMAsmParser::Match_ImmThumbSR; 6423 break; 6424 } 6425 // 'TraceSyncBarrierOpt' class 6426 case MCK_TraceSyncBarrierOpt: { 6427 DiagnosticPredicate DP(Operand.isTraceSyncBarrierOpt()); 6428 if (DP.isMatch()) 6429 return MCTargetAsmParser::Match_Success; 6430 break; 6431 } 6432 // 'UnsignedOffset_b8s2' class 6433 case MCK_UnsignedOffset_b8s2: { 6434 DiagnosticPredicate DP(Operand.isUnsignedOffset<8, 2>()); 6435 if (DP.isMatch()) 6436 return MCTargetAsmParser::Match_Success; 6437 break; 6438 } 6439 // 'VecListDPairAllLanes' class 6440 case MCK_VecListDPairAllLanes: { 6441 DiagnosticPredicate DP(Operand.isVecListDPairAllLanes()); 6442 if (DP.isMatch()) 6443 return MCTargetAsmParser::Match_Success; 6444 break; 6445 } 6446 // 'VecListDPair' class 6447 case MCK_VecListDPair: { 6448 DiagnosticPredicate DP(Operand.isVecListDPair()); 6449 if (DP.isMatch()) 6450 return MCTargetAsmParser::Match_Success; 6451 break; 6452 } 6453 // 'VecListDPairSpacedAllLanes' class 6454 case MCK_VecListDPairSpacedAllLanes: { 6455 DiagnosticPredicate DP(Operand.isVecListDPairSpacedAllLanes()); 6456 if (DP.isMatch()) 6457 return MCTargetAsmParser::Match_Success; 6458 break; 6459 } 6460 // 'VecListDPairSpaced' class 6461 case MCK_VecListDPairSpaced: { 6462 DiagnosticPredicate DP(Operand.isVecListDPairSpaced()); 6463 if (DP.isMatch()) 6464 return MCTargetAsmParser::Match_Success; 6465 break; 6466 } 6467 // 'VecListFourDAllLanes' class 6468 case MCK_VecListFourDAllLanes: { 6469 DiagnosticPredicate DP(Operand.isVecListFourDAllLanes()); 6470 if (DP.isMatch()) 6471 return MCTargetAsmParser::Match_Success; 6472 break; 6473 } 6474 // 'VecListFourD' class 6475 case MCK_VecListFourD: { 6476 DiagnosticPredicate DP(Operand.isVecListFourD()); 6477 if (DP.isMatch()) 6478 return MCTargetAsmParser::Match_Success; 6479 break; 6480 } 6481 // 'VecListFourDByteIndexed' class 6482 case MCK_VecListFourDByteIndexed: { 6483 DiagnosticPredicate DP(Operand.isVecListFourDByteIndexed()); 6484 if (DP.isMatch()) 6485 return MCTargetAsmParser::Match_Success; 6486 break; 6487 } 6488 // 'VecListFourDHWordIndexed' class 6489 case MCK_VecListFourDHWordIndexed: { 6490 DiagnosticPredicate DP(Operand.isVecListFourDHWordIndexed()); 6491 if (DP.isMatch()) 6492 return MCTargetAsmParser::Match_Success; 6493 break; 6494 } 6495 // 'VecListFourDWordIndexed' class 6496 case MCK_VecListFourDWordIndexed: { 6497 DiagnosticPredicate DP(Operand.isVecListFourDWordIndexed()); 6498 if (DP.isMatch()) 6499 return MCTargetAsmParser::Match_Success; 6500 break; 6501 } 6502 // 'VecListFourQAllLanes' class 6503 case MCK_VecListFourQAllLanes: { 6504 DiagnosticPredicate DP(Operand.isVecListFourQAllLanes()); 6505 if (DP.isMatch()) 6506 return MCTargetAsmParser::Match_Success; 6507 break; 6508 } 6509 // 'VecListFourQ' class 6510 case MCK_VecListFourQ: { 6511 DiagnosticPredicate DP(Operand.isVecListFourQ()); 6512 if (DP.isMatch()) 6513 return MCTargetAsmParser::Match_Success; 6514 break; 6515 } 6516 // 'VecListFourQHWordIndexed' class 6517 case MCK_VecListFourQHWordIndexed: { 6518 DiagnosticPredicate DP(Operand.isVecListFourQHWordIndexed()); 6519 if (DP.isMatch()) 6520 return MCTargetAsmParser::Match_Success; 6521 break; 6522 } 6523 // 'VecListFourQWordIndexed' class 6524 case MCK_VecListFourQWordIndexed: { 6525 DiagnosticPredicate DP(Operand.isVecListFourQWordIndexed()); 6526 if (DP.isMatch()) 6527 return MCTargetAsmParser::Match_Success; 6528 break; 6529 } 6530 // 'VecListOneDAllLanes' class 6531 case MCK_VecListOneDAllLanes: { 6532 DiagnosticPredicate DP(Operand.isVecListOneDAllLanes()); 6533 if (DP.isMatch()) 6534 return MCTargetAsmParser::Match_Success; 6535 break; 6536 } 6537 // 'VecListOneD' class 6538 case MCK_VecListOneD: { 6539 DiagnosticPredicate DP(Operand.isVecListOneD()); 6540 if (DP.isMatch()) 6541 return MCTargetAsmParser::Match_Success; 6542 break; 6543 } 6544 // 'VecListOneDByteIndexed' class 6545 case MCK_VecListOneDByteIndexed: { 6546 DiagnosticPredicate DP(Operand.isVecListOneDByteIndexed()); 6547 if (DP.isMatch()) 6548 return MCTargetAsmParser::Match_Success; 6549 break; 6550 } 6551 // 'VecListOneDHWordIndexed' class 6552 case MCK_VecListOneDHWordIndexed: { 6553 DiagnosticPredicate DP(Operand.isVecListOneDHWordIndexed()); 6554 if (DP.isMatch()) 6555 return MCTargetAsmParser::Match_Success; 6556 break; 6557 } 6558 // 'VecListOneDWordIndexed' class 6559 case MCK_VecListOneDWordIndexed: { 6560 DiagnosticPredicate DP(Operand.isVecListOneDWordIndexed()); 6561 if (DP.isMatch()) 6562 return MCTargetAsmParser::Match_Success; 6563 break; 6564 } 6565 // 'VecListThreeDAllLanes' class 6566 case MCK_VecListThreeDAllLanes: { 6567 DiagnosticPredicate DP(Operand.isVecListThreeDAllLanes()); 6568 if (DP.isMatch()) 6569 return MCTargetAsmParser::Match_Success; 6570 break; 6571 } 6572 // 'VecListThreeD' class 6573 case MCK_VecListThreeD: { 6574 DiagnosticPredicate DP(Operand.isVecListThreeD()); 6575 if (DP.isMatch()) 6576 return MCTargetAsmParser::Match_Success; 6577 break; 6578 } 6579 // 'VecListThreeDByteIndexed' class 6580 case MCK_VecListThreeDByteIndexed: { 6581 DiagnosticPredicate DP(Operand.isVecListThreeDByteIndexed()); 6582 if (DP.isMatch()) 6583 return MCTargetAsmParser::Match_Success; 6584 break; 6585 } 6586 // 'VecListThreeDHWordIndexed' class 6587 case MCK_VecListThreeDHWordIndexed: { 6588 DiagnosticPredicate DP(Operand.isVecListThreeDHWordIndexed()); 6589 if (DP.isMatch()) 6590 return MCTargetAsmParser::Match_Success; 6591 break; 6592 } 6593 // 'VecListThreeDWordIndexed' class 6594 case MCK_VecListThreeDWordIndexed: { 6595 DiagnosticPredicate DP(Operand.isVecListThreeDWordIndexed()); 6596 if (DP.isMatch()) 6597 return MCTargetAsmParser::Match_Success; 6598 break; 6599 } 6600 // 'VecListThreeQAllLanes' class 6601 case MCK_VecListThreeQAllLanes: { 6602 DiagnosticPredicate DP(Operand.isVecListThreeQAllLanes()); 6603 if (DP.isMatch()) 6604 return MCTargetAsmParser::Match_Success; 6605 break; 6606 } 6607 // 'VecListThreeQ' class 6608 case MCK_VecListThreeQ: { 6609 DiagnosticPredicate DP(Operand.isVecListThreeQ()); 6610 if (DP.isMatch()) 6611 return MCTargetAsmParser::Match_Success; 6612 break; 6613 } 6614 // 'VecListThreeQHWordIndexed' class 6615 case MCK_VecListThreeQHWordIndexed: { 6616 DiagnosticPredicate DP(Operand.isVecListThreeQHWordIndexed()); 6617 if (DP.isMatch()) 6618 return MCTargetAsmParser::Match_Success; 6619 break; 6620 } 6621 // 'VecListThreeQWordIndexed' class 6622 case MCK_VecListThreeQWordIndexed: { 6623 DiagnosticPredicate DP(Operand.isVecListThreeQWordIndexed()); 6624 if (DP.isMatch()) 6625 return MCTargetAsmParser::Match_Success; 6626 break; 6627 } 6628 // 'VecListTwoDByteIndexed' class 6629 case MCK_VecListTwoDByteIndexed: { 6630 DiagnosticPredicate DP(Operand.isVecListTwoDByteIndexed()); 6631 if (DP.isMatch()) 6632 return MCTargetAsmParser::Match_Success; 6633 break; 6634 } 6635 // 'VecListTwoDHWordIndexed' class 6636 case MCK_VecListTwoDHWordIndexed: { 6637 DiagnosticPredicate DP(Operand.isVecListTwoDHWordIndexed()); 6638 if (DP.isMatch()) 6639 return MCTargetAsmParser::Match_Success; 6640 break; 6641 } 6642 // 'VecListTwoDWordIndexed' class 6643 case MCK_VecListTwoDWordIndexed: { 6644 DiagnosticPredicate DP(Operand.isVecListTwoDWordIndexed()); 6645 if (DP.isMatch()) 6646 return MCTargetAsmParser::Match_Success; 6647 break; 6648 } 6649 // 'VecListTwoQHWordIndexed' class 6650 case MCK_VecListTwoQHWordIndexed: { 6651 DiagnosticPredicate DP(Operand.isVecListTwoQHWordIndexed()); 6652 if (DP.isMatch()) 6653 return MCTargetAsmParser::Match_Success; 6654 break; 6655 } 6656 // 'VecListTwoQWordIndexed' class 6657 case MCK_VecListTwoQWordIndexed: { 6658 DiagnosticPredicate DP(Operand.isVecListTwoQWordIndexed()); 6659 if (DP.isMatch()) 6660 return MCTargetAsmParser::Match_Success; 6661 break; 6662 } 6663 // 'VectorIndex16' class 6664 case MCK_VectorIndex16: { 6665 DiagnosticPredicate DP(Operand.isVectorIndex16()); 6666 if (DP.isMatch()) 6667 return MCTargetAsmParser::Match_Success; 6668 break; 6669 } 6670 // 'VectorIndex32' class 6671 case MCK_VectorIndex32: { 6672 DiagnosticPredicate DP(Operand.isVectorIndex32()); 6673 if (DP.isMatch()) 6674 return MCTargetAsmParser::Match_Success; 6675 break; 6676 } 6677 // 'VectorIndex64' class 6678 case MCK_VectorIndex64: { 6679 DiagnosticPredicate DP(Operand.isVectorIndex64()); 6680 if (DP.isMatch()) 6681 return MCTargetAsmParser::Match_Success; 6682 break; 6683 } 6684 // 'VectorIndex8' class 6685 case MCK_VectorIndex8: { 6686 DiagnosticPredicate DP(Operand.isVectorIndex8()); 6687 if (DP.isMatch()) 6688 return MCTargetAsmParser::Match_Success; 6689 break; 6690 } 6691 // 'MemTBB' class 6692 case MCK_MemTBB: { 6693 DiagnosticPredicate DP(Operand.isMemTBB()); 6694 if (DP.isMatch()) 6695 return MCTargetAsmParser::Match_Success; 6696 break; 6697 } 6698 // 'MemTBH' class 6699 case MCK_MemTBH: { 6700 DiagnosticPredicate DP(Operand.isMemTBH()); 6701 if (DP.isMatch()) 6702 return MCTargetAsmParser::Match_Success; 6703 break; 6704 } 6705 // 'ComplexRotationEven' class 6706 case MCK_ComplexRotationEven: { 6707 DiagnosticPredicate DP(Operand.isComplexRotation<90, 0>()); 6708 if (DP.isMatch()) 6709 return MCTargetAsmParser::Match_Success; 6710 if (DP.isNearMatch()) 6711 return ARMAsmParser::Match_ComplexRotationEven; 6712 break; 6713 } 6714 // 'ComplexRotationOdd' class 6715 case MCK_ComplexRotationOdd: { 6716 DiagnosticPredicate DP(Operand.isComplexRotation<180, 90>()); 6717 if (DP.isMatch()) 6718 return MCTargetAsmParser::Match_Success; 6719 if (DP.isNearMatch()) 6720 return ARMAsmParser::Match_ComplexRotationOdd; 6721 break; 6722 } 6723 // 'NEONi16vmovi8Replicate' class 6724 case MCK_NEONi16vmovi8Replicate: { 6725 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 16>()); 6726 if (DP.isMatch()) 6727 return MCTargetAsmParser::Match_Success; 6728 break; 6729 } 6730 // 'NEONi16invi8Replicate' class 6731 case MCK_NEONi16invi8Replicate: { 6732 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 16>()); 6733 if (DP.isMatch()) 6734 return MCTargetAsmParser::Match_Success; 6735 break; 6736 } 6737 // 'NEONi32vmovi8Replicate' class 6738 case MCK_NEONi32vmovi8Replicate: { 6739 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 32>()); 6740 if (DP.isMatch()) 6741 return MCTargetAsmParser::Match_Success; 6742 break; 6743 } 6744 // 'NEONi32invi8Replicate' class 6745 case MCK_NEONi32invi8Replicate: { 6746 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 32>()); 6747 if (DP.isMatch()) 6748 return MCTargetAsmParser::Match_Success; 6749 break; 6750 } 6751 // 'NEONi64vmovi8Replicate' class 6752 case MCK_NEONi64vmovi8Replicate: { 6753 DiagnosticPredicate DP(Operand.isNEONmovReplicate<8, 64>()); 6754 if (DP.isMatch()) 6755 return MCTargetAsmParser::Match_Success; 6756 break; 6757 } 6758 // 'NEONi64invi8Replicate' class 6759 case MCK_NEONi64invi8Replicate: { 6760 DiagnosticPredicate DP(Operand.isNEONinvReplicate<8, 64>()); 6761 if (DP.isMatch()) 6762 return MCTargetAsmParser::Match_Success; 6763 break; 6764 } 6765 // 'NEONi32vmovi16Replicate' class 6766 case MCK_NEONi32vmovi16Replicate: { 6767 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 32>()); 6768 if (DP.isMatch()) 6769 return MCTargetAsmParser::Match_Success; 6770 break; 6771 } 6772 // 'NEONi64vmovi16Replicate' class 6773 case MCK_NEONi64vmovi16Replicate: { 6774 DiagnosticPredicate DP(Operand.isNEONmovReplicate<16, 64>()); 6775 if (DP.isMatch()) 6776 return MCTargetAsmParser::Match_Success; 6777 break; 6778 } 6779 // 'NEONi64vmovi32Replicate' class 6780 case MCK_NEONi64vmovi32Replicate: { 6781 DiagnosticPredicate DP(Operand.isNEONmovReplicate<32, 64>()); 6782 if (DP.isMatch()) 6783 return MCTargetAsmParser::Match_Success; 6784 break; 6785 } 6786 // 'ConstPoolAsmImm' class 6787 case MCK_ConstPoolAsmImm: { 6788 DiagnosticPredicate DP(Operand.isConstPoolAsmImm()); 6789 if (DP.isMatch()) 6790 return MCTargetAsmParser::Match_Success; 6791 break; 6792 } 6793 // 'FBits16' class 6794 case MCK_FBits16: { 6795 DiagnosticPredicate DP(Operand.isFBits16()); 6796 if (DP.isMatch()) 6797 return MCTargetAsmParser::Match_Success; 6798 break; 6799 } 6800 // 'FBits32' class 6801 case MCK_FBits32: { 6802 DiagnosticPredicate DP(Operand.isFBits32()); 6803 if (DP.isMatch()) 6804 return MCTargetAsmParser::Match_Success; 6805 break; 6806 } 6807 // 'Imm0_4095' class 6808 case MCK_Imm0_4095: { 6809 DiagnosticPredicate DP(Operand.isImmediate<0,4095>()); 6810 if (DP.isMatch()) 6811 return MCTargetAsmParser::Match_Success; 6812 if (DP.isNearMatch()) 6813 return ARMAsmParser::Match_Imm0_4095; 6814 break; 6815 } 6816 // 'Imm0_4095Neg' class 6817 case MCK_Imm0_4095Neg: { 6818 DiagnosticPredicate DP(Operand.isImm0_4095Neg()); 6819 if (DP.isMatch()) 6820 return MCTargetAsmParser::Match_Success; 6821 break; 6822 } 6823 // 'ITMask' class 6824 case MCK_ITMask: { 6825 DiagnosticPredicate DP(Operand.isITMask()); 6826 if (DP.isMatch()) 6827 return MCTargetAsmParser::Match_Success; 6828 break; 6829 } 6830 // 'ITCondCode' class 6831 case MCK_ITCondCode: { 6832 DiagnosticPredicate DP(Operand.isITCondCode()); 6833 if (DP.isMatch()) 6834 return MCTargetAsmParser::Match_Success; 6835 break; 6836 } 6837 // 'NEONi16splat' class 6838 case MCK_NEONi16splat: { 6839 DiagnosticPredicate DP(Operand.isNEONi16splat()); 6840 if (DP.isMatch()) 6841 return MCTargetAsmParser::Match_Success; 6842 break; 6843 } 6844 // 'NEONi32splat' class 6845 case MCK_NEONi32splat: { 6846 DiagnosticPredicate DP(Operand.isNEONi32splat()); 6847 if (DP.isMatch()) 6848 return MCTargetAsmParser::Match_Success; 6849 break; 6850 } 6851 // 'NEONi64splat' class 6852 case MCK_NEONi64splat: { 6853 DiagnosticPredicate DP(Operand.isNEONi64splat()); 6854 if (DP.isMatch()) 6855 return MCTargetAsmParser::Match_Success; 6856 break; 6857 } 6858 // 'NEONi8splat' class 6859 case MCK_NEONi8splat: { 6860 DiagnosticPredicate DP(Operand.isNEONi8splat()); 6861 if (DP.isMatch()) 6862 return MCTargetAsmParser::Match_Success; 6863 break; 6864 } 6865 // 'NEONi16splatNot' class 6866 case MCK_NEONi16splatNot: { 6867 DiagnosticPredicate DP(Operand.isNEONi16splatNot()); 6868 if (DP.isMatch()) 6869 return MCTargetAsmParser::Match_Success; 6870 break; 6871 } 6872 // 'NEONi32splatNot' class 6873 case MCK_NEONi32splatNot: { 6874 DiagnosticPredicate DP(Operand.isNEONi32splatNot()); 6875 if (DP.isMatch()) 6876 return MCTargetAsmParser::Match_Success; 6877 break; 6878 } 6879 // 'NEONi32vmov' class 6880 case MCK_NEONi32vmov: { 6881 DiagnosticPredicate DP(Operand.isNEONi32vmov()); 6882 if (DP.isMatch()) 6883 return MCTargetAsmParser::Match_Success; 6884 break; 6885 } 6886 // 'NEONi32vmovNeg' class 6887 case MCK_NEONi32vmovNeg: { 6888 DiagnosticPredicate DP(Operand.isNEONi32vmovNeg()); 6889 if (DP.isMatch()) 6890 return MCTargetAsmParser::Match_Success; 6891 break; 6892 } 6893 // 'ShrImm16' class 6894 case MCK_ShrImm16: { 6895 DiagnosticPredicate DP(Operand.isImmediate<1,16>()); 6896 if (DP.isMatch()) 6897 return MCTargetAsmParser::Match_Success; 6898 if (DP.isNearMatch()) 6899 return ARMAsmParser::Match_ShrImm16; 6900 break; 6901 } 6902 // 'ShrImm32' class 6903 case MCK_ShrImm32: { 6904 DiagnosticPredicate DP(Operand.isImmediate<1,32>()); 6905 if (DP.isMatch()) 6906 return MCTargetAsmParser::Match_Success; 6907 if (DP.isNearMatch()) 6908 return ARMAsmParser::Match_ShrImm32; 6909 break; 6910 } 6911 // 'ShrImm64' class 6912 case MCK_ShrImm64: { 6913 DiagnosticPredicate DP(Operand.isImmediate<1,64>()); 6914 if (DP.isMatch()) 6915 return MCTargetAsmParser::Match_Success; 6916 if (DP.isNearMatch()) 6917 return ARMAsmParser::Match_ShrImm64; 6918 break; 6919 } 6920 // 'ShrImm8' class 6921 case MCK_ShrImm8: { 6922 DiagnosticPredicate DP(Operand.isImmediate<1,8>()); 6923 if (DP.isMatch()) 6924 return MCTargetAsmParser::Match_Success; 6925 if (DP.isNearMatch()) 6926 return ARMAsmParser::Match_ShrImm8; 6927 break; 6928 } 6929 // 'T2SOImm' class 6930 case MCK_T2SOImm: { 6931 DiagnosticPredicate DP(Operand.isT2SOImm()); 6932 if (DP.isMatch()) 6933 return MCTargetAsmParser::Match_Success; 6934 break; 6935 } 6936 // 'T2SOImmNeg' class 6937 case MCK_T2SOImmNeg: { 6938 DiagnosticPredicate DP(Operand.isT2SOImmNeg()); 6939 if (DP.isMatch()) 6940 return MCTargetAsmParser::Match_Success; 6941 break; 6942 } 6943 // 'T2SOImmNot' class 6944 case MCK_T2SOImmNot: { 6945 DiagnosticPredicate DP(Operand.isT2SOImmNot()); 6946 if (DP.isMatch()) 6947 return MCTargetAsmParser::Match_Success; 6948 break; 6949 } 6950 // 'MemUImm12Offset' class 6951 case MCK_MemUImm12Offset: { 6952 DiagnosticPredicate DP(Operand.isMemUImm12Offset()); 6953 if (DP.isMatch()) 6954 return MCTargetAsmParser::Match_Success; 6955 break; 6956 } 6957 // 'T2MemRegOffset' class 6958 case MCK_T2MemRegOffset: { 6959 DiagnosticPredicate DP(Operand.isT2MemRegOffset()); 6960 if (DP.isMatch()) 6961 return MCTargetAsmParser::Match_Success; 6962 break; 6963 } 6964 // 'Imm8s4' class 6965 case MCK_Imm8s4: { 6966 DiagnosticPredicate DP(Operand.isImm8s4()); 6967 if (DP.isMatch()) 6968 return MCTargetAsmParser::Match_Success; 6969 break; 6970 } 6971 // 'MemPCRelImm12' class 6972 case MCK_MemPCRelImm12: { 6973 DiagnosticPredicate DP(Operand.isMemPCRelImm12()); 6974 if (DP.isMatch()) 6975 return MCTargetAsmParser::Match_Success; 6976 break; 6977 } 6978 // 'MemThumbRIs1' class 6979 case MCK_MemThumbRIs1: { 6980 DiagnosticPredicate DP(Operand.isMemThumbRIs1()); 6981 if (DP.isMatch()) 6982 return MCTargetAsmParser::Match_Success; 6983 break; 6984 } 6985 // 'MemThumbRIs2' class 6986 case MCK_MemThumbRIs2: { 6987 DiagnosticPredicate DP(Operand.isMemThumbRIs2()); 6988 if (DP.isMatch()) 6989 return MCTargetAsmParser::Match_Success; 6990 break; 6991 } 6992 // 'MemThumbRIs4' class 6993 case MCK_MemThumbRIs4: { 6994 DiagnosticPredicate DP(Operand.isMemThumbRIs4()); 6995 if (DP.isMatch()) 6996 return MCTargetAsmParser::Match_Success; 6997 break; 6998 } 6999 // 'MemThumbRR' class 7000 case MCK_MemThumbRR: { 7001 DiagnosticPredicate DP(Operand.isMemThumbRR()); 7002 if (DP.isMatch()) 7003 return MCTargetAsmParser::Match_Success; 7004 break; 7005 } 7006 // 'MemThumbSPI' class 7007 case MCK_MemThumbSPI: { 7008 DiagnosticPredicate DP(Operand.isMemThumbSPI()); 7009 if (DP.isMatch()) 7010 return MCTargetAsmParser::Match_Success; 7011 break; 7012 } 7013 // 'Imm0_1020s4' class 7014 case MCK_Imm0_1020s4: { 7015 DiagnosticPredicate DP(Operand.isImm0_1020s4()); 7016 if (DP.isMatch()) 7017 return MCTargetAsmParser::Match_Success; 7018 break; 7019 } 7020 // 'Imm0_508s4' class 7021 case MCK_Imm0_508s4: { 7022 DiagnosticPredicate DP(Operand.isImm0_508s4()); 7023 if (DP.isMatch()) 7024 return MCTargetAsmParser::Match_Success; 7025 break; 7026 } 7027 // 'Imm0_508s4Neg' class 7028 case MCK_Imm0_508s4Neg: { 7029 DiagnosticPredicate DP(Operand.isImm0_508s4Neg()); 7030 if (DP.isMatch()) 7031 return MCTargetAsmParser::Match_Success; 7032 break; 7033 } 7034 } // end switch (Kind) 7035 7036 if (Operand.isReg()) { 7037 MatchClassKind OpKind; 7038 switch (Operand.getReg()) { 7039 default: OpKind = InvalidMatchClass; break; 7040 case ARM::R0: OpKind = MCK_Reg0; break; 7041 case ARM::R1: OpKind = MCK_Reg0; break; 7042 case ARM::R2: OpKind = MCK_Reg0; break; 7043 case ARM::R3: OpKind = MCK_Reg0; break; 7044 case ARM::R4: OpKind = MCK_tGPR; break; 7045 case ARM::R5: OpKind = MCK_tGPR; break; 7046 case ARM::R6: OpKind = MCK_tGPR; break; 7047 case ARM::R7: OpKind = MCK_tGPR; break; 7048 case ARM::R8: OpKind = MCK_Reg10; break; 7049 case ARM::R9: OpKind = MCK_Reg10; break; 7050 case ARM::R10: OpKind = MCK_Reg10; break; 7051 case ARM::R11: OpKind = MCK_Reg10; break; 7052 case ARM::R12: OpKind = MCK_Reg11; break; 7053 case ARM::SP: OpKind = MCK_GPRsp; break; 7054 case ARM::LR: OpKind = MCK_LR; break; 7055 case ARM::PC: OpKind = MCK_PC; break; 7056 case ARM::S0: OpKind = MCK_SPR_8; break; 7057 case ARM::S1: OpKind = MCK_SPR_8; break; 7058 case ARM::S2: OpKind = MCK_SPR_8; break; 7059 case ARM::S3: OpKind = MCK_SPR_8; break; 7060 case ARM::S4: OpKind = MCK_SPR_8; break; 7061 case ARM::S5: OpKind = MCK_SPR_8; break; 7062 case ARM::S6: OpKind = MCK_SPR_8; break; 7063 case ARM::S7: OpKind = MCK_SPR_8; break; 7064 case ARM::S8: OpKind = MCK_SPR_8; break; 7065 case ARM::S9: OpKind = MCK_SPR_8; break; 7066 case ARM::S10: OpKind = MCK_SPR_8; break; 7067 case ARM::S11: OpKind = MCK_SPR_8; break; 7068 case ARM::S12: OpKind = MCK_SPR_8; break; 7069 case ARM::S13: OpKind = MCK_SPR_8; break; 7070 case ARM::S14: OpKind = MCK_SPR_8; break; 7071 case ARM::S15: OpKind = MCK_SPR_8; break; 7072 case ARM::S16: OpKind = MCK_HPR; break; 7073 case ARM::S17: OpKind = MCK_HPR; break; 7074 case ARM::S18: OpKind = MCK_HPR; break; 7075 case ARM::S19: OpKind = MCK_HPR; break; 7076 case ARM::S20: OpKind = MCK_HPR; break; 7077 case ARM::S21: OpKind = MCK_HPR; break; 7078 case ARM::S22: OpKind = MCK_HPR; break; 7079 case ARM::S23: OpKind = MCK_HPR; break; 7080 case ARM::S24: OpKind = MCK_HPR; break; 7081 case ARM::S25: OpKind = MCK_HPR; break; 7082 case ARM::S26: OpKind = MCK_HPR; break; 7083 case ARM::S27: OpKind = MCK_HPR; break; 7084 case ARM::S28: OpKind = MCK_HPR; break; 7085 case ARM::S29: OpKind = MCK_HPR; break; 7086 case ARM::S30: OpKind = MCK_HPR; break; 7087 case ARM::S31: OpKind = MCK_HPR; break; 7088 case ARM::D0: OpKind = MCK_DPR_8; break; 7089 case ARM::D1: OpKind = MCK_DPR_8; break; 7090 case ARM::D2: OpKind = MCK_DPR_8; break; 7091 case ARM::D3: OpKind = MCK_DPR_8; break; 7092 case ARM::D4: OpKind = MCK_DPR_8; break; 7093 case ARM::D5: OpKind = MCK_DPR_8; break; 7094 case ARM::D6: OpKind = MCK_DPR_8; break; 7095 case ARM::D7: OpKind = MCK_DPR_8; break; 7096 case ARM::D8: OpKind = MCK_DPR_VFP2; break; 7097 case ARM::D9: OpKind = MCK_DPR_VFP2; break; 7098 case ARM::D10: OpKind = MCK_DPR_VFP2; break; 7099 case ARM::D11: OpKind = MCK_DPR_VFP2; break; 7100 case ARM::D12: OpKind = MCK_DPR_VFP2; break; 7101 case ARM::D13: OpKind = MCK_DPR_VFP2; break; 7102 case ARM::D14: OpKind = MCK_DPR_VFP2; break; 7103 case ARM::D15: OpKind = MCK_DPR_VFP2; break; 7104 case ARM::D16: OpKind = MCK_DPR; break; 7105 case ARM::D17: OpKind = MCK_DPR; break; 7106 case ARM::D18: OpKind = MCK_DPR; break; 7107 case ARM::D19: OpKind = MCK_DPR; break; 7108 case ARM::D20: OpKind = MCK_DPR; break; 7109 case ARM::D21: OpKind = MCK_DPR; break; 7110 case ARM::D22: OpKind = MCK_DPR; break; 7111 case ARM::D23: OpKind = MCK_DPR; break; 7112 case ARM::D24: OpKind = MCK_DPR; break; 7113 case ARM::D25: OpKind = MCK_DPR; break; 7114 case ARM::D26: OpKind = MCK_DPR; break; 7115 case ARM::D27: OpKind = MCK_DPR; break; 7116 case ARM::D28: OpKind = MCK_DPR; break; 7117 case ARM::D29: OpKind = MCK_DPR; break; 7118 case ARM::D30: OpKind = MCK_DPR; break; 7119 case ARM::D31: OpKind = MCK_DPR; break; 7120 case ARM::Q0: OpKind = MCK_QPR_8; break; 7121 case ARM::Q1: OpKind = MCK_QPR_8; break; 7122 case ARM::Q2: OpKind = MCK_QPR_8; break; 7123 case ARM::Q3: OpKind = MCK_QPR_8; break; 7124 case ARM::Q4: OpKind = MCK_QPR_VFP2; break; 7125 case ARM::Q5: OpKind = MCK_QPR_VFP2; break; 7126 case ARM::Q6: OpKind = MCK_QPR_VFP2; break; 7127 case ARM::Q7: OpKind = MCK_QPR_VFP2; break; 7128 case ARM::Q8: OpKind = MCK_QPR; break; 7129 case ARM::Q9: OpKind = MCK_QPR; break; 7130 case ARM::Q10: OpKind = MCK_QPR; break; 7131 case ARM::Q11: OpKind = MCK_QPR; break; 7132 case ARM::Q12: OpKind = MCK_QPR; break; 7133 case ARM::Q13: OpKind = MCK_QPR; break; 7134 case ARM::Q14: OpKind = MCK_QPR; break; 7135 case ARM::Q15: OpKind = MCK_QPR; break; 7136 case ARM::CPSR: OpKind = MCK_CCR; break; 7137 case ARM::APSR: OpKind = MCK_APSR; break; 7138 case ARM::APSR_NZCV: OpKind = MCK_APSR_NZCV; break; 7139 case ARM::SPSR: OpKind = MCK_SPSR; break; 7140 case ARM::FPSCR: OpKind = MCK_FPSCR; break; 7141 case ARM::FPSID: OpKind = MCK_FPSID; break; 7142 case ARM::MVFR2: OpKind = MCK_MVFR2; break; 7143 case ARM::MVFR1: OpKind = MCK_MVFR1; break; 7144 case ARM::MVFR0: OpKind = MCK_MVFR0; break; 7145 case ARM::FPEXC: OpKind = MCK_FPEXC; break; 7146 case ARM::FPINST: OpKind = MCK_FPINST; break; 7147 case ARM::FPINST2: OpKind = MCK_FPINST2; break; 7148 case ARM::D0_D2: OpKind = MCK_Reg40; break; 7149 case ARM::D1_D3: OpKind = MCK_Reg40; break; 7150 case ARM::D2_D4: OpKind = MCK_Reg40; break; 7151 case ARM::D3_D5: OpKind = MCK_Reg40; break; 7152 case ARM::D4_D6: OpKind = MCK_Reg40; break; 7153 case ARM::D5_D7: OpKind = MCK_Reg40; break; 7154 case ARM::D6_D8: OpKind = MCK_Reg41; break; 7155 case ARM::D7_D9: OpKind = MCK_Reg41; break; 7156 case ARM::D8_D10: OpKind = MCK_Reg42; break; 7157 case ARM::D9_D11: OpKind = MCK_Reg42; break; 7158 case ARM::D10_D12: OpKind = MCK_Reg42; break; 7159 case ARM::D11_D13: OpKind = MCK_Reg42; break; 7160 case ARM::D12_D14: OpKind = MCK_Reg42; break; 7161 case ARM::D13_D15: OpKind = MCK_Reg42; break; 7162 case ARM::D14_D16: OpKind = MCK_Reg43; break; 7163 case ARM::D15_D17: OpKind = MCK_Reg43; break; 7164 case ARM::D16_D18: OpKind = MCK_DPairSpc; break; 7165 case ARM::D17_D19: OpKind = MCK_DPairSpc; break; 7166 case ARM::D18_D20: OpKind = MCK_DPairSpc; break; 7167 case ARM::D19_D21: OpKind = MCK_DPairSpc; break; 7168 case ARM::D20_D22: OpKind = MCK_DPairSpc; break; 7169 case ARM::D21_D23: OpKind = MCK_DPairSpc; break; 7170 case ARM::D22_D24: OpKind = MCK_DPairSpc; break; 7171 case ARM::D23_D25: OpKind = MCK_DPairSpc; break; 7172 case ARM::D24_D26: OpKind = MCK_DPairSpc; break; 7173 case ARM::D25_D27: OpKind = MCK_DPairSpc; break; 7174 case ARM::D26_D28: OpKind = MCK_DPairSpc; break; 7175 case ARM::D27_D29: OpKind = MCK_DPairSpc; break; 7176 case ARM::D28_D30: OpKind = MCK_DPairSpc; break; 7177 case ARM::D29_D31: OpKind = MCK_DPairSpc; break; 7178 case ARM::Q0_Q1: OpKind = MCK_Reg45; break; 7179 case ARM::Q1_Q2: OpKind = MCK_Reg45; break; 7180 case ARM::Q2_Q3: OpKind = MCK_Reg45; break; 7181 case ARM::Q3_Q4: OpKind = MCK_Reg46; break; 7182 case ARM::Q4_Q5: OpKind = MCK_Reg47; break; 7183 case ARM::Q5_Q6: OpKind = MCK_Reg47; break; 7184 case ARM::Q6_Q7: OpKind = MCK_Reg47; break; 7185 case ARM::Q7_Q8: OpKind = MCK_Reg48; break; 7186 case ARM::Q8_Q9: OpKind = MCK_QQPR; break; 7187 case ARM::Q9_Q10: OpKind = MCK_QQPR; break; 7188 case ARM::Q10_Q11: OpKind = MCK_QQPR; break; 7189 case ARM::Q11_Q12: OpKind = MCK_QQPR; break; 7190 case ARM::Q12_Q13: OpKind = MCK_QQPR; break; 7191 case ARM::Q13_Q14: OpKind = MCK_QQPR; break; 7192 case ARM::Q14_Q15: OpKind = MCK_QQPR; break; 7193 case ARM::Q0_Q1_Q2_Q3: OpKind = MCK_Reg59; break; 7194 case ARM::Q1_Q2_Q3_Q4: OpKind = MCK_Reg60; break; 7195 case ARM::Q2_Q3_Q4_Q5: OpKind = MCK_Reg61; break; 7196 case ARM::Q3_Q4_Q5_Q6: OpKind = MCK_Reg62; break; 7197 case ARM::Q4_Q5_Q6_Q7: OpKind = MCK_Reg63; break; 7198 case ARM::Q5_Q6_Q7_Q8: OpKind = MCK_Reg64; break; 7199 case ARM::Q6_Q7_Q8_Q9: OpKind = MCK_Reg65; break; 7200 case ARM::Q7_Q8_Q9_Q10: OpKind = MCK_Reg66; break; 7201 case ARM::Q8_Q9_Q10_Q11: OpKind = MCK_QQQQPR; break; 7202 case ARM::Q9_Q10_Q11_Q12: OpKind = MCK_QQQQPR; break; 7203 case ARM::Q10_Q11_Q12_Q13: OpKind = MCK_QQQQPR; break; 7204 case ARM::Q11_Q12_Q13_Q14: OpKind = MCK_QQQQPR; break; 7205 case ARM::Q12_Q13_Q14_Q15: OpKind = MCK_QQQQPR; break; 7206 case ARM::R0_R1: OpKind = MCK_Reg68; break; 7207 case ARM::R2_R3: OpKind = MCK_Reg68; break; 7208 case ARM::R4_R5: OpKind = MCK_Reg69; break; 7209 case ARM::R6_R7: OpKind = MCK_Reg69; break; 7210 case ARM::R8_R9: OpKind = MCK_Reg73; break; 7211 case ARM::R10_R11: OpKind = MCK_Reg73; break; 7212 case ARM::R12_SP: OpKind = MCK_Reg75; break; 7213 case ARM::D0_D1_D2: OpKind = MCK_Reg83; break; 7214 case ARM::D1_D2_D3: OpKind = MCK_Reg88; break; 7215 case ARM::D2_D3_D4: OpKind = MCK_Reg83; break; 7216 case ARM::D3_D4_D5: OpKind = MCK_Reg88; break; 7217 case ARM::D4_D5_D6: OpKind = MCK_Reg83; break; 7218 case ARM::D5_D6_D7: OpKind = MCK_Reg88; break; 7219 case ARM::D6_D7_D8: OpKind = MCK_Reg84; break; 7220 case ARM::D7_D8_D9: OpKind = MCK_Reg89; break; 7221 case ARM::D8_D9_D10: OpKind = MCK_Reg85; break; 7222 case ARM::D9_D10_D11: OpKind = MCK_Reg90; break; 7223 case ARM::D10_D11_D12: OpKind = MCK_Reg85; break; 7224 case ARM::D11_D12_D13: OpKind = MCK_Reg90; break; 7225 case ARM::D12_D13_D14: OpKind = MCK_Reg85; break; 7226 case ARM::D13_D14_D15: OpKind = MCK_Reg90; break; 7227 case ARM::D14_D15_D16: OpKind = MCK_Reg86; break; 7228 case ARM::D15_D16_D17: OpKind = MCK_Reg91; break; 7229 case ARM::D16_D17_D18: OpKind = MCK_Reg87; break; 7230 case ARM::D17_D18_D19: OpKind = MCK_Reg92; break; 7231 case ARM::D18_D19_D20: OpKind = MCK_Reg87; break; 7232 case ARM::D19_D20_D21: OpKind = MCK_Reg92; break; 7233 case ARM::D20_D21_D22: OpKind = MCK_Reg87; break; 7234 case ARM::D21_D22_D23: OpKind = MCK_Reg92; break; 7235 case ARM::D22_D23_D24: OpKind = MCK_Reg87; break; 7236 case ARM::D23_D24_D25: OpKind = MCK_Reg92; break; 7237 case ARM::D24_D25_D26: OpKind = MCK_Reg87; break; 7238 case ARM::D25_D26_D27: OpKind = MCK_Reg92; break; 7239 case ARM::D26_D27_D28: OpKind = MCK_Reg87; break; 7240 case ARM::D27_D28_D29: OpKind = MCK_Reg92; break; 7241 case ARM::D28_D29_D30: OpKind = MCK_Reg87; break; 7242 case ARM::D29_D30_D31: OpKind = MCK_Reg92; break; 7243 case ARM::D0_D2_D4: OpKind = MCK_Reg93; break; 7244 case ARM::D1_D3_D5: OpKind = MCK_Reg93; break; 7245 case ARM::D2_D4_D6: OpKind = MCK_Reg93; break; 7246 case ARM::D3_D5_D7: OpKind = MCK_Reg93; break; 7247 case ARM::D4_D6_D8: OpKind = MCK_Reg94; break; 7248 case ARM::D5_D7_D9: OpKind = MCK_Reg94; break; 7249 case ARM::D6_D8_D10: OpKind = MCK_Reg95; break; 7250 case ARM::D7_D9_D11: OpKind = MCK_Reg95; break; 7251 case ARM::D8_D10_D12: OpKind = MCK_Reg96; break; 7252 case ARM::D9_D11_D13: OpKind = MCK_Reg96; break; 7253 case ARM::D10_D12_D14: OpKind = MCK_Reg96; break; 7254 case ARM::D11_D13_D15: OpKind = MCK_Reg96; break; 7255 case ARM::D12_D14_D16: OpKind = MCK_Reg97; break; 7256 case ARM::D13_D15_D17: OpKind = MCK_Reg97; break; 7257 case ARM::D14_D16_D18: OpKind = MCK_Reg98; break; 7258 case ARM::D15_D17_D19: OpKind = MCK_Reg98; break; 7259 case ARM::D16_D18_D20: OpKind = MCK_DTripleSpc; break; 7260 case ARM::D17_D19_D21: OpKind = MCK_DTripleSpc; break; 7261 case ARM::D18_D20_D22: OpKind = MCK_DTripleSpc; break; 7262 case ARM::D19_D21_D23: OpKind = MCK_DTripleSpc; break; 7263 case ARM::D20_D22_D24: OpKind = MCK_DTripleSpc; break; 7264 case ARM::D21_D23_D25: OpKind = MCK_DTripleSpc; break; 7265 case ARM::D22_D24_D26: OpKind = MCK_DTripleSpc; break; 7266 case ARM::D23_D25_D27: OpKind = MCK_DTripleSpc; break; 7267 case ARM::D24_D26_D28: OpKind = MCK_DTripleSpc; break; 7268 case ARM::D25_D27_D29: OpKind = MCK_DTripleSpc; break; 7269 case ARM::D26_D28_D30: OpKind = MCK_DTripleSpc; break; 7270 case ARM::D27_D29_D31: OpKind = MCK_DTripleSpc; break; 7271 case ARM::D1_D2: OpKind = MCK_Reg26; break; 7272 case ARM::D3_D4: OpKind = MCK_Reg26; break; 7273 case ARM::D5_D6: OpKind = MCK_Reg26; break; 7274 case ARM::D7_D8: OpKind = MCK_Reg27; break; 7275 case ARM::D9_D10: OpKind = MCK_Reg24; break; 7276 case ARM::D11_D12: OpKind = MCK_Reg24; break; 7277 case ARM::D13_D14: OpKind = MCK_Reg24; break; 7278 case ARM::D15_D16: OpKind = MCK_Reg25; break; 7279 case ARM::D17_D18: OpKind = MCK_DPair; break; 7280 case ARM::D19_D20: OpKind = MCK_DPair; break; 7281 case ARM::D21_D22: OpKind = MCK_DPair; break; 7282 case ARM::D23_D24: OpKind = MCK_DPair; break; 7283 case ARM::D25_D26: OpKind = MCK_DPair; break; 7284 case ARM::D27_D28: OpKind = MCK_DPair; break; 7285 case ARM::D29_D30: OpKind = MCK_DPair; break; 7286 case ARM::D1_D2_D3_D4: OpKind = MCK_Reg100; break; 7287 case ARM::D3_D4_D5_D6: OpKind = MCK_Reg100; break; 7288 case ARM::D5_D6_D7_D8: OpKind = MCK_Reg101; break; 7289 case ARM::D7_D8_D9_D10: OpKind = MCK_Reg102; break; 7290 case ARM::D9_D10_D11_D12: OpKind = MCK_Reg103; break; 7291 case ARM::D11_D12_D13_D14: OpKind = MCK_Reg103; break; 7292 case ARM::D13_D14_D15_D16: OpKind = MCK_Reg104; break; 7293 case ARM::D15_D16_D17_D18: OpKind = MCK_Reg105; break; 7294 case ARM::D17_D18_D19_D20: OpKind = MCK_Reg106; break; 7295 case ARM::D19_D20_D21_D22: OpKind = MCK_Reg106; break; 7296 case ARM::D21_D22_D23_D24: OpKind = MCK_Reg106; break; 7297 case ARM::D23_D24_D25_D26: OpKind = MCK_Reg106; break; 7298 case ARM::D25_D26_D27_D28: OpKind = MCK_Reg106; break; 7299 case ARM::D27_D28_D29_D30: OpKind = MCK_Reg106; break; 7300 } 7301 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success : 7302 getDiagKindFromRegisterClass(Kind); 7303 } 7304 7305 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER) 7306 return getDiagKindFromRegisterClass(Kind); 7307 7308 return MCTargetAsmParser::Match_InvalidOperand; 7309} 7310 7311#ifndef NDEBUG 7312const char *getMatchClassName(MatchClassKind Kind) { 7313 switch (Kind) { 7314 case InvalidMatchClass: return "InvalidMatchClass"; 7315 case OptionalMatchClass: return "OptionalMatchClass"; 7316 case MCK__DOT_d: return "MCK__DOT_d"; 7317 case MCK__DOT_f: return "MCK__DOT_f"; 7318 case MCK__DOT_s16: return "MCK__DOT_s16"; 7319 case MCK__DOT_s32: return "MCK__DOT_s32"; 7320 case MCK__DOT_s64: return "MCK__DOT_s64"; 7321 case MCK__DOT_s8: return "MCK__DOT_s8"; 7322 case MCK__DOT_u16: return "MCK__DOT_u16"; 7323 case MCK__DOT_u32: return "MCK__DOT_u32"; 7324 case MCK__DOT_u64: return "MCK__DOT_u64"; 7325 case MCK__DOT_u8: return "MCK__DOT_u8"; 7326 case MCK__DOT_f32: return "MCK__DOT_f32"; 7327 case MCK__DOT_f64: return "MCK__DOT_f64"; 7328 case MCK__DOT_i16: return "MCK__DOT_i16"; 7329 case MCK__DOT_i32: return "MCK__DOT_i32"; 7330 case MCK__DOT_i64: return "MCK__DOT_i64"; 7331 case MCK__DOT_i8: return "MCK__DOT_i8"; 7332 case MCK__DOT_p16: return "MCK__DOT_p16"; 7333 case MCK__DOT_p8: return "MCK__DOT_p8"; 7334 case MCK__EXCLAIM_: return "MCK__EXCLAIM_"; 7335 case MCK__35_0: return "MCK__35_0"; 7336 case MCK__DOT_16: return "MCK__DOT_16"; 7337 case MCK__DOT_32: return "MCK__DOT_32"; 7338 case MCK__DOT_64: return "MCK__DOT_64"; 7339 case MCK__DOT_8: return "MCK__DOT_8"; 7340 case MCK__DOT_f16: return "MCK__DOT_f16"; 7341 case MCK__DOT_p64: return "MCK__DOT_p64"; 7342 case MCK__DOT_w: return "MCK__DOT_w"; 7343 case MCK__91_: return "MCK__91_"; 7344 case MCK__93_: return "MCK__93_"; 7345 case MCK__94_: return "MCK__94_"; 7346 case MCK__123_: return "MCK__123_"; 7347 case MCK__125_: return "MCK__125_"; 7348 case MCK_Reg11: return "MCK_Reg11"; 7349 case MCK_Reg59: return "MCK_Reg59"; 7350 case MCK_Reg75: return "MCK_Reg75"; 7351 case MCK_APSR: return "MCK_APSR"; 7352 case MCK_APSR_NZCV: return "MCK_APSR_NZCV"; 7353 case MCK_CCR: return "MCK_CCR"; 7354 case MCK_FPEXC: return "MCK_FPEXC"; 7355 case MCK_FPINST: return "MCK_FPINST"; 7356 case MCK_FPINST2: return "MCK_FPINST2"; 7357 case MCK_FPSCR: return "MCK_FPSCR"; 7358 case MCK_FPSID: return "MCK_FPSID"; 7359 case MCK_GPRsp: return "MCK_GPRsp"; 7360 case MCK_LR: return "MCK_LR"; 7361 case MCK_MVFR0: return "MCK_MVFR0"; 7362 case MCK_MVFR1: return "MCK_MVFR1"; 7363 case MCK_MVFR2: return "MCK_MVFR2"; 7364 case MCK_PC: return "MCK_PC"; 7365 case MCK_SPSR: return "MCK_SPSR"; 7366 case MCK_Reg60: return "MCK_Reg60"; 7367 case MCK_Reg68: return "MCK_Reg68"; 7368 case MCK_Reg73: return "MCK_Reg73"; 7369 case MCK_Reg100: return "MCK_Reg100"; 7370 case MCK_Reg45: return "MCK_Reg45"; 7371 case MCK_Reg61: return "MCK_Reg61"; 7372 case MCK_Reg72: return "MCK_Reg72"; 7373 case MCK_Reg74: return "MCK_Reg74"; 7374 case MCK_Reg83: return "MCK_Reg83"; 7375 case MCK_Reg88: return "MCK_Reg88"; 7376 case MCK_Reg101: return "MCK_Reg101"; 7377 case MCK_Reg0: return "MCK_Reg0"; 7378 case MCK_Reg46: return "MCK_Reg46"; 7379 case MCK_Reg62: return "MCK_Reg62"; 7380 case MCK_Reg69: return "MCK_Reg69"; 7381 case MCK_Reg84: return "MCK_Reg84"; 7382 case MCK_Reg89: return "MCK_Reg89"; 7383 case MCK_Reg93: return "MCK_Reg93"; 7384 case MCK_Reg102: return "MCK_Reg102"; 7385 case MCK_QPR_8: return "MCK_QPR_8"; 7386 case MCK_Reg57: return "MCK_Reg57"; 7387 case MCK_Reg63: return "MCK_Reg63"; 7388 case MCK_tcGPR: return "MCK_tcGPR"; 7389 case MCK_Reg10: return "MCK_Reg10"; 7390 case MCK_Reg40: return "MCK_Reg40"; 7391 case MCK_Reg58: return "MCK_Reg58"; 7392 case MCK_Reg64: return "MCK_Reg64"; 7393 case MCK_Reg70: return "MCK_Reg70"; 7394 case MCK_Reg76: return "MCK_Reg76"; 7395 case MCK_Reg94: return "MCK_Reg94"; 7396 case MCK_Reg103: return "MCK_Reg103"; 7397 case MCK_Reg8: return "MCK_Reg8"; 7398 case MCK_Reg26: return "MCK_Reg26"; 7399 case MCK_Reg47: return "MCK_Reg47"; 7400 case MCK_Reg55: return "MCK_Reg55"; 7401 case MCK_Reg65: return "MCK_Reg65"; 7402 case MCK_Reg77: return "MCK_Reg77"; 7403 case MCK_Reg85: return "MCK_Reg85"; 7404 case MCK_Reg90: return "MCK_Reg90"; 7405 case MCK_Reg104: return "MCK_Reg104"; 7406 case MCK_GPRPair: return "MCK_GPRPair"; 7407 case MCK_Reg27: return "MCK_Reg27"; 7408 case MCK_Reg41: return "MCK_Reg41"; 7409 case MCK_Reg48: return "MCK_Reg48"; 7410 case MCK_Reg56: return "MCK_Reg56"; 7411 case MCK_Reg66: return "MCK_Reg66"; 7412 case MCK_Reg78: return "MCK_Reg78"; 7413 case MCK_Reg86: return "MCK_Reg86"; 7414 case MCK_Reg91: return "MCK_Reg91"; 7415 case MCK_Reg95: return "MCK_Reg95"; 7416 case MCK_Reg105: return "MCK_Reg105"; 7417 case MCK_DPR_8: return "MCK_DPR_8"; 7418 case MCK_QPR_VFP2: return "MCK_QPR_VFP2"; 7419 case MCK_hGPR: return "MCK_hGPR"; 7420 case MCK_tGPR: return "MCK_tGPR"; 7421 case MCK_tGPRwithpc: return "MCK_tGPRwithpc"; 7422 case MCK_Reg96: return "MCK_Reg96"; 7423 case MCK_Reg53: return "MCK_Reg53"; 7424 case MCK_QQQQPR: return "MCK_QQQQPR"; 7425 case MCK_Reg42: return "MCK_Reg42"; 7426 case MCK_Reg54: return "MCK_Reg54"; 7427 case MCK_Reg79: return "MCK_Reg79"; 7428 case MCK_Reg97: return "MCK_Reg97"; 7429 case MCK_Reg106: return "MCK_Reg106"; 7430 case MCK_rGPR: return "MCK_rGPR"; 7431 case MCK_Reg24: return "MCK_Reg24"; 7432 case MCK_Reg51: return "MCK_Reg51"; 7433 case MCK_Reg80: return "MCK_Reg80"; 7434 case MCK_Reg87: return "MCK_Reg87"; 7435 case MCK_Reg92: return "MCK_Reg92"; 7436 case MCK_GPRnopc: return "MCK_GPRnopc"; 7437 case MCK_QQPR: return "MCK_QQPR"; 7438 case MCK_Reg25: return "MCK_Reg25"; 7439 case MCK_Reg43: return "MCK_Reg43"; 7440 case MCK_Reg52: return "MCK_Reg52"; 7441 case MCK_Reg81: return "MCK_Reg81"; 7442 case MCK_Reg98: return "MCK_Reg98"; 7443 case MCK_DPR_VFP2: return "MCK_DPR_VFP2"; 7444 case MCK_GPR: return "MCK_GPR"; 7445 case MCK_GPRwithAPSR: return "MCK_GPRwithAPSR"; 7446 case MCK_QPR: return "MCK_QPR"; 7447 case MCK_SPR_8: return "MCK_SPR_8"; 7448 case MCK_DTripleSpc: return "MCK_DTripleSpc"; 7449 case MCK_DQuad: return "MCK_DQuad"; 7450 case MCK_DPairSpc: return "MCK_DPairSpc"; 7451 case MCK_DTriple: return "MCK_DTriple"; 7452 case MCK_DPair: return "MCK_DPair"; 7453 case MCK_DPR: return "MCK_DPR"; 7454 case MCK_HPR: return "MCK_HPR"; 7455 case MCK_AM2OffsetImm: return "MCK_AM2OffsetImm"; 7456 case MCK_AM3Offset: return "MCK_AM3Offset"; 7457 case MCK_ARMBranchTarget: return "MCK_ARMBranchTarget"; 7458 case MCK_AddrMode3: return "MCK_AddrMode3"; 7459 case MCK_AddrMode5: return "MCK_AddrMode5"; 7460 case MCK_AddrMode5FP16: return "MCK_AddrMode5FP16"; 7461 case MCK_AlignedMemory16: return "MCK_AlignedMemory16"; 7462 case MCK_AlignedMemory32: return "MCK_AlignedMemory32"; 7463 case MCK_AlignedMemory64: return "MCK_AlignedMemory64"; 7464 case MCK_AlignedMemory64or128: return "MCK_AlignedMemory64or128"; 7465 case MCK_AlignedMemory64or128or256: return "MCK_AlignedMemory64or128or256"; 7466 case MCK_AlignedMemoryNone: return "MCK_AlignedMemoryNone"; 7467 case MCK_AlignedMemory: return "MCK_AlignedMemory"; 7468 case MCK_DupAlignedMemory16: return "MCK_DupAlignedMemory16"; 7469 case MCK_DupAlignedMemory32: return "MCK_DupAlignedMemory32"; 7470 case MCK_DupAlignedMemory64: return "MCK_DupAlignedMemory64"; 7471 case MCK_DupAlignedMemory64or128: return "MCK_DupAlignedMemory64or128"; 7472 case MCK_DupAlignedMemoryNone: return "MCK_DupAlignedMemoryNone"; 7473 case MCK_AdrLabel: return "MCK_AdrLabel"; 7474 case MCK_BankedReg: return "MCK_BankedReg"; 7475 case MCK_Bitfield: return "MCK_Bitfield"; 7476 case MCK_CCOut: return "MCK_CCOut"; 7477 case MCK_CondCode: return "MCK_CondCode"; 7478 case MCK_CoprocNum: return "MCK_CoprocNum"; 7479 case MCK_CoprocOption: return "MCK_CoprocOption"; 7480 case MCK_CoprocReg: return "MCK_CoprocReg"; 7481 case MCK_DPRRegList: return "MCK_DPRRegList"; 7482 case MCK_FPImm: return "MCK_FPImm"; 7483 case MCK_Imm0_15: return "MCK_Imm0_15"; 7484 case MCK_Imm0_1: return "MCK_Imm0_1"; 7485 case MCK_Imm0_239: return "MCK_Imm0_239"; 7486 case MCK_Imm0_255: return "MCK_Imm0_255"; 7487 case MCK_Imm0_31: return "MCK_Imm0_31"; 7488 case MCK_Imm0_32: return "MCK_Imm0_32"; 7489 case MCK_Imm0_3: return "MCK_Imm0_3"; 7490 case MCK_Imm0_63: return "MCK_Imm0_63"; 7491 case MCK_Imm0_65535: return "MCK_Imm0_65535"; 7492 case MCK_Imm0_65535Expr: return "MCK_Imm0_65535Expr"; 7493 case MCK_Imm0_7: return "MCK_Imm0_7"; 7494 case MCK_Imm16: return "MCK_Imm16"; 7495 case MCK_Imm1_15: return "MCK_Imm1_15"; 7496 case MCK_Imm1_16: return "MCK_Imm1_16"; 7497 case MCK_Imm1_31: return "MCK_Imm1_31"; 7498 case MCK_Imm1_32: return "MCK_Imm1_32"; 7499 case MCK_Imm1_7: return "MCK_Imm1_7"; 7500 case MCK_Imm24bit: return "MCK_Imm24bit"; 7501 case MCK_Imm256_65535Expr: return "MCK_Imm256_65535Expr"; 7502 case MCK_Imm32: return "MCK_Imm32"; 7503 case MCK_Imm8: return "MCK_Imm8"; 7504 case MCK_Imm8_255: return "MCK_Imm8_255"; 7505 case MCK_Imm: return "MCK_Imm"; 7506 case MCK_InstSyncBarrierOpt: return "MCK_InstSyncBarrierOpt"; 7507 case MCK_MSRMask: return "MCK_MSRMask"; 7508 case MCK_MemBarrierOpt: return "MCK_MemBarrierOpt"; 7509 case MCK_MemImm0_1020s4Offset: return "MCK_MemImm0_1020s4Offset"; 7510 case MCK_MemImm12Offset: return "MCK_MemImm12Offset"; 7511 case MCK_MemImm8Offset: return "MCK_MemImm8Offset"; 7512 case MCK_MemImm8s4Offset: return "MCK_MemImm8s4Offset"; 7513 case MCK_MemNegImm8Offset: return "MCK_MemNegImm8Offset"; 7514 case MCK_MemNoOffset: return "MCK_MemNoOffset"; 7515 case MCK_MemPosImm8Offset: return "MCK_MemPosImm8Offset"; 7516 case MCK_MemRegOffset: return "MCK_MemRegOffset"; 7517 case MCK_ModImm: return "MCK_ModImm"; 7518 case MCK_ModImmNeg: return "MCK_ModImmNeg"; 7519 case MCK_ModImmNot: return "MCK_ModImmNot"; 7520 case MCK_PKHASRImm: return "MCK_PKHASRImm"; 7521 case MCK_PKHLSLImm: return "MCK_PKHLSLImm"; 7522 case MCK_PostIdxImm8: return "MCK_PostIdxImm8"; 7523 case MCK_PostIdxImm8s4: return "MCK_PostIdxImm8s4"; 7524 case MCK_PostIdxReg: return "MCK_PostIdxReg"; 7525 case MCK_PostIdxRegShifted: return "MCK_PostIdxRegShifted"; 7526 case MCK_ProcIFlags: return "MCK_ProcIFlags"; 7527 case MCK_RegList: return "MCK_RegList"; 7528 case MCK_RotImm: return "MCK_RotImm"; 7529 case MCK_SPRRegList: return "MCK_SPRRegList"; 7530 case MCK_SetEndImm: return "MCK_SetEndImm"; 7531 case MCK_RegShiftedImm: return "MCK_RegShiftedImm"; 7532 case MCK_RegShiftedReg: return "MCK_RegShiftedReg"; 7533 case MCK_ShifterImm: return "MCK_ShifterImm"; 7534 case MCK_ThumbBranchTarget: return "MCK_ThumbBranchTarget"; 7535 case MCK_ThumbMemPC: return "MCK_ThumbMemPC"; 7536 case MCK_ThumbModImmNeg1_7: return "MCK_ThumbModImmNeg1_7"; 7537 case MCK_ThumbModImmNeg8_255: return "MCK_ThumbModImmNeg8_255"; 7538 case MCK_ImmThumbSR: return "MCK_ImmThumbSR"; 7539 case MCK_TraceSyncBarrierOpt: return "MCK_TraceSyncBarrierOpt"; 7540 case MCK_UnsignedOffset_b8s2: return "MCK_UnsignedOffset_b8s2"; 7541 case MCK_VecListDPairAllLanes: return "MCK_VecListDPairAllLanes"; 7542 case MCK_VecListDPair: return "MCK_VecListDPair"; 7543 case MCK_VecListDPairSpacedAllLanes: return "MCK_VecListDPairSpacedAllLanes"; 7544 case MCK_VecListDPairSpaced: return "MCK_VecListDPairSpaced"; 7545 case MCK_VecListFourDAllLanes: return "MCK_VecListFourDAllLanes"; 7546 case MCK_VecListFourD: return "MCK_VecListFourD"; 7547 case MCK_VecListFourDByteIndexed: return "MCK_VecListFourDByteIndexed"; 7548 case MCK_VecListFourDHWordIndexed: return "MCK_VecListFourDHWordIndexed"; 7549 case MCK_VecListFourDWordIndexed: return "MCK_VecListFourDWordIndexed"; 7550 case MCK_VecListFourQAllLanes: return "MCK_VecListFourQAllLanes"; 7551 case MCK_VecListFourQ: return "MCK_VecListFourQ"; 7552 case MCK_VecListFourQHWordIndexed: return "MCK_VecListFourQHWordIndexed"; 7553 case MCK_VecListFourQWordIndexed: return "MCK_VecListFourQWordIndexed"; 7554 case MCK_VecListOneDAllLanes: return "MCK_VecListOneDAllLanes"; 7555 case MCK_VecListOneD: return "MCK_VecListOneD"; 7556 case MCK_VecListOneDByteIndexed: return "MCK_VecListOneDByteIndexed"; 7557 case MCK_VecListOneDHWordIndexed: return "MCK_VecListOneDHWordIndexed"; 7558 case MCK_VecListOneDWordIndexed: return "MCK_VecListOneDWordIndexed"; 7559 case MCK_VecListThreeDAllLanes: return "MCK_VecListThreeDAllLanes"; 7560 case MCK_VecListThreeD: return "MCK_VecListThreeD"; 7561 case MCK_VecListThreeDByteIndexed: return "MCK_VecListThreeDByteIndexed"; 7562 case MCK_VecListThreeDHWordIndexed: return "MCK_VecListThreeDHWordIndexed"; 7563 case MCK_VecListThreeDWordIndexed: return "MCK_VecListThreeDWordIndexed"; 7564 case MCK_VecListThreeQAllLanes: return "MCK_VecListThreeQAllLanes"; 7565 case MCK_VecListThreeQ: return "MCK_VecListThreeQ"; 7566 case MCK_VecListThreeQHWordIndexed: return "MCK_VecListThreeQHWordIndexed"; 7567 case MCK_VecListThreeQWordIndexed: return "MCK_VecListThreeQWordIndexed"; 7568 case MCK_VecListTwoDByteIndexed: return "MCK_VecListTwoDByteIndexed"; 7569 case MCK_VecListTwoDHWordIndexed: return "MCK_VecListTwoDHWordIndexed"; 7570 case MCK_VecListTwoDWordIndexed: return "MCK_VecListTwoDWordIndexed"; 7571 case MCK_VecListTwoQHWordIndexed: return "MCK_VecListTwoQHWordIndexed"; 7572 case MCK_VecListTwoQWordIndexed: return "MCK_VecListTwoQWordIndexed"; 7573 case MCK_VectorIndex16: return "MCK_VectorIndex16"; 7574 case MCK_VectorIndex32: return "MCK_VectorIndex32"; 7575 case MCK_VectorIndex64: return "MCK_VectorIndex64"; 7576 case MCK_VectorIndex8: return "MCK_VectorIndex8"; 7577 case MCK_MemTBB: return "MCK_MemTBB"; 7578 case MCK_MemTBH: return "MCK_MemTBH"; 7579 case MCK_ComplexRotationEven: return "MCK_ComplexRotationEven"; 7580 case MCK_ComplexRotationOdd: return "MCK_ComplexRotationOdd"; 7581 case MCK_NEONi16vmovi8Replicate: return "MCK_NEONi16vmovi8Replicate"; 7582 case MCK_NEONi16invi8Replicate: return "MCK_NEONi16invi8Replicate"; 7583 case MCK_NEONi32vmovi8Replicate: return "MCK_NEONi32vmovi8Replicate"; 7584 case MCK_NEONi32invi8Replicate: return "MCK_NEONi32invi8Replicate"; 7585 case MCK_NEONi64vmovi8Replicate: return "MCK_NEONi64vmovi8Replicate"; 7586 case MCK_NEONi64invi8Replicate: return "MCK_NEONi64invi8Replicate"; 7587 case MCK_NEONi32vmovi16Replicate: return "MCK_NEONi32vmovi16Replicate"; 7588 case MCK_NEONi64vmovi16Replicate: return "MCK_NEONi64vmovi16Replicate"; 7589 case MCK_NEONi64vmovi32Replicate: return "MCK_NEONi64vmovi32Replicate"; 7590 case MCK_ConstPoolAsmImm: return "MCK_ConstPoolAsmImm"; 7591 case MCK_FBits16: return "MCK_FBits16"; 7592 case MCK_FBits32: return "MCK_FBits32"; 7593 case MCK_Imm0_4095: return "MCK_Imm0_4095"; 7594 case MCK_Imm0_4095Neg: return "MCK_Imm0_4095Neg"; 7595 case MCK_ITMask: return "MCK_ITMask"; 7596 case MCK_ITCondCode: return "MCK_ITCondCode"; 7597 case MCK_NEONi16splat: return "MCK_NEONi16splat"; 7598 case MCK_NEONi32splat: return "MCK_NEONi32splat"; 7599 case MCK_NEONi64splat: return "MCK_NEONi64splat"; 7600 case MCK_NEONi8splat: return "MCK_NEONi8splat"; 7601 case MCK_NEONi16splatNot: return "MCK_NEONi16splatNot"; 7602 case MCK_NEONi32splatNot: return "MCK_NEONi32splatNot"; 7603 case MCK_NEONi32vmov: return "MCK_NEONi32vmov"; 7604 case MCK_NEONi32vmovNeg: return "MCK_NEONi32vmovNeg"; 7605 case MCK_ShrImm16: return "MCK_ShrImm16"; 7606 case MCK_ShrImm32: return "MCK_ShrImm32"; 7607 case MCK_ShrImm64: return "MCK_ShrImm64"; 7608 case MCK_ShrImm8: return "MCK_ShrImm8"; 7609 case MCK_T2SOImm: return "MCK_T2SOImm"; 7610 case MCK_T2SOImmNeg: return "MCK_T2SOImmNeg"; 7611 case MCK_T2SOImmNot: return "MCK_T2SOImmNot"; 7612 case MCK_MemUImm12Offset: return "MCK_MemUImm12Offset"; 7613 case MCK_T2MemRegOffset: return "MCK_T2MemRegOffset"; 7614 case MCK_Imm8s4: return "MCK_Imm8s4"; 7615 case MCK_MemPCRelImm12: return "MCK_MemPCRelImm12"; 7616 case MCK_MemThumbRIs1: return "MCK_MemThumbRIs1"; 7617 case MCK_MemThumbRIs2: return "MCK_MemThumbRIs2"; 7618 case MCK_MemThumbRIs4: return "MCK_MemThumbRIs4"; 7619 case MCK_MemThumbRR: return "MCK_MemThumbRR"; 7620 case MCK_MemThumbSPI: return "MCK_MemThumbSPI"; 7621 case MCK_Imm0_1020s4: return "MCK_Imm0_1020s4"; 7622 case MCK_Imm0_508s4: return "MCK_Imm0_508s4"; 7623 case MCK_Imm0_508s4Neg: return "MCK_Imm0_508s4Neg"; 7624 case NumMatchClassKinds: return "NumMatchClassKinds"; 7625 } 7626 llvm_unreachable("unhandled MatchClassKind!"); 7627} 7628 7629#endif // NDEBUG 7630uint64_t ARMAsmParser:: 7631ComputeAvailableFeatures(const FeatureBitset& FB) const { 7632 uint64_t Features = 0; 7633 if ((FB[ARM::HasV4TOps])) 7634 Features |= Feature_HasV4T; 7635 if ((FB[ARM::HasV5TOps])) 7636 Features |= Feature_HasV5T; 7637 if ((FB[ARM::HasV5TEOps])) 7638 Features |= Feature_HasV5TE; 7639 if ((FB[ARM::HasV6Ops])) 7640 Features |= Feature_HasV6; 7641 if ((FB[ARM::HasV6MOps])) 7642 Features |= Feature_HasV6M; 7643 if ((FB[ARM::HasV8MBaselineOps])) 7644 Features |= Feature_HasV8MBaseline; 7645 if ((FB[ARM::HasV8MMainlineOps])) 7646 Features |= Feature_HasV8MMainline; 7647 if ((FB[ARM::HasV6T2Ops])) 7648 Features |= Feature_HasV6T2; 7649 if ((FB[ARM::HasV6KOps])) 7650 Features |= Feature_HasV6K; 7651 if ((FB[ARM::HasV7Ops])) 7652 Features |= Feature_HasV7; 7653 if ((FB[ARM::HasV8Ops])) 7654 Features |= Feature_HasV8; 7655 if ((!FB[ARM::HasV8Ops])) 7656 Features |= Feature_PreV8; 7657 if ((FB[ARM::HasV8_1aOps])) 7658 Features |= Feature_HasV8_1a; 7659 if ((FB[ARM::HasV8_2aOps])) 7660 Features |= Feature_HasV8_2a; 7661 if ((FB[ARM::HasV8_3aOps])) 7662 Features |= Feature_HasV8_3a; 7663 if ((FB[ARM::HasV8_4aOps])) 7664 Features |= Feature_HasV8_4a; 7665 if ((FB[ARM::FeatureVFP2])) 7666 Features |= Feature_HasVFP2; 7667 if ((FB[ARM::FeatureVFP3])) 7668 Features |= Feature_HasVFP3; 7669 if ((FB[ARM::FeatureVFP4])) 7670 Features |= Feature_HasVFP4; 7671 if ((!FB[ARM::FeatureVFPOnlySP])) 7672 Features |= Feature_HasDPVFP; 7673 if ((FB[ARM::FeatureFPARMv8])) 7674 Features |= Feature_HasFPARMv8; 7675 if ((FB[ARM::FeatureNEON])) 7676 Features |= Feature_HasNEON; 7677 if ((FB[ARM::FeatureSHA2])) 7678 Features |= Feature_HasSHA2; 7679 if ((FB[ARM::FeatureAES])) 7680 Features |= Feature_HasAES; 7681 if ((FB[ARM::FeatureCrypto])) 7682 Features |= Feature_HasCrypto; 7683 if ((FB[ARM::FeatureDotProd])) 7684 Features |= Feature_HasDotProd; 7685 if ((FB[ARM::FeatureCRC])) 7686 Features |= Feature_HasCRC; 7687 if ((FB[ARM::FeatureRAS])) 7688 Features |= Feature_HasRAS; 7689 if ((FB[ARM::FeatureFP16])) 7690 Features |= Feature_HasFP16; 7691 if ((FB[ARM::FeatureFullFP16])) 7692 Features |= Feature_HasFullFP16; 7693 if ((FB[ARM::FeatureHWDivThumb])) 7694 Features |= Feature_HasDivideInThumb; 7695 if ((FB[ARM::FeatureHWDivARM])) 7696 Features |= Feature_HasDivideInARM; 7697 if ((FB[ARM::FeatureDSP])) 7698 Features |= Feature_HasDSP; 7699 if ((FB[ARM::FeatureDB])) 7700 Features |= Feature_HasDB; 7701 if ((FB[ARM::FeatureDFB])) 7702 Features |= Feature_HasDFB; 7703 if ((FB[ARM::FeatureV7Clrex])) 7704 Features |= Feature_HasV7Clrex; 7705 if ((FB[ARM::FeatureAcquireRelease])) 7706 Features |= Feature_HasAcquireRelease; 7707 if ((FB[ARM::FeatureMP])) 7708 Features |= Feature_HasMP; 7709 if ((FB[ARM::FeatureVirtualization])) 7710 Features |= Feature_HasVirtualization; 7711 if ((FB[ARM::FeatureTrustZone])) 7712 Features |= Feature_HasTrustZone; 7713 if ((FB[ARM::Feature8MSecExt])) 7714 Features |= Feature_Has8MSecExt; 7715 if ((FB[ARM::ModeThumb])) 7716 Features |= Feature_IsThumb; 7717 if ((FB[ARM::ModeThumb]) && (FB[ARM::FeatureThumb2])) 7718 Features |= Feature_IsThumb2; 7719 if ((FB[ARM::FeatureMClass])) 7720 Features |= Feature_IsMClass; 7721 if ((!FB[ARM::FeatureMClass])) 7722 Features |= Feature_IsNotMClass; 7723 if ((!FB[ARM::ModeThumb])) 7724 Features |= Feature_IsARM; 7725 if ((FB[ARM::FeatureNaClTrap])) 7726 Features |= Feature_UseNaClTrap; 7727 if ((!FB[ARM::FeatureNoNegativeImmediates])) 7728 Features |= Feature_UseNegativeImmediates; 7729 return Features; 7730} 7731 7732static const char *const MnemonicTable = 7733 "\t__brkdiv0\003adc\003add\004addw\003adr\004aesd\004aese\006aesimc\005a" 7734 "esmc\003and\003asr\001b\003bfc\003bfi\003bic\004bkpt\002bl\003blx\005bl" 7735 "xns\002bx\003bxj\004bxns\004cbnz\003cbz\003cdp\004cdp2\005clrex\003clz\003" 7736 "cmn\003cmp\003cps\006crc32b\007crc32cb\007crc32ch\007crc32cw\006crc32h\006" 7737 "crc32w\004csdb\003dbg\005dcps1\005dcps2\005dcps3\003dfb\003dmb\003dsb\003" 7738 "eor\004eret\003esb\005faddd\005fadds\006fcmpzd\006fcmpzs\007fconstd\007" 7739 "fconsts\007fldmdbx\007fldmiax\005fmdhr\005fmdlr\006fmstat\007fstmdbx\007" 7740 "fstmiax\005fsubd\005fsubs\004hint\003hlt\003hvc\003isb\002it\003lda\004" 7741 "ldab\005ldaex\006ldaexb\006ldaexd\006ldaexh\004ldah\003ldc\004ldc2\005l" 7742 "dc2l\004ldcl\003ldm\005ldmda\005ldmdb\005ldmib\003ldr\004ldrb\005ldrbt\004" 7743 "ldrd\005ldrex\006ldrexb\006ldrexd\006ldrexh\004ldrh\005ldrht\005ldrsb\006" 7744 "ldrsbt\005ldrsh\006ldrsht\004ldrt\003lsl\003lsr\003mcr\004mcr2\004mcrr\005" 7745 "mcrr2\003mla\003mls\003mov\004movs\004movt\004movw\003mrc\004mrc2\004mr" 7746 "rc\005mrrc2\003mrs\003msr\003mul\003mvn\003neg\003nop\003orn\003orr\005" 7747 "pkhbt\005pkhtb\003pld\004pldw\003pli\003pop\004push\004qadd\006qadd16\005" 7748 "qadd8\004qasx\005qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub8\004r" 7749 "bit\003rev\005rev16\005revsh\005rfeda\005rfedb\005rfeia\005rfeib\003ror" 7750 "\003rrx\003rsb\003rsc\006sadd16\005sadd8\004sasx\003sbc\004sbfx\004sdiv" 7751 "\003sel\006setend\006setpan\003sev\004sevl\002sg\005sha1c\005sha1h\005s" 7752 "ha1m\005sha1p\007sha1su0\007sha1su1\007sha256h\010sha256h2\tsha256su0\t" 7753 "sha256su1\007shadd16\006shadd8\005shasx\005shsax\007shsub16\006shsub8\003" 7754 "smc\006smlabb\006smlabt\005smlad\006smladx\005smlal\007smlalbb\007smlal" 7755 "bt\006smlald\007smlaldx\007smlaltb\007smlaltt\006smlatb\006smlatt\006sm" 7756 "lawb\006smlawt\005smlsd\006smlsdx\006smlsld\007smlsldx\005smmla\006smml" 7757 "ar\005smmls\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006smulbb\006" 7758 "smulbt\005smull\006smultb\006smultt\006smulwb\006smulwt\005smusd\006smu" 7759 "sdx\005srsda\005srsdb\005srsia\005srsib\004ssat\006ssat16\004ssax\006ss" 7760 "ub16\005ssub8\003stc\004stc2\005stc2l\004stcl\003stl\004stlb\005stlex\006" 7761 "stlexb\006stlexd\006stlexh\004stlh\003stm\005stmda\005stmdb\005stmib\003" 7762 "str\004strb\005strbt\004strd\005strex\006strexb\006strexd\006strexh\004" 7763 "strh\005strht\004strt\003sub\004subs\004subw\003svc\003swp\004swpb\005s" 7764 "xtab\007sxtab16\005sxtah\004sxtb\006sxtb16\004sxth\003tbb\003tbh\003teq" 7765 "\004trap\003tsb\003tst\002tt\003tta\004ttat\003ttt\006uadd16\005uadd8\004" 7766 "uasx\004ubfx\003udf\004udiv\007uhadd16\006uhadd8\005uhasx\005uhsax\007u" 7767 "hsub16\006uhsub8\005umaal\005umlal\005umull\007uqadd16\006uqadd8\005uqa" 7768 "sx\005uqsax\007uqsub16\006uqsub8\005usad8\006usada8\004usat\006usat16\004" 7769 "usax\006usub16\005usub8\005uxtab\007uxtab16\005uxtah\004uxtb\006uxtb16\004" 7770 "uxth\004vaba\005vabal\004vabd\005vabdl\004vabs\005vacge\005vacgt\005vac" 7771 "le\005vaclt\004vadd\006vaddhn\005vaddl\005vaddw\004vand\004vbic\004vbif" 7772 "\004vbit\004vbsl\005vcadd\004vceq\004vcge\004vcgt\004vcle\004vcls\004vc" 7773 "lt\004vclz\005vcmla\004vcmp\005vcmpe\004vcnt\004vcvt\005vcvta\005vcvtb\005" 7774 "vcvtm\005vcvtn\005vcvtp\005vcvtr\005vcvtt\004vdiv\004vdup\004veor\004ve" 7775 "xt\004vfma\004vfms\005vfnma\005vfnms\005vhadd\005vhsub\004vins\005vjcvt" 7776 "\004vld1\004vld2\004vld3\004vld4\006vldmdb\006vldmia\004vldr\005vlldm\005" 7777 "vlstm\004vmax\006vmaxnm\004vmin\006vminnm\004vmla\005vmlal\004vmls\005v" 7778 "mlsl\004vmov\005vmovl\005vmovn\005vmovx\004vmrs\004vmsr\004vmul\005vmul" 7779 "l\004vmvn\004vneg\005vnmla\005vnmls\005vnmul\004vorn\004vorr\006vpadal\005" 7780 "vpadd\006vpaddl\005vpmax\005vpmin\004vpop\005vpush\005vqabs\005vqadd\007" 7781 "vqdmlal\007vqdmlsl\007vqdmulh\007vqdmull\006vqmovn\007vqmovun\005vqneg\010" 7782 "vqrdmlah\010vqrdmlsh\010vqrdmulh\006vqrshl\007vqrshrn\010vqrshrun\005vq" 7783 "shl\006vqshlu\006vqshrn\007vqshrun\005vqsub\007vraddhn\006vrecpe\006vre" 7784 "cps\006vrev16\006vrev32\006vrev64\006vrhadd\006vrinta\006vrintm\006vrin" 7785 "tn\006vrintp\006vrintr\006vrintx\006vrintz\005vrshl\005vrshr\006vrshrn\007" 7786 "vrsqrte\007vrsqrts\005vrsra\007vrsubhn\005vsdot\006vseleq\006vselge\006" 7787 "vselgt\006vselvs\004vshl\005vshll\004vshr\005vshrn\004vsli\005vsqrt\004" 7788 "vsra\004vsri\004vst1\004vst2\004vst3\004vst4\006vstmdb\006vstmia\004vst" 7789 "r\004vsub\006vsubhn\005vsubl\005vsubw\004vswp\004vtbl\004vtbx\004vtrn\004" 7790 "vtst\005vudot\004vuzp\004vzip\003wfe\003wfi\005yield"; 7791 7792namespace { 7793 struct MatchEntry { 7794 uint16_t Mnemonic; 7795 uint16_t Opcode; 7796 uint16_t ConvertFn; 7797 uint64_t RequiredFeatures; 7798 uint16_t Classes[18]; 7799 StringRef getMnemonic() const { 7800 return StringRef(MnemonicTable + Mnemonic + 1, 7801 MnemonicTable[Mnemonic]); 7802 } 7803 }; 7804 7805 // Predicate for searching for an opcode. 7806 struct LessOpcode { 7807 bool operator()(const MatchEntry &LHS, StringRef RHS) { 7808 return LHS.getMnemonic() < RHS; 7809 } 7810 bool operator()(StringRef LHS, const MatchEntry &RHS) { 7811 return LHS < RHS.getMnemonic(); 7812 } 7813 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { 7814 return LHS.getMnemonic() < RHS.getMnemonic(); 7815 } 7816 }; 7817} // end anonymous namespace. 7818 7819static const MatchEntry MatchTable0[] = { 7820 { 0 /* __brkdiv0 */, ARM::t__brkdiv0, Convert_NoOperands, Feature_IsThumb, { }, }, 7821 { 10 /* adc */, ARM::tADC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 7822 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 7823 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 7824 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 7825 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 7826 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 7827 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 7828 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 7829 { 10 /* adc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 7830 { 10 /* adc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 7831 { 10 /* adc */, ARM::ADCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, }, 7832 { 10 /* adc */, ARM::ADCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 7833 { 10 /* adc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 7834 { 10 /* adc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 7835 { 10 /* adc */, ARM::ADCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 7836 { 10 /* adc */, ARM::t2ADCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 7837 { 10 /* adc */, ARM::t2ADCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 7838 { 14 /* add */, ARM::tADDspr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPR }, }, 7839 { 14 /* add */, ARM::tADDspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, }, 7840 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_2__CondCode2_0, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4Neg }, }, 7841 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095 }, }, 7842 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095Neg }, }, 7843 { 14 /* add */, ARM::tADDhirr, Convert__Reg1_1__Tie0_1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 7844 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 7845 { 14 /* add */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 7846 { 14 /* add */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, }, 7847 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 7848 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 7849 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 7850 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 7851 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 7852 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 7853 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 7854 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, }, 7855 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 7856 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 7857 { 14 /* add */, ARM::tADDspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, }, 7858 { 14 /* add */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s4Neg1_3__CondCode2_0, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4Neg }, }, 7859 { 14 /* add */, ARM::tADDrSPi, Convert__Reg1_1__Reg1_2__Imm0_1020s41_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_GPRsp, MCK_Imm0_1020s4 }, }, 7860 { 14 /* add */, ARM::t2ADR, Convert__Reg1_1__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_PC, MCK_Imm0_4095 }, }, 7861 { 14 /* add */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, }, 7862 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, }, 7863 { 14 /* add */, ARM::tADDrSP, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPRsp, MCK_GPR }, }, 7864 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 7865 { 14 /* add */, ARM::tADDrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, }, 7866 { 14 /* add */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, }, 7867 { 14 /* add */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, }, 7868 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 7869 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 7870 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, }, 7871 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 7872 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 7873 { 14 /* add */, ARM::ADDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 7874 { 14 /* add */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 7875 { 14 /* add */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, }, 7876 { 14 /* add */, ARM::ADDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 7877 { 14 /* add */, ARM::ADDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 7878 { 14 /* add */, ARM::t2ADDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 7879 { 14 /* add */, ARM::t2ADDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 7880 { 14 /* add */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, }, 7881 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 7882 { 14 /* add */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 7883 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095Neg }, }, 7884 { 18 /* addw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, }, 7885 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, }, 7886 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_T2SOImmNeg }, }, 7887 { 23 /* adr */, ARM::tADR, Convert__Reg1_1__UnsignedOffset_b8s21_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_UnsignedOffset_b8s2 }, }, 7888 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 7889 { 23 /* adr */, ARM::ADR, Convert__Reg1_1__AdrLabel1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AdrLabel }, }, 7890 { 23 /* adr */, ARM::t2ADR, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm }, }, 7891 { 27 /* aesd */, ARM::AESD, Convert__Reg1_1__Tie0_1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 7892 { 32 /* aese */, ARM::AESE, Convert__Reg1_1__Tie0_1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 7893 { 37 /* aesimc */, ARM::AESIMC, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 7894 { 44 /* aesmc */, ARM::AESMC, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 7895 { 50 /* and */, ARM::tAND, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 7896 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 7897 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 7898 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 7899 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 7900 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 7901 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 7902 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 7903 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 7904 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 7905 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 7906 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 7907 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 7908 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, }, 7909 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 7910 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 7911 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 7912 { 50 /* and */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 7913 { 50 /* and */, ARM::ANDrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 7914 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 7915 { 50 /* and */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 7916 { 50 /* and */, ARM::ANDrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 7917 { 50 /* and */, ARM::ANDrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 7918 { 50 /* and */, ARM::t2ANDrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 7919 { 50 /* and */, ARM::t2ANDrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 7920 { 50 /* and */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 7921 { 50 /* and */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 7922 { 54 /* asr */, ARM::tASRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 7923 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, }, 7924 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 7925 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, }, 7926 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 7927 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, }, 7928 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 7929 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, }, 7930 { 54 /* asr */, ARM::tASRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, }, 7931 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 7932 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 7933 { 54 /* asr */, ARM::ASRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 7934 { 54 /* asr */, ARM::ASRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, }, 7935 { 54 /* asr */, ARM::t2ASRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 7936 { 54 /* asr */, ARM::t2ASRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 7937 { 58 /* b */, ARM::Bcc, Convert__ARMBranchTarget1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, }, 7938 { 58 /* b */, ARM::tB, ConvertCustom_cvtThumbBranches, Feature_IsThumb, { MCK_CondCode, MCK_Imm }, }, 7939 { 58 /* b */, ARM::tBcc, ConvertCustom_cvtThumbBranches, Feature_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, }, 7940 { 58 /* b */, ARM::t2Bcc, ConvertCustom_cvtThumbBranches, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm }, }, 7941 { 58 /* b */, ARM::t2B, ConvertCustom_cvtThumbBranches, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK__DOT_w, MCK_ThumbBranchTarget }, }, 7942 { 60 /* bfc */, ARM::t2BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Bitfield }, }, 7943 { 60 /* bfc */, ARM::BFC, Convert__Reg1_1__Tie0_1_1__Bitfield1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Bitfield }, }, 7944 { 64 /* bfi */, ARM::t2BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Bitfield }, }, 7945 { 64 /* bfi */, ARM::BFI, Convert__Reg1_1__Tie0_1_1__Reg1_2__Bitfield1_3__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Bitfield }, }, 7946 { 68 /* bic */, ARM::tBIC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 7947 { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 7948 { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 7949 { 68 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 7950 { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 7951 { 68 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 7952 { 68 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 7953 { 68 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 7954 { 68 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 7955 { 68 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 7956 { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 7957 { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 7958 { 68 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 7959 { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImmNot }, }, 7960 { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 7961 { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 7962 { 68 /* bic */, ARM::t2BICri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 7963 { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 7964 { 68 /* bic */, ARM::BICrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 7965 { 68 /* bic */, ARM::BICri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 7966 { 68 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 7967 { 68 /* bic */, ARM::BICrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 7968 { 68 /* bic */, ARM::BICrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 7969 { 68 /* bic */, ARM::t2BICrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 7970 { 68 /* bic */, ARM::t2BICrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 7971 { 68 /* bic */, ARM::t2BICri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 7972 { 68 /* bic */, ARM::t2ANDri, Convert__Reg1_3__Reg1_4__T2SOImmNot1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 7973 { 72 /* bkpt */, ARM::BKPT, Convert__imm_95_0, Feature_IsARM, { }, }, 7974 { 72 /* bkpt */, ARM::tBKPT, Convert__imm_95_0, Feature_IsThumb, { }, }, 7975 { 72 /* bkpt */, ARM::tBKPT, Convert__Imm0_2551_0, Feature_IsThumb, { MCK_Imm0_255 }, }, 7976 { 72 /* bkpt */, ARM::BKPT, Convert__Imm0_655351_0, Feature_IsARM, { MCK_Imm0_65535 }, }, 7977 { 77 /* bl */, ARM::BL, Convert__ARMBranchTarget1_0, Feature_IsARM, { MCK_ARMBranchTarget }, }, 7978 { 77 /* bl */, ARM::BL_pred, Convert__ARMBranchTarget1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_ARMBranchTarget }, }, 7979 { 77 /* bl */, ARM::tBL, Convert__CondCode2_0__ThumbBranchTarget1_1, Feature_IsThumb, { MCK_CondCode, MCK_ThumbBranchTarget }, }, 7980 { 80 /* blx */, ARM::BLX, Convert__Reg1_0, Feature_IsARM|Feature_HasV5T, { MCK_GPR }, }, 7981 { 80 /* blx */, ARM::BLXi, Convert__ThumbBranchTarget1_0, Feature_IsARM|Feature_HasV5T, { MCK_ThumbBranchTarget }, }, 7982 { 80 /* blx */, ARM::BLX_pred, Convert__Reg1_1__CondCode2_0, Feature_IsARM|Feature_HasV5T, { MCK_CondCode, MCK_GPR }, }, 7983 { 80 /* blx */, ARM::tBLXr, Convert__CondCode2_0__Reg1_1, Feature_IsThumb|Feature_HasV5T, { MCK_CondCode, MCK_GPR }, }, 7984 { 80 /* blx */, ARM::tBLXi, Convert__CondCode2_0__ARMBranchTarget1_1, Feature_IsThumb|Feature_HasV5T|Feature_IsNotMClass, { MCK_CondCode, MCK_ARMBranchTarget }, }, 7985 { 84 /* blxns */, ARM::tBLXNSr, Convert__CondCode2_0__Reg1_1, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, }, 7986 { 90 /* bx */, ARM::BX, Convert__Reg1_0, Feature_IsARM|Feature_HasV4T, { MCK_GPR }, }, 7987 { 90 /* bx */, ARM::BX_RET, Convert__CondCode2_0, Feature_IsARM|Feature_HasV4T, { MCK_CondCode, MCK_LR }, }, 7988 { 90 /* bx */, ARM::BX_pred, Convert__Reg1_1__CondCode2_0, Feature_IsARM|Feature_HasV4T, { MCK_CondCode, MCK_GPR }, }, 7989 { 90 /* bx */, ARM::tBX, Convert__Reg1_1__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR }, }, 7990 { 93 /* bxj */, ARM::t2BXJ, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRnopc }, }, 7991 { 93 /* bxj */, ARM::BXJ, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR }, }, 7992 { 97 /* bxns */, ARM::tBXNS, Convert__Reg1_1__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPR }, }, 7993 { 102 /* cbnz */, ARM::tCBNZ, Convert__Reg1_0__ThumbBranchTarget1_1, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, }, 7994 { 107 /* cbz */, ARM::tCBZ, Convert__Reg1_0__ThumbBranchTarget1_1, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_tGPR, MCK_ThumbBranchTarget }, }, 7995 { 111 /* cdp */, ARM::CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsARM|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 7996 { 111 /* cdp */, ARM::t2CDP, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 7997 { 115 /* cdp2 */, ARM::CDP2, Convert__CoprocNum1_0__Imm0_151_1__CoprocReg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 7998 { 115 /* cdp2 */, ARM::t2CDP2, Convert__CoprocNum1_1__Imm0_151_2__CoprocReg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_CoprocReg, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 7999 { 120 /* clrex */, ARM::CLREX, Convert_NoOperands, Feature_IsARM|Feature_HasV6K, { }, }, 8000 { 120 /* clrex */, ARM::t2CLREX, Convert__CondCode2_0, Feature_IsThumb|Feature_HasV7Clrex, { MCK_CondCode }, }, 8001 { 126 /* clz */, ARM::t2CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8002 { 126 /* clz */, ARM::CLZ, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV5T, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8003 { 130 /* cmn */, ARM::tCMNz, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8004 { 130 /* cmn */, ARM::CMPri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, }, 8005 { 130 /* cmn */, ARM::t2CMPri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 8006 { 130 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 8007 { 130 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 8008 { 130 /* cmn */, ARM::CMNzrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 8009 { 130 /* cmn */, ARM::t2CMNri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 8010 { 130 /* cmn */, ARM::CMNzrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8011 { 130 /* cmn */, ARM::CMNri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8012 { 130 /* cmn */, ARM::CMNzrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8013 { 130 /* cmn */, ARM::t2CMNzrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 8014 { 130 /* cmn */, ARM::t2CMNzrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, }, 8015 { 130 /* cmn */, ARM::t2CMNri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, }, 8016 { 134 /* cmp */, ARM::tCMPr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8017 { 134 /* cmp */, ARM::tCMPi8, Convert__Reg1_1__Imm0_2551_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 8018 { 134 /* cmp */, ARM::CMNri, Convert__Reg1_1__ModImmNeg1_2__CondCode2_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_ModImmNeg }, }, 8019 { 134 /* cmp */, ARM::t2CMNri, Convert__Reg1_1__T2SOImmNeg1_2__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNeg }, }, 8020 { 134 /* cmp */, ARM::t2CMPrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 8021 { 134 /* cmp */, ARM::CMPrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 8022 { 134 /* cmp */, ARM::t2CMPri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 8023 { 134 /* cmp */, ARM::CMPrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8024 { 134 /* cmp */, ARM::tCMPhir, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8025 { 134 /* cmp */, ARM::CMPri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8026 { 134 /* cmp */, ARM::CMPrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8027 { 134 /* cmp */, ARM::t2CMPrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 8028 { 134 /* cmp */, ARM::t2CMPrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, }, 8029 { 134 /* cmp */, ARM::t2CMPri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, }, 8030 { 138 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_Imm0_31 }, }, 8031 { 138 /* cps */, ARM::CPS1p, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, }, 8032 { 138 /* cps */, ARM::t2CPS1p, Convert__Imm0_311_1, Feature_IsThumb2, { MCK__DOT_w, MCK_Imm0_31 }, }, 8033 { 138 /* cps */, ARM::CPS2p, Convert__Imm1_0__ProcIFlags1_1, Feature_IsARM, { MCK_Imm, MCK_ProcIFlags }, }, 8034 { 138 /* cps */, ARM::tCPS, Convert__Imm1_0__ProcIFlags1_1, Feature_IsThumb, { MCK_Imm, MCK_ProcIFlags }, }, 8035 { 138 /* cps */, ARM::t2CPS2p, Convert__Imm1_0__ProcIFlags1_2, Feature_IsThumb2|Feature_IsNotMClass, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags }, }, 8036 { 138 /* cps */, ARM::CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm0_311_2, Feature_IsARM, { MCK_Imm, MCK_ProcIFlags, MCK_Imm0_31 }, }, 8037 { 138 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_1__Imm1_2, Feature_IsThumb2|Feature_IsNotMClass, { MCK_Imm, MCK_ProcIFlags, MCK_Imm }, }, 8038 { 138 /* cps */, ARM::t2CPS3p, Convert__Imm1_0__ProcIFlags1_2__Imm1_3, Feature_IsThumb2, { MCK_Imm, MCK__DOT_w, MCK_ProcIFlags, MCK_Imm }, }, 8039 { 142 /* crc32b */, ARM::t2CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8040 { 142 /* crc32b */, ARM::CRC32B, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8041 { 149 /* crc32cb */, ARM::t2CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8042 { 149 /* crc32cb */, ARM::CRC32CB, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8043 { 157 /* crc32ch */, ARM::t2CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8044 { 157 /* crc32ch */, ARM::CRC32CH, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8045 { 165 /* crc32cw */, ARM::t2CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8046 { 165 /* crc32cw */, ARM::CRC32CW, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8047 { 173 /* crc32h */, ARM::t2CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8048 { 173 /* crc32h */, ARM::CRC32H, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8049 { 180 /* crc32w */, ARM::t2CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsThumb2|Feature_HasV8|Feature_HasCRC, { MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8050 { 180 /* crc32w */, ARM::CRC32W, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_IsARM|Feature_HasV8|Feature_HasCRC, { MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8051 { 187 /* csdb */, ARM::HINT, Convert__imm_95_20__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, }, 8052 { 187 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, Feature_IsThumb2, { MCK_CondCode }, }, 8053 { 187 /* csdb */, ARM::t2HINT, Convert__imm_95_20__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 8054 { 192 /* dbg */, ARM::DBG, Convert__Imm0_151_1__CondCode2_0, Feature_IsARM|Feature_HasV7, { MCK_CondCode, MCK_Imm0_15 }, }, 8055 { 192 /* dbg */, ARM::t2DBG, Convert__Imm0_151_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_15 }, }, 8056 { 196 /* dcps1 */, ARM::t2DCPS1, Convert__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, }, 8057 { 202 /* dcps2 */, ARM::t2DCPS2, Convert__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, }, 8058 { 208 /* dcps3 */, ARM::t2DCPS3, Convert__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, }, 8059 { 214 /* dfb */, ARM::DSB, Convert__imm_95_12, Feature_IsARM|Feature_HasDFB, { }, }, 8060 { 214 /* dfb */, ARM::t2DSB, Convert__imm_95_12__CondCode2_0, Feature_HasDFB, { MCK_CondCode }, }, 8061 { 218 /* dmb */, ARM::DMB, Convert__imm_95_15, Feature_IsARM|Feature_HasDB, { }, }, 8062 { 218 /* dmb */, ARM::t2DMB, Convert__imm_95_15__CondCode2_0, Feature_HasDB, { MCK_CondCode }, }, 8063 { 218 /* dmb */, ARM::DMB, Convert__MemBarrierOpt1_0, Feature_IsARM|Feature_HasDB, { MCK_MemBarrierOpt }, }, 8064 { 218 /* dmb */, ARM::t2DMB, Convert__MemBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, }, 8065 { 222 /* dsb */, ARM::DSB, Convert__imm_95_15, Feature_IsARM|Feature_HasDB, { }, }, 8066 { 222 /* dsb */, ARM::t2DSB, Convert__imm_95_15__CondCode2_0, Feature_HasDB, { MCK_CondCode }, }, 8067 { 222 /* dsb */, ARM::DSB, Convert__MemBarrierOpt1_0, Feature_IsARM|Feature_HasDB, { MCK_MemBarrierOpt }, }, 8068 { 222 /* dsb */, ARM::t2DSB, Convert__MemBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasDB, { MCK_CondCode, MCK_MemBarrierOpt }, }, 8069 { 226 /* eor */, ARM::tEOR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8070 { 226 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8071 { 226 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 8072 { 226 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 8073 { 226 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8074 { 226 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8075 { 226 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8076 { 226 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 8077 { 226 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8078 { 226 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 8079 { 226 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 8080 { 226 /* eor */, ARM::t2EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8081 { 226 /* eor */, ARM::t2EORrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 8082 { 226 /* eor */, ARM::t2EORri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 8083 { 226 /* eor */, ARM::EORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8084 { 226 /* eor */, ARM::EORri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 8085 { 226 /* eor */, ARM::EORrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 8086 { 226 /* eor */, ARM::EORrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 8087 { 226 /* eor */, ARM::t2EORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8088 { 226 /* eor */, ARM::t2EORrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 8089 { 226 /* eor */, ARM::t2EORri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 8090 { 230 /* eret */, ARM::ERET, Convert__CondCode2_0, Feature_IsARM|Feature_HasVirtualization, { MCK_CondCode }, }, 8091 { 230 /* eret */, ARM::t2SUBS_PC_LR, Convert__imm_95_0__CondCode2_0, Feature_IsThumb2|Feature_HasVirtualization, { MCK_CondCode }, }, 8092 { 235 /* esb */, ARM::HINT, Convert__imm_95_16__CondCode2_0, Feature_IsARM|Feature_HasRAS, { MCK_CondCode }, }, 8093 { 235 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, Feature_IsThumb2|Feature_HasRAS, { MCK_CondCode }, }, 8094 { 235 /* esb */, ARM::t2HINT, Convert__imm_95_16__CondCode2_0, Feature_IsThumb2|Feature_HasRAS, { MCK_CondCode, MCK__DOT_w }, }, 8095 { 239 /* faddd */, ARM::VADDD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 8096 { 245 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, }, 8097 { 251 /* fcmpzd */, ARM::VCMPZD, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR }, }, 8098 { 258 /* fcmpzs */, ARM::VCMPZS, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR }, }, 8099 { 265 /* fconstd */, ARM::FCONSTD, Convert__Reg1_1__FPImm1_2__CondCode2_0, Feature_HasVFP3, { MCK_CondCode, MCK_DPR, MCK_FPImm }, }, 8100 { 273 /* fconsts */, ARM::FCONSTS, Convert__Reg1_1__FPImm1_2__CondCode2_0, Feature_HasVFP3, { MCK_CondCode, MCK_HPR, MCK_FPImm }, }, 8101 { 281 /* fldmdbx */, ARM::FLDMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 8102 { 289 /* fldmiax */, ARM::FLDMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 8103 { 289 /* fldmiax */, ARM::FLDMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 8104 { 297 /* fmdhr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, }, 8105 { 303 /* fmdlr */, ARM::VSETLNi32, Convert__Reg1_1__Tie0_2_2__Reg1_2__imm_95_0__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR }, }, 8106 { 309 /* fmstat */, ARM::FMSTAT, Convert__CondCode2_0, Feature_HasVFP2, { MCK_CondCode }, }, 8107 { 316 /* fstmdbx */, ARM::FSTMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 8108 { 324 /* fstmiax */, ARM::FSTMXIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 8109 { 324 /* fstmiax */, ARM::FSTMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 8110 { 332 /* fsubd */, ARM::VSUBD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 8111 { 338 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, }, 8112 { 344 /* hint */, ARM::tHINT, Convert__Imm0_151_1__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode, MCK_Imm0_15 }, }, 8113 { 344 /* hint */, ARM::HINT, Convert__Imm0_2391_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_Imm0_239 }, }, 8114 { 344 /* hint */, ARM::t2HINT, Convert__Imm0_2391_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_239 }, }, 8115 { 344 /* hint */, ARM::t2HINT, Convert__Imm0_2391_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_Imm0_239 }, }, 8116 { 349 /* hlt */, ARM::tHLT, Convert__Imm0_631_0, Feature_IsThumb|Feature_HasV8, { MCK_Imm0_63 }, }, 8117 { 349 /* hlt */, ARM::HLT, Convert__Imm0_655351_0, Feature_IsARM|Feature_HasV8, { MCK_Imm0_65535 }, }, 8118 { 353 /* hvc */, ARM::HVC, Convert__Imm0_655351_0, Feature_IsARM|Feature_HasVirtualization, { MCK_Imm0_65535 }, }, 8119 { 353 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_0, Feature_IsThumb2, { MCK_Imm0_65535 }, }, 8120 { 353 /* hvc */, ARM::t2HVC, Convert__Imm0_655351_1, Feature_IsThumb2|Feature_HasVirtualization, { MCK__DOT_w, MCK_Imm0_65535 }, }, 8121 { 357 /* isb */, ARM::ISB, Convert__imm_95_15, Feature_IsARM|Feature_HasDB, { }, }, 8122 { 357 /* isb */, ARM::t2ISB, Convert__imm_95_15__CondCode2_0, Feature_HasDB, { MCK_CondCode }, }, 8123 { 357 /* isb */, ARM::ISB, Convert__InstSyncBarrierOpt1_0, Feature_IsARM|Feature_HasDB, { MCK_InstSyncBarrierOpt }, }, 8124 { 357 /* isb */, ARM::t2ISB, Convert__InstSyncBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasDB, { MCK_CondCode, MCK_InstSyncBarrierOpt }, }, 8125 { 361 /* it */, ARM::ITasm, Convert__ITCondCode1_1__ITMask1_0, Feature_IsARM, { MCK_ITMask, MCK_ITCondCode }, }, 8126 { 361 /* it */, ARM::t2IT, Convert__ITCondCode1_1__ITMask1_0, Feature_IsThumb2, { MCK_ITMask, MCK_ITCondCode }, }, 8127 { 364 /* lda */, ARM::t2LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8128 { 364 /* lda */, ARM::LDA, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8129 { 368 /* ldab */, ARM::t2LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8130 { 368 /* ldab */, ARM::LDAB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8131 { 373 /* ldaex */, ARM::t2LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8132 { 373 /* ldaex */, ARM::LDAEX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8133 { 379 /* ldaexb */, ARM::t2LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8134 { 379 /* ldaexb */, ARM::LDAEXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8135 { 386 /* ldaexd */, ARM::LDAEXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, }, 8136 { 386 /* ldaexd */, ARM::t2LDAEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 8137 { 393 /* ldaexh */, ARM::t2LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8138 { 393 /* ldaexh */, ARM::LDAEXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8139 { 400 /* ldah */, ARM::t2LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8140 { 400 /* ldah */, ARM::LDAH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8141 { 405 /* ldc */, ARM::LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8142 { 405 /* ldc */, ARM::t2LDC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8143 { 405 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8144 { 405 /* ldc */, ARM::t2LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8145 { 405 /* ldc */, ARM::LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8146 { 405 /* ldc */, ARM::t2LDC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8147 { 405 /* ldc */, ARM::LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8148 { 405 /* ldc */, ARM::t2LDC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8149 { 409 /* ldc2 */, ARM::LDC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8150 { 409 /* ldc2 */, ARM::t2LDC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8151 { 409 /* ldc2 */, ARM::LDC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8152 { 409 /* ldc2 */, ARM::LDC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8153 { 409 /* ldc2 */, ARM::LDC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8154 { 409 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8155 { 409 /* ldc2 */, ARM::t2LDC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8156 { 409 /* ldc2 */, ARM::t2LDC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8157 { 414 /* ldc2l */, ARM::LDC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8158 { 414 /* ldc2l */, ARM::t2LDC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8159 { 414 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8160 { 414 /* ldc2l */, ARM::LDC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8161 { 414 /* ldc2l */, ARM::LDC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8162 { 414 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8163 { 414 /* ldc2l */, ARM::t2LDC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8164 { 414 /* ldc2l */, ARM::t2LDC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8165 { 420 /* ldcl */, ARM::LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8166 { 420 /* ldcl */, ARM::t2LDCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8167 { 420 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8168 { 420 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8169 { 420 /* ldcl */, ARM::LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8170 { 420 /* ldcl */, ARM::t2LDCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8171 { 420 /* ldcl */, ARM::LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8172 { 420 /* ldcl */, ARM::t2LDCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8173 { 425 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_RegList }, }, 8174 { 425 /* ldm */, ARM::LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8175 { 425 /* ldm */, ARM::t2LDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8176 { 425 /* ldm */, ARM::t2LDMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 8177 { 425 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_3, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, }, 8178 { 425 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8179 { 425 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8180 { 425 /* ldm */, ARM::sysLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 8181 { 425 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8182 { 425 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 8183 { 429 /* ldmda */, ARM::LDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8184 { 429 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8185 { 429 /* ldmda */, ARM::sysLDMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 8186 { 429 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 8187 { 435 /* ldmdb */, ARM::LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8188 { 435 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8189 { 435 /* ldmdb */, ARM::t2LDMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 8190 { 435 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8191 { 435 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8192 { 435 /* ldmdb */, ARM::sysLDMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 8193 { 435 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8194 { 435 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 8195 { 441 /* ldmib */, ARM::LDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8196 { 441 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8197 { 441 /* ldmib */, ARM::sysLDMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 8198 { 441 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 8199 { 447 /* ldr */, ARM::tLDRpci, Convert__Reg1_1__ThumbMemPC1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ThumbMemPC }, }, 8200 { 447 /* ldr */, ARM::tLDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_ConstPoolAsmImm }, }, 8201 { 447 /* ldr */, ARM::tLDRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, }, 8202 { 447 /* ldr */, ARM::tLDRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 8203 { 447 /* ldr */, ARM::tLDRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, }, 8204 { 447 /* ldr */, ARM::t2LDRpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_Imm }, }, 8205 { 447 /* ldr */, ARM::LDRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, }, 8206 { 447 /* ldr */, ARM::t2LDRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, }, 8207 { 447 /* ldr */, ARM::LDRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, }, 8208 { 447 /* ldr */, ARM::LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, }, 8209 { 447 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_1__ConstPoolAsmImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_ConstPoolAsmImm }, }, 8210 { 447 /* ldr */, ARM::t2LDRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, }, 8211 { 447 /* ldr */, ARM::t2LDRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, }, 8212 { 447 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemPCRelImm12 }, }, 8213 { 447 /* ldr */, ARM::t2LDRConstPool, Convert__Reg1_2__ConstPoolAsmImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_ConstPoolAsmImm }, }, 8214 { 447 /* ldr */, ARM::t2LDRpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_Imm }, }, 8215 { 447 /* ldr */, ARM::t2LDRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, }, 8216 { 447 /* ldr */, ARM::t2LDRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, }, 8217 { 447 /* ldr */, ARM::t2LDRpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemPCRelImm12 }, }, 8218 { 447 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 8219 { 447 /* ldr */, ARM::t2LDR_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 8220 { 447 /* ldr */, ARM::LDR_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 8221 { 447 /* ldr */, ARM::t2LDR_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 8222 { 447 /* ldr */, ARM::LDR_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 8223 { 447 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 8224 { 451 /* ldrb */, ARM::tLDRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, }, 8225 { 451 /* ldrb */, ARM::tLDRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 8226 { 451 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 8227 { 451 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 8228 { 451 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 8229 { 451 /* ldrb */, ARM::LDRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, }, 8230 { 451 /* ldrb */, ARM::t2LDRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 8231 { 451 /* ldrb */, ARM::LDRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, }, 8232 { 451 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 8233 { 451 /* ldrb */, ARM::t2LDRBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 8234 { 451 /* ldrb */, ARM::t2LDRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 8235 { 451 /* ldrb */, ARM::t2LDRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 8236 { 451 /* ldrb */, ARM::t2LDRBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 8237 { 451 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 8238 { 451 /* ldrb */, ARM::t2LDRB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 8239 { 451 /* ldrb */, ARM::LDRB_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 8240 { 451 /* ldrb */, ARM::t2LDRB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 8241 { 451 /* ldrb */, ARM::LDRB_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 8242 { 451 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 8243 { 456 /* ldrbt */, ARM::t2LDRBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 8244 { 456 /* ldrbt */, ARM::LDRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8245 { 456 /* ldrbt */, ARM::LDRBT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 8246 { 456 /* ldrbt */, ARM::LDRBT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 8247 { 462 /* ldrd */, ARM::t2LDRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, }, 8248 { 462 /* ldrd */, ARM::LDRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, }, 8249 { 462 /* ldrd */, ARM::t2LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, }, 8250 { 462 /* ldrd */, ARM::t2LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__Imm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 8251 { 462 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 8252 { 462 /* ldrd */, ARM::LDRD_POST, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__Tie2_4_4__AM3Offset2_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 8253 { 467 /* ldrex */, ARM::t2LDREX, Convert__Reg1_1__MemImm0_1020s4Offset2_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemImm0_1020s4Offset }, }, 8254 { 467 /* ldrex */, ARM::LDREX, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8255 { 473 /* ldrexb */, ARM::t2LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8256 { 473 /* ldrexb */, ARM::LDREXB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8257 { 480 /* ldrexd */, ARM::LDREXD, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRPair, MCK_MemNoOffset }, }, 8258 { 480 /* ldrexd */, ARM::t2LDREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 8259 { 487 /* ldrexh */, ARM::t2LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8260 { 487 /* ldrexh */, ARM::LDREXH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8261 { 494 /* ldrh */, ARM::tLDRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, }, 8262 { 494 /* ldrh */, ARM::tLDRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 8263 { 494 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 8264 { 494 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 8265 { 494 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 8266 { 494 /* ldrh */, ARM::t2LDRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 8267 { 494 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 8268 { 494 /* ldrh */, ARM::LDRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 8269 { 494 /* ldrh */, ARM::t2LDRHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 8270 { 494 /* ldrh */, ARM::t2LDRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 8271 { 494 /* ldrh */, ARM::t2LDRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 8272 { 494 /* ldrh */, ARM::t2LDRHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 8273 { 494 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 8274 { 494 /* ldrh */, ARM::t2LDRH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 8275 { 494 /* ldrh */, ARM::LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 8276 { 494 /* ldrh */, ARM::t2LDRH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 8277 { 499 /* ldrht */, ARM::t2LDRHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 8278 { 499 /* ldrht */, ARM::LDRHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, }, 8279 { 499 /* ldrht */, ARM::LDRHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 8280 { 505 /* ldrsb */, ARM::tLDRSB, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 8281 { 505 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 8282 { 505 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 8283 { 505 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 8284 { 505 /* ldrsb */, ARM::t2LDRSBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 8285 { 505 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 8286 { 505 /* ldrsb */, ARM::LDRSB, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 8287 { 505 /* ldrsb */, ARM::t2LDRSBpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 8288 { 505 /* ldrsb */, ARM::t2LDRSBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 8289 { 505 /* ldrsb */, ARM::t2LDRSBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 8290 { 505 /* ldrsb */, ARM::t2LDRSBpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 8291 { 505 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 8292 { 505 /* ldrsb */, ARM::t2LDRSB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 8293 { 505 /* ldrsb */, ARM::LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 8294 { 505 /* ldrsb */, ARM::t2LDRSB_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 8295 { 511 /* ldrsbt */, ARM::t2LDRSBT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 8296 { 511 /* ldrsbt */, ARM::LDRSBTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, }, 8297 { 511 /* ldrsbt */, ARM::LDRSBTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 8298 { 518 /* ldrsh */, ARM::tLDRSH, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 8299 { 518 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_1__Imm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm }, }, 8300 { 518 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 8301 { 518 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 8302 { 518 /* ldrsh */, ARM::t2LDRSHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNegImm8Offset }, }, 8303 { 518 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_1__MemPCRelImm121_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 8304 { 518 /* ldrsh */, ARM::LDRSH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 8305 { 518 /* ldrsh */, ARM::t2LDRSHpci, Convert__Reg1_2__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_Imm }, }, 8306 { 518 /* ldrsh */, ARM::t2LDRSHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemUImm12Offset }, }, 8307 { 518 /* ldrsh */, ARM::t2LDRSHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2MemRegOffset }, }, 8308 { 518 /* ldrsh */, ARM::t2LDRSHpcrel, Convert__Reg1_2__MemPCRelImm121_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_MemPCRelImm12 }, }, 8309 { 518 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 8310 { 518 /* ldrsh */, ARM::t2LDRSH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 8311 { 518 /* ldrsh */, ARM::LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 8312 { 518 /* ldrsh */, ARM::t2LDRSH_POST, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_Imm }, }, 8313 { 524 /* ldrsht */, ARM::t2LDRSHT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 8314 { 524 /* ldrsht */, ARM::LDRSHTr, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_PostIdxReg }, }, 8315 { 524 /* ldrsht */, ARM::LDRSHTi, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 8316 { 531 /* ldrt */, ARM::t2LDRT, Convert__Reg1_1__MemPosImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemPosImm8Offset }, }, 8317 { 531 /* ldrt */, ARM::LDRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8318 { 531 /* ldrt */, ARM::LDRT_POST_IMM, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 8319 { 531 /* ldrt */, ARM::LDRT_POST_REG, Convert__Reg1_1__MemNoOffset1_2__Tie1_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 8320 { 536 /* lsl */, ARM::tLSLrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8321 { 536 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_2__Imm0_311_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_31 }, }, 8322 { 536 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8323 { 536 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_2__Imm1_311_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm1_31 }, }, 8324 { 536 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 8325 { 536 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, }, 8326 { 536 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8327 { 536 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm1_31 }, }, 8328 { 536 /* lsl */, ARM::tLSLri, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_311_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_31 }, }, 8329 { 536 /* lsl */, ARM::t2LSLrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8330 { 536 /* lsl */, ARM::t2LSLri, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, }, 8331 { 536 /* lsl */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK__35_0 }, }, 8332 { 536 /* lsl */, ARM::LSLr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8333 { 536 /* lsl */, ARM::LSLi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, }, 8334 { 536 /* lsl */, ARM::t2LSLrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8335 { 536 /* lsl */, ARM::t2LSLri, Convert__Reg1_3__Reg1_4__Imm1_311_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm1_31 }, }, 8336 { 536 /* lsl */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK__35_0 }, }, 8337 { 540 /* lsr */, ARM::tLSRrr, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8338 { 540 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_2__ImmThumbSR1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ImmThumbSR }, }, 8339 { 540 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8340 { 540 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_2__ImmThumbSR1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ImmThumbSR }, }, 8341 { 540 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 8342 { 540 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_2__Imm0_321_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_32 }, }, 8343 { 540 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8344 { 540 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_ImmThumbSR }, }, 8345 { 540 /* lsr */, ARM::tLSRri, Convert__Reg1_2__CCOut1_0__Reg1_3__ImmThumbSR1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ImmThumbSR }, }, 8346 { 540 /* lsr */, ARM::t2LSRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8347 { 540 /* lsr */, ARM::t2LSRri, Convert__Reg1_2__Reg1_3__ImmThumbSR1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 8348 { 540 /* lsr */, ARM::LSRr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8349 { 540 /* lsr */, ARM::LSRi, Convert__Reg1_2__Reg1_3__Imm0_321_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_32 }, }, 8350 { 540 /* lsr */, ARM::t2LSRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8351 { 540 /* lsr */, ARM::t2LSRri, Convert__Reg1_3__Reg1_4__ImmThumbSR1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_ImmThumbSR }, }, 8352 { 544 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 8353 { 544 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 8354 { 544 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 8355 { 544 /* mcr */, ARM::t2MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 8356 { 548 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__imm_95_0, Feature_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 8357 { 548 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg }, }, 8358 { 548 /* mcr2 */, ARM::MCR2, Convert__CoprocNum1_0__Imm0_71_1__Reg1_2__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 8359 { 548 /* mcr2 */, ARM::t2MCR2, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 8360 { 553 /* mcrr */, ARM::MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 8361 { 553 /* mcrr */, ARM::t2MCRR, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 8362 { 558 /* mcrr2 */, ARM::MCRR2, Convert__CoprocNum1_0__Imm0_151_1__Reg1_2__Reg1_3__CoprocReg1_4, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 8363 { 558 /* mcrr2 */, ARM::t2MCRR2, Convert__CoprocNum1_1__Imm0_151_2__Reg1_3__Reg1_4__CoprocReg1_5__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 8364 { 564 /* mla */, ARM::t2MLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8365 { 564 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8366 { 564 /* mla */, ARM::MLA, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8367 { 568 /* mls */, ARM::t2MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8368 { 568 /* mls */, ARM::MLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8369 { 572 /* mov */, ARM::MOVPCLR, Convert__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_PC, MCK_LR }, }, 8370 { 572 /* mov */, ARM::t2MOVi16, Convert__Reg1_1__Imm256_65535Expr1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm256_65535Expr }, }, 8371 { 572 /* mov */, ARM::t2MOVsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 8372 { 572 /* mov */, ARM::t2MOVsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, }, 8373 { 572 /* mov */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__reg0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 8374 { 572 /* mov */, ARM::t2MVNi, Convert__Reg1_1__T2SOImmNot1_2__CondCode2_0__reg0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 8375 { 572 /* mov */, ARM::tMOVr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8376 { 572 /* mov */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, }, 8377 { 572 /* mov */, ARM::MOVr_TC, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_tcGPR, MCK_tcGPR }, }, 8378 { 572 /* mov */, ARM::tMOVi8, Convert__Reg1_2__CCOut1_0__Imm0_2551_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 8379 { 572 /* mov */, ARM::MVNi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, }, 8380 { 572 /* mov */, ARM::MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 8381 { 572 /* mov */, ARM::MOVr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8382 { 572 /* mov */, ARM::MOVi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8383 { 572 /* mov */, ARM::MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8384 { 572 /* mov */, ARM::t2MOVsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 8385 { 572 /* mov */, ARM::t2MOVsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, }, 8386 { 572 /* mov */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__reg0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 8387 { 572 /* mov */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__reg0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, }, 8388 { 572 /* mov */, ARM::t2MOVi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 8389 { 572 /* mov */, ARM::t2MOVr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, }, 8390 { 576 /* movs */, ARM::tMOVSr, Convert__Reg1_0__Reg1_1, Feature_IsThumb, { MCK_tGPR, MCK_tGPR }, }, 8391 { 576 /* movs */, ARM::tMOVi8, Convert__Reg1_0__regCPSR__Imm0_2551_1__imm_95_14__imm_95_0, Feature_IsThumb, { MCK_tGPR, MCK_Imm0_255 }, }, 8392 { 576 /* movs */, ARM::t2MOVSsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 8393 { 576 /* movs */, ARM::t2MOVSsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_RegShiftedReg }, }, 8394 { 576 /* movs */, ARM::t2MOVi, Convert__Reg1_1__T2SOImm1_2__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 8395 { 576 /* movs */, ARM::t2MOVr, Convert__Reg1_1__Reg1_2__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 8396 { 576 /* movs */, ARM::t2MOVSsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 8397 { 576 /* movs */, ARM::t2MOVSsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedReg }, }, 8398 { 576 /* movs */, ARM::t2MOVi, Convert__Reg1_2__T2SOImm1_3__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 8399 { 576 /* movs */, ARM::t2MOVr, Convert__Reg1_2__Reg1_3__CondCode2_0__regCPSR, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc }, }, 8400 { 581 /* movt */, ARM::t2MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, }, 8401 { 581 /* movt */, ARM::MOVTi16, Convert__Reg1_1__Tie0_1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_65535Expr }, }, 8402 { 586 /* movw */, ARM::t2MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_Imm0_65535Expr }, }, 8403 { 586 /* movw */, ARM::MOVi16, Convert__Reg1_1__Imm0_65535Expr1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_Imm0_65535Expr }, }, 8404 { 591 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 8405 { 591 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 8406 { 591 /* mrc */, ARM::MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 8407 { 591 /* mrc */, ARM::t2MRC, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 8408 { 595 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__imm_95_0, Feature_IsARM, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 8409 { 595 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg }, }, 8410 { 595 /* mrc2 */, ARM::MRC2, Convert__Reg1_2__CoprocNum1_0__Imm0_71_1__CoprocReg1_3__CoprocReg1_4__Imm0_71_5, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 8411 { 595 /* mrc2 */, ARM::t2MRC2, Convert__Reg1_3__CoprocNum1_1__Imm0_71_2__CoprocReg1_4__CoprocReg1_5__Imm0_71_6__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_7, MCK_GPRwithAPSR, MCK_CoprocReg, MCK_CoprocReg, MCK_Imm0_7 }, }, 8412 { 600 /* mrrc */, ARM::MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 8413 { 600 /* mrrc */, ARM::t2MRRC, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 8414 { 605 /* mrrc2 */, ARM::MRRC2, Convert__Reg1_2__Reg1_3__CoprocNum1_0__Imm0_151_1__CoprocReg1_4, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_Imm0_15, MCK_GPRnopc, MCK_GPRnopc, MCK_CoprocReg }, }, 8415 { 605 /* mrrc2 */, ARM::t2MRRC2, Convert__Reg1_3__Reg1_4__CoprocNum1_1__Imm0_151_2__CoprocReg1_5__CondCode2_0, Feature_IsThumb2|Feature_PreV8, { MCK_CondCode, MCK_CoprocNum, MCK_Imm0_15, MCK_GPR, MCK_GPR, MCK_CoprocReg }, }, 8416 { 611 /* mrs */, ARM::t2MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, Feature_IsThumb|Feature_HasVirtualization, { MCK_CondCode, MCK_rGPR, MCK_BankedReg }, }, 8417 { 611 /* mrs */, ARM::t2MRS_M, Convert__Reg1_1__MSRMask1_2__CondCode2_0, Feature_IsThumb|Feature_IsMClass, { MCK_CondCode, MCK_rGPR, MCK_MSRMask }, }, 8418 { 611 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_APSR }, }, 8419 { 611 /* mrs */, ARM::MRS, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_CCR }, }, 8420 { 611 /* mrs */, ARM::MRSsys, Convert__Reg1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_SPSR }, }, 8421 { 611 /* mrs */, ARM::MRSbanked, Convert__Reg1_1__BankedReg1_2__CondCode2_0, Feature_IsARM|Feature_HasVirtualization, { MCK_CondCode, MCK_GPRnopc, MCK_BankedReg }, }, 8422 { 611 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_APSR }, }, 8423 { 611 /* mrs */, ARM::t2MRS_AR, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_CCR }, }, 8424 { 611 /* mrs */, ARM::t2MRSsys_AR, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK_SPSR }, }, 8425 { 615 /* msr */, ARM::t2MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_rGPR }, }, 8426 { 615 /* msr */, ARM::MSRbanked, Convert__BankedReg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasVirtualization, { MCK_CondCode, MCK_BankedReg, MCK_GPRnopc }, }, 8427 { 615 /* msr */, ARM::t2MSR_AR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, }, 8428 { 615 /* msr */, ARM::t2MSR_M, Convert__MSRMask1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_IsMClass, { MCK_CondCode, MCK_MSRMask, MCK_rGPR }, }, 8429 { 615 /* msr */, ARM::MSR, Convert__MSRMask1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_GPR }, }, 8430 { 615 /* msr */, ARM::MSRi, Convert__MSRMask1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_MSRMask, MCK_ModImm }, }, 8431 { 619 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8432 { 619 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8433 { 619 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 8434 { 619 /* mul */, ARM::t2MUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8435 { 619 /* mul */, ARM::tMUL, ConvertCustom_cvtThumbMultiply, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, }, 8436 { 619 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8437 { 619 /* mul */, ARM::MUL, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8438 { 623 /* mvn */, ARM::tMVN, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8439 { 623 /* mvn */, ARM::t2MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8440 { 623 /* mvn */, ARM::MOVi, Convert__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_ModImmNot }, }, 8441 { 623 /* mvn */, ARM::t2MVNs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 8442 { 623 /* mvn */, ARM::t2MVNi, Convert__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 8443 { 623 /* mvn */, ARM::t2MOVi, Convert__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 8444 { 623 /* mvn */, ARM::MVNsr, Convert__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 8445 { 623 /* mvn */, ARM::MVNr, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8446 { 623 /* mvn */, ARM::MVNi, Convert__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8447 { 623 /* mvn */, ARM::MVNsi, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8448 { 623 /* mvn */, ARM::t2MVNr, Convert__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8449 { 623 /* mvn */, ARM::t2MVNs, Convert__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 8450 { 623 /* mvn */, ARM::t2MVNi, Convert__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 8451 { 627 /* neg */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8452 { 627 /* neg */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8453 { 627 /* neg */, ARM::RSBri, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8454 { 631 /* nop */, ARM::tMOVr, Convert__regR8__regR8__imm_95_14__imm_95_0, Feature_IsThumb, { }, }, 8455 { 631 /* nop */, ARM::HINT, Convert__imm_95_0__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, }, 8456 { 631 /* nop */, ARM::tHINT, Convert__imm_95_0__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, }, 8457 { 631 /* nop */, ARM::MOVr, Convert__regR0__regR0__CondCode2_0__reg0, Feature_IsARM, { MCK_CondCode }, }, 8458 { 631 /* nop */, ARM::t2HINT, Convert__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 8459 { 635 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8460 { 635 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 8461 { 635 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 8462 { 635 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 8463 { 635 /* orn */, ARM::t2ORNrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8464 { 635 /* orn */, ARM::t2ORNrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 8465 { 635 /* orn */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 8466 { 635 /* orn */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 8467 { 639 /* orr */, ARM::tORR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8468 { 639 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8469 { 639 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 8470 { 639 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 8471 { 639 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_2__T2SOImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImmNot }, }, 8472 { 639 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8473 { 639 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8474 { 639 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8475 { 639 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 8476 { 639 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8477 { 639 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_RegShiftedImm }, }, 8478 { 639 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2SOImm }, }, 8479 { 639 /* orr */, ARM::t2ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8480 { 639 /* orr */, ARM::t2ORRrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 8481 { 639 /* orr */, ARM::t2ORRri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 8482 { 639 /* orr */, ARM::t2ORNri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 8483 { 639 /* orr */, ARM::ORRrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8484 { 639 /* orr */, ARM::ORRri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 8485 { 639 /* orr */, ARM::ORRrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 8486 { 639 /* orr */, ARM::ORRrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 8487 { 639 /* orr */, ARM::t2ORRrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8488 { 639 /* orr */, ARM::t2ORRrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 8489 { 639 /* orr */, ARM::t2ORRri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 8490 { 643 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8491 { 643 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8492 { 643 /* pkhbt */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHLSLImm }, }, 8493 { 643 /* pkhbt */, ARM::PKHBT, Convert__Reg1_1__Reg1_2__Reg1_3__PKHLSLImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHLSLImm }, }, 8494 { 649 /* pkhtb */, ARM::t2PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8495 { 649 /* pkhtb */, ARM::PKHBT, Convert__Reg1_1__Reg1_3__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8496 { 649 /* pkhtb */, ARM::t2PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_PKHASRImm }, }, 8497 { 649 /* pkhtb */, ARM::PKHTB, Convert__Reg1_1__Reg1_2__Reg1_3__PKHASRImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_PKHASRImm }, }, 8498 { 655 /* pld */, ARM::PLDi12, Convert__MemImm12Offset2_0, Feature_IsARM, { MCK_MemImm12Offset }, }, 8499 { 655 /* pld */, ARM::PLDrs, Convert__MemRegOffset3_0, Feature_IsARM, { MCK_MemRegOffset }, }, 8500 { 655 /* pld */, ARM::t2PLDpci, Convert__Imm1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm }, }, 8501 { 655 /* pld */, ARM::t2PLDi8, Convert__MemNegImm8Offset2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemNegImm8Offset }, }, 8502 { 655 /* pld */, ARM::t2PLDi12, Convert__MemUImm12Offset2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemUImm12Offset }, }, 8503 { 655 /* pld */, ARM::t2PLDs, Convert__T2MemRegOffset3_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_T2MemRegOffset }, }, 8504 { 655 /* pld */, ARM::t2PLDpci, Convert__MemPCRelImm121_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemPCRelImm12 }, }, 8505 { 659 /* pldw */, ARM::PLDWi12, Convert__MemImm12Offset2_0, Feature_IsARM|Feature_HasV7|Feature_HasMP, { MCK_MemImm12Offset }, }, 8506 { 659 /* pldw */, ARM::PLDWrs, Convert__MemRegOffset3_0, Feature_IsARM|Feature_HasV7|Feature_HasMP, { MCK_MemRegOffset }, }, 8507 { 659 /* pldw */, ARM::t2PLDWi8, Convert__MemNegImm8Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7|Feature_HasMP, { MCK_CondCode, MCK_MemNegImm8Offset }, }, 8508 { 659 /* pldw */, ARM::t2PLDWi12, Convert__MemUImm12Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7|Feature_HasMP, { MCK_CondCode, MCK_MemUImm12Offset }, }, 8509 { 659 /* pldw */, ARM::t2PLDWs, Convert__T2MemRegOffset3_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7|Feature_HasMP, { MCK_CondCode, MCK_T2MemRegOffset }, }, 8510 { 664 /* pli */, ARM::PLIi12, Convert__MemImm12Offset2_0, Feature_IsARM|Feature_HasV7, { MCK_MemImm12Offset }, }, 8511 { 664 /* pli */, ARM::PLIrs, Convert__MemRegOffset3_0, Feature_IsARM|Feature_HasV7, { MCK_MemRegOffset }, }, 8512 { 664 /* pli */, ARM::t2PLIpci, Convert__Imm1_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_Imm }, }, 8513 { 664 /* pli */, ARM::t2PLIi8, Convert__MemNegImm8Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_MemNegImm8Offset }, }, 8514 { 664 /* pli */, ARM::t2PLIi12, Convert__MemUImm12Offset2_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_MemUImm12Offset }, }, 8515 { 664 /* pli */, ARM::t2PLIs, Convert__T2MemRegOffset3_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_T2MemRegOffset }, }, 8516 { 664 /* pli */, ARM::t2PLIpci, Convert__MemPCRelImm121_1__CondCode2_0, Feature_IsThumb2|Feature_HasV7, { MCK_CondCode, MCK_MemPCRelImm12 }, }, 8517 { 668 /* pop */, ARM::tPOP, Convert__CondCode2_0__RegList1_1, Feature_IsThumb, { MCK_CondCode, MCK_RegList }, }, 8518 { 668 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, Feature_IsThumb2, { MCK_CondCode, MCK_RegList }, }, 8519 { 668 /* pop */, ARM::LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, Feature_IsARM, { MCK_CondCode, MCK_RegList }, }, 8520 { 668 /* pop */, ARM::t2LDMIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, }, 8521 { 672 /* push */, ARM::tPUSH, Convert__CondCode2_0__RegList1_1, Feature_IsThumb, { MCK_CondCode, MCK_RegList }, }, 8522 { 672 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, Feature_IsThumb2, { MCK_CondCode, MCK_RegList }, }, 8523 { 672 /* push */, ARM::STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_1, Feature_IsARM, { MCK_CondCode, MCK_RegList }, }, 8524 { 672 /* push */, ARM::t2STMDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_RegList }, }, 8525 { 677 /* qadd */, ARM::t2QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8526 { 677 /* qadd */, ARM::QADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8527 { 682 /* qadd16 */, ARM::t2QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8528 { 682 /* qadd16 */, ARM::QADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8529 { 689 /* qadd8 */, ARM::t2QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8530 { 689 /* qadd8 */, ARM::QADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8531 { 695 /* qasx */, ARM::t2QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8532 { 695 /* qasx */, ARM::QASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8533 { 700 /* qdadd */, ARM::t2QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8534 { 700 /* qdadd */, ARM::QDADD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8535 { 706 /* qdsub */, ARM::t2QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8536 { 706 /* qdsub */, ARM::QDSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8537 { 712 /* qsax */, ARM::t2QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8538 { 712 /* qsax */, ARM::QSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8539 { 717 /* qsub */, ARM::t2QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8540 { 717 /* qsub */, ARM::QSUB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8541 { 722 /* qsub16 */, ARM::t2QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8542 { 722 /* qsub16 */, ARM::QSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8543 { 729 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8544 { 729 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8545 { 735 /* rbit */, ARM::t2RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8546 { 735 /* rbit */, ARM::RBIT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8547 { 740 /* rev */, ARM::tREV, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8548 { 740 /* rev */, ARM::t2REV, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8549 { 740 /* rev */, ARM::REV, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8550 { 740 /* rev */, ARM::t2REV, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8551 { 744 /* rev16 */, ARM::tREV16, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8552 { 744 /* rev16 */, ARM::t2REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8553 { 744 /* rev16 */, ARM::REV16, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8554 { 744 /* rev16 */, ARM::t2REV16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8555 { 750 /* revsh */, ARM::tREVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8556 { 750 /* revsh */, ARM::t2REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8557 { 750 /* revsh */, ARM::REVSH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8558 { 750 /* revsh */, ARM::t2REVSH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8559 { 756 /* rfeda */, ARM::RFEDA, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, }, 8560 { 756 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 8561 { 762 /* rfedb */, ARM::RFEDB, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, }, 8562 { 762 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 8563 { 762 /* rfedb */, ARM::t2RFEDB, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR }, }, 8564 { 762 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, }, 8565 { 768 /* rfeia */, ARM::RFEIA, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, }, 8566 { 768 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 8567 { 768 /* rfeia */, ARM::t2RFEIA, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR }, }, 8568 { 768 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, }, 8569 { 774 /* rfeib */, ARM::RFEIB, Convert__Reg1_0, Feature_IsARM, { MCK_GPR }, }, 8570 { 774 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, Feature_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, }, 8571 { 780 /* ror */, ARM::tROR, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8572 { 780 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8573 { 780 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_Imm0_31 }, }, 8574 { 780 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 8575 { 780 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_2__Imm0_311_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_Imm0_31 }, }, 8576 { 780 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8577 { 780 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_Imm0_31 }, }, 8578 { 780 /* ror */, ARM::t2RORrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8579 { 780 /* ror */, ARM::t2RORri, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31 }, }, 8580 { 780 /* ror */, ARM::RORr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8581 { 780 /* ror */, ARM::RORi, Convert__Reg1_2__Reg1_3__Imm0_311_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_Imm0_31 }, }, 8582 { 780 /* ror */, ARM::t2RORrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8583 { 780 /* ror */, ARM::t2RORri, Convert__Reg1_3__Reg1_4__Imm0_311_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_Imm0_31 }, }, 8584 { 784 /* rrx */, ARM::t2RRX, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8585 { 784 /* rrx */, ARM::RRXi, Convert__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8586 { 788 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8587 { 788 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_RegShiftedImm }, }, 8588 { 788 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_T2SOImm }, }, 8589 { 788 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8590 { 788 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8591 { 788 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8592 { 788 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 8593 { 788 /* rsb */, ARM::tRSB, Convert__Reg1_2__CCOut1_0__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK__35_0 }, }, 8594 { 788 /* rsb */, ARM::t2RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8595 { 788 /* rsb */, ARM::t2RSBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 8596 { 788 /* rsb */, ARM::t2RSBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 8597 { 788 /* rsb */, ARM::RSBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8598 { 788 /* rsb */, ARM::RSBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 8599 { 788 /* rsb */, ARM::RSBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 8600 { 788 /* rsb */, ARM::RSBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 8601 { 788 /* rsb */, ARM::t2RSBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 8602 { 792 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8603 { 792 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8604 { 792 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8605 { 792 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 8606 { 792 /* rsc */, ARM::RSCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8607 { 792 /* rsc */, ARM::RSCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 8608 { 792 /* rsc */, ARM::RSCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 8609 { 792 /* rsc */, ARM::RSCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 8610 { 796 /* sadd16 */, ARM::t2SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8611 { 796 /* sadd16 */, ARM::SADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8612 { 803 /* sadd8 */, ARM::t2SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8613 { 803 /* sadd8 */, ARM::SADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8614 { 809 /* sasx */, ARM::t2SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8615 { 809 /* sasx */, ARM::SASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8616 { 814 /* sbc */, ARM::tSBC, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8617 { 814 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 8618 { 814 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8619 { 814 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8620 { 814 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, }, 8621 { 814 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8622 { 814 /* sbc */, ARM::t2SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8623 { 814 /* sbc */, ARM::t2SBCrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 8624 { 814 /* sbc */, ARM::t2SBCri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImm }, }, 8625 { 814 /* sbc */, ARM::t2ADCri, Convert__Reg1_2__Reg1_3__T2SOImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_T2SOImmNot }, }, 8626 { 814 /* sbc */, ARM::SBCrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedReg }, }, 8627 { 814 /* sbc */, ARM::SBCrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8628 { 814 /* sbc */, ARM::SBCri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 8629 { 814 /* sbc */, ARM::ADCri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, }, 8630 { 814 /* sbc */, ARM::SBCrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 8631 { 814 /* sbc */, ARM::t2SBCrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8632 { 814 /* sbc */, ARM::t2SBCrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RegShiftedImm }, }, 8633 { 818 /* sbfx */, ARM::t2SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, }, 8634 { 818 /* sbfx */, ARM::SBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, }, 8635 { 823 /* sdiv */, ARM::t2SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasDivideInThumb|Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8636 { 823 /* sdiv */, ARM::SDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8637 { 828 /* sel */, ARM::SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8638 { 828 /* sel */, ARM::t2SEL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8639 { 832 /* setend */, ARM::tSETEND, Convert__SetEndImm1_0, Feature_IsThumb|Feature_IsNotMClass, { MCK_SetEndImm }, }, 8640 { 832 /* setend */, ARM::SETEND, Convert__SetEndImm1_0, Feature_IsARM, { MCK_SetEndImm }, }, 8641 { 839 /* setpan */, ARM::SETPAN, Convert__Imm0_11_0, Feature_IsARM|Feature_HasV8|Feature_HasV8_1a, { MCK_Imm0_1 }, }, 8642 { 839 /* setpan */, ARM::t2SETPAN, Convert__Imm0_11_0, Feature_IsThumb2|Feature_HasV8|Feature_HasV8_1a, { MCK_Imm0_1 }, }, 8643 { 846 /* sev */, ARM::HINT, Convert__imm_95_4__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, }, 8644 { 846 /* sev */, ARM::tHINT, Convert__imm_95_4__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, }, 8645 { 846 /* sev */, ARM::t2HINT, Convert__imm_95_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 8646 { 850 /* sevl */, ARM::HINT, Convert__imm_95_5__CondCode2_0, Feature_IsARM|Feature_HasV8, { MCK_CondCode }, }, 8647 { 850 /* sevl */, ARM::tHINT, Convert__imm_95_5__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode }, }, 8648 { 850 /* sevl */, ARM::t2HINT, Convert__imm_95_5__CondCode2_0, Feature_IsThumb2|Feature_HasV8, { MCK_CondCode, MCK__DOT_w }, }, 8649 { 855 /* sg */, ARM::t2SG, Convert__CondCode2_0, Feature_Has8MSecExt, { MCK_CondCode }, }, 8650 { 858 /* sha1c */, ARM::SHA1C, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 8651 { 864 /* sha1h */, ARM::SHA1H, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 8652 { 870 /* sha1m */, ARM::SHA1M, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 8653 { 876 /* sha1p */, ARM::SHA1P, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 8654 { 882 /* sha1su0 */, ARM::SHA1SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 8655 { 890 /* sha1su1 */, ARM::SHA1SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 8656 { 898 /* sha256h */, ARM::SHA256H, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 8657 { 906 /* sha256h2 */, ARM::SHA256H2, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 8658 { 915 /* sha256su0 */, ARM::SHA256SU0, Convert__Reg1_1__Tie0_1_1__Reg1_2, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 8659 { 925 /* sha256su1 */, ARM::SHA256SU1, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 8660 { 935 /* shadd16 */, ARM::t2SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8661 { 935 /* shadd16 */, ARM::SHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8662 { 943 /* shadd8 */, ARM::t2SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8663 { 943 /* shadd8 */, ARM::SHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8664 { 950 /* shasx */, ARM::t2SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8665 { 950 /* shasx */, ARM::SHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8666 { 956 /* shsax */, ARM::t2SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8667 { 956 /* shsax */, ARM::SHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8668 { 962 /* shsub16 */, ARM::t2SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8669 { 962 /* shsub16 */, ARM::SHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8670 { 970 /* shsub8 */, ARM::t2SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8671 { 970 /* shsub8 */, ARM::SHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8672 { 977 /* smc */, ARM::SMC, Convert__Imm0_151_1__CondCode2_0, Feature_IsARM|Feature_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, }, 8673 { 977 /* smc */, ARM::t2SMC, Convert__Imm0_151_1__CondCode2_0, Feature_IsThumb2|Feature_HasTrustZone, { MCK_CondCode, MCK_Imm0_15 }, }, 8674 { 981 /* smlabb */, ARM::t2SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8675 { 981 /* smlabb */, ARM::SMLABB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8676 { 988 /* smlabt */, ARM::t2SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8677 { 988 /* smlabt */, ARM::SMLABT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8678 { 995 /* smlad */, ARM::t2SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8679 { 995 /* smlad */, ARM::SMLAD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8680 { 1001 /* smladx */, ARM::t2SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8681 { 1001 /* smladx */, ARM::SMLADX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8682 { 1008 /* smlal */, ARM::t2SMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8683 { 1008 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8684 { 1008 /* smlal */, ARM::SMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8685 { 1014 /* smlalbb */, ARM::t2SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8686 { 1014 /* smlalbb */, ARM::SMLALBB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8687 { 1022 /* smlalbt */, ARM::t2SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8688 { 1022 /* smlalbt */, ARM::SMLALBT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8689 { 1030 /* smlald */, ARM::t2SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8690 { 1030 /* smlald */, ARM::SMLALD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8691 { 1037 /* smlaldx */, ARM::t2SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8692 { 1037 /* smlaldx */, ARM::SMLALDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8693 { 1045 /* smlaltb */, ARM::t2SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8694 { 1045 /* smlaltb */, ARM::SMLALTB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8695 { 1053 /* smlaltt */, ARM::t2SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8696 { 1053 /* smlaltt */, ARM::SMLALTT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8697 { 1061 /* smlatb */, ARM::t2SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8698 { 1061 /* smlatb */, ARM::SMLATB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8699 { 1068 /* smlatt */, ARM::t2SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8700 { 1068 /* smlatt */, ARM::SMLATT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8701 { 1075 /* smlawb */, ARM::t2SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8702 { 1075 /* smlawb */, ARM::SMLAWB, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8703 { 1082 /* smlawt */, ARM::t2SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8704 { 1082 /* smlawt */, ARM::SMLAWT, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8705 { 1089 /* smlsd */, ARM::t2SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8706 { 1089 /* smlsd */, ARM::SMLSD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8707 { 1095 /* smlsdx */, ARM::t2SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8708 { 1095 /* smlsdx */, ARM::SMLSDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPR }, }, 8709 { 1102 /* smlsld */, ARM::t2SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8710 { 1102 /* smlsld */, ARM::SMLSLD, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8711 { 1109 /* smlsldx */, ARM::t2SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8712 { 1109 /* smlsldx */, ARM::SMLSLDX, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8713 { 1117 /* smmla */, ARM::t2SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8714 { 1117 /* smmla */, ARM::SMMLA, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8715 { 1123 /* smmlar */, ARM::t2SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8716 { 1123 /* smmlar */, ARM::SMMLAR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8717 { 1130 /* smmls */, ARM::t2SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8718 { 1130 /* smmls */, ARM::SMMLS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8719 { 1136 /* smmlsr */, ARM::t2SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8720 { 1136 /* smmlsr */, ARM::SMMLSR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8721 { 1143 /* smmul */, ARM::t2SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8722 { 1143 /* smmul */, ARM::SMMUL, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8723 { 1149 /* smmulr */, ARM::t2SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8724 { 1149 /* smmulr */, ARM::SMMULR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8725 { 1156 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8726 { 1156 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8727 { 1162 /* smuadx */, ARM::t2SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8728 { 1162 /* smuadx */, ARM::SMUADX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8729 { 1169 /* smulbb */, ARM::t2SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8730 { 1169 /* smulbb */, ARM::SMULBB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8731 { 1176 /* smulbt */, ARM::t2SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8732 { 1176 /* smulbt */, ARM::SMULBT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8733 { 1183 /* smull */, ARM::t2SMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8734 { 1183 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8735 { 1183 /* smull */, ARM::SMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8736 { 1189 /* smultb */, ARM::t2SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8737 { 1189 /* smultb */, ARM::SMULTB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8738 { 1196 /* smultt */, ARM::t2SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8739 { 1196 /* smultt */, ARM::SMULTT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8740 { 1203 /* smulwb */, ARM::t2SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8741 { 1203 /* smulwb */, ARM::SMULWB, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8742 { 1210 /* smulwt */, ARM::t2SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8743 { 1210 /* smulwt */, ARM::SMULWT, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8744 { 1217 /* smusd */, ARM::t2SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8745 { 1217 /* smusd */, ARM::SMUSD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8746 { 1223 /* smusdx */, ARM::t2SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8747 { 1223 /* smusdx */, ARM::SMUSDX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8748 { 1230 /* srsda */, ARM::SRSDA, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, }, 8749 { 1230 /* srsda */, ARM::SRSDA, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 8750 { 1230 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 8751 { 1230 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 8752 { 1236 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, }, 8753 { 1236 /* srsdb */, ARM::SRSDB, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 8754 { 1236 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, }, 8755 { 1236 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 8756 { 1236 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 8757 { 1236 /* srsdb */, ARM::t2SRSDB, Convert__Imm0_311_2__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, }, 8758 { 1236 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, }, 8759 { 1236 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 8760 { 1242 /* srsia */, ARM::SRSIA, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, }, 8761 { 1242 /* srsia */, ARM::SRSIA, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 8762 { 1242 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31 }, }, 8763 { 1242 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 8764 { 1242 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 8765 { 1242 /* srsia */, ARM::t2SRSIA, Convert__Imm0_311_2__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_31 }, }, 8766 { 1242 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, }, 8767 { 1242 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 8768 { 1248 /* srsib */, ARM::SRSIB, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31 }, }, 8769 { 1248 /* srsib */, ARM::SRSIB, Convert__Imm0_311_1, Feature_IsARM, { MCK_GPRsp, MCK_Imm0_31 }, }, 8770 { 1248 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, Feature_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, }, 8771 { 1248 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, Feature_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, }, 8772 { 1254 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR }, }, 8773 { 1254 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc }, }, 8774 { 1254 /* ssat */, ARM::t2SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm1_32, MCK_rGPR, MCK_ShifterImm }, }, 8775 { 1254 /* ssat */, ARM::SSAT, Convert__Reg1_1__Imm1_321_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_32, MCK_GPRnopc, MCK_ShifterImm }, }, 8776 { 1259 /* ssat16 */, ARM::t2SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm1_16, MCK_rGPR }, }, 8777 { 1259 /* ssat16 */, ARM::SSAT16, Convert__Reg1_1__Imm1_161_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm1_16, MCK_GPRnopc }, }, 8778 { 1266 /* ssax */, ARM::t2SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8779 { 1266 /* ssax */, ARM::SSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8780 { 1271 /* ssub16 */, ARM::t2SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8781 { 1271 /* ssub16 */, ARM::SSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8782 { 1278 /* ssub8 */, ARM::t2SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8783 { 1278 /* ssub8 */, ARM::SSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 8784 { 1284 /* stc */, ARM::STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8785 { 1284 /* stc */, ARM::t2STC_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8786 { 1284 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8787 { 1284 /* stc */, ARM::t2STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8788 { 1284 /* stc */, ARM::STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8789 { 1284 /* stc */, ARM::t2STC_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8790 { 1284 /* stc */, ARM::STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8791 { 1284 /* stc */, ARM::t2STC_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8792 { 1288 /* stc2 */, ARM::STC2_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8793 { 1288 /* stc2 */, ARM::t2STC2_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8794 { 1288 /* stc2 */, ARM::STC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8795 { 1288 /* stc2 */, ARM::STC2_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8796 { 1288 /* stc2 */, ARM::STC2_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8797 { 1288 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8798 { 1288 /* stc2 */, ARM::t2STC2_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8799 { 1288 /* stc2 */, ARM::t2STC2_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8800 { 1293 /* stc2l */, ARM::STC2L_OFFSET, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8801 { 1293 /* stc2l */, ARM::t2STC2L_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8802 { 1293 /* stc2l */, ARM::STC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8803 { 1293 /* stc2l */, ARM::STC2L_OPTION, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__CoprocOption1_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8804 { 1293 /* stc2l */, ARM::STC2L_POST, Convert__CoprocNum1_0__CoprocReg1_1__MemNoOffset1_2__PostIdxImm8s41_3, Feature_IsARM|Feature_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8805 { 1293 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8806 { 1293 /* stc2l */, ARM::t2STC2L_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8807 { 1293 /* stc2l */, ARM::t2STC2L_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_PreV8|Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8808 { 1299 /* stcl */, ARM::STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8809 { 1299 /* stcl */, ARM::t2STCL_OFFSET, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5 }, }, 8810 { 1299 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8811 { 1299 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, }, 8812 { 1299 /* stcl */, ARM::STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8813 { 1299 /* stcl */, ARM::t2STCL_OPTION, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__CoprocOption1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_CoprocOption }, }, 8814 { 1299 /* stcl */, ARM::STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8815 { 1299 /* stcl */, ARM::t2STCL_POST, Convert__CoprocNum1_1__CoprocReg1_2__MemNoOffset1_3__PostIdxImm8s41_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_MemNoOffset, MCK_PostIdxImm8s4 }, }, 8816 { 1304 /* stl */, ARM::t2STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8817 { 1304 /* stl */, ARM::STL, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8818 { 1308 /* stlb */, ARM::t2STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8819 { 1308 /* stlb */, ARM::STLB, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8820 { 1313 /* stlex */, ARM::t2STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 8821 { 1313 /* stlex */, ARM::STLEX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 8822 { 1319 /* stlexb */, ARM::t2STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 8823 { 1319 /* stlexb */, ARM::STLEXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 8824 { 1326 /* stlexd */, ARM::STLEXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, }, 8825 { 1326 /* stlexd */, ARM::t2STLEXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 8826 { 1333 /* stlexh */, ARM::t2STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 8827 { 1333 /* stlexh */, ARM::STLEXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease|Feature_HasV7Clrex, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 8828 { 1340 /* stlh */, ARM::t2STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsThumb|Feature_HasAcquireRelease, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset }, }, 8829 { 1340 /* stlh */, ARM::STLH, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM|Feature_HasAcquireRelease, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8830 { 1345 /* stm */, ARM::STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8831 { 1345 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8832 { 1345 /* stm */, ARM::t2STMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8833 { 1345 /* stm */, ARM::t2STMIA, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 8834 { 1345 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, }, 8835 { 1345 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8836 { 1345 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8837 { 1345 /* stm */, ARM::sysSTMIA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 8838 { 1345 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8839 { 1345 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 8840 { 1349 /* stmda */, ARM::STMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8841 { 1349 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8842 { 1349 /* stmda */, ARM::sysSTMDA, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 8843 { 1349 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 8844 { 1355 /* stmdb */, ARM::STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8845 { 1355 /* stmdb */, ARM::t2STMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8846 { 1355 /* stmdb */, ARM::t2STMDB, Convert__Reg1_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_RegList }, }, 8847 { 1355 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8848 { 1355 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8849 { 1355 /* stmdb */, ARM::sysSTMDB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 8850 { 1355 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8851 { 1355 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 8852 { 1361 /* stmib */, ARM::STMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList }, }, 8853 { 1361 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, }, 8854 { 1361 /* stmib */, ARM::sysSTMIB, Convert__Reg1_1__CondCode2_0__RegList1_2, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegList, MCK__94_ }, }, 8855 { 1361 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, }, 8856 { 1367 /* str */, ARM::tSTRi, Convert__Reg1_1__MemThumbRIs42_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs4 }, }, 8857 { 1367 /* str */, ARM::tSTRr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 8858 { 1367 /* str */, ARM::tSTRspi, Convert__Reg1_1__MemThumbSPI2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbSPI }, }, 8859 { 1367 /* str */, ARM::STRi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset }, }, 8860 { 1367 /* str */, ARM::t2STRi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemNegImm8Offset }, }, 8861 { 1367 /* str */, ARM::STRrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset }, }, 8862 { 1367 /* str */, ARM::t2STRi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemUImm12Offset }, }, 8863 { 1367 /* str */, ARM::t2STRs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_T2MemRegOffset }, }, 8864 { 1367 /* str */, ARM::t2STRi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_MemUImm12Offset }, }, 8865 { 1367 /* str */, ARM::t2STRs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK_T2MemRegOffset }, }, 8866 { 1367 /* str */, ARM::t2STR_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 8867 { 1367 /* str */, ARM::t2STR_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemNoOffset, MCK_Imm }, }, 8868 { 1367 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 8869 { 1367 /* str */, ARM::STR_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 8870 { 1367 /* str */, ARM::STR_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 8871 { 1367 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 8872 { 1371 /* strb */, ARM::tSTRBi, Convert__Reg1_1__MemThumbRIs12_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs1 }, }, 8873 { 1371 /* strb */, ARM::tSTRBr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 8874 { 1371 /* strb */, ARM::t2STRBi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, }, 8875 { 1371 /* strb */, ARM::t2STRBi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 8876 { 1371 /* strb */, ARM::t2STRBs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 8877 { 1371 /* strb */, ARM::STRBi12, Convert__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm12Offset }, }, 8878 { 1371 /* strb */, ARM::STRBrs, Convert__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_MemRegOffset }, }, 8879 { 1371 /* strb */, ARM::t2STRBi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, }, 8880 { 1371 /* strb */, ARM::t2STRBs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, }, 8881 { 1371 /* strb */, ARM::t2STRB_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 8882 { 1371 /* strb */, ARM::t2STRB_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 8883 { 1371 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, }, 8884 { 1371 /* strb */, ARM::STRB_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 8885 { 1371 /* strb */, ARM::STRB_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 8886 { 1371 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, }, 8887 { 1376 /* strbt */, ARM::t2STRBT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, }, 8888 { 1376 /* strbt */, ARM::STRBT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8889 { 1376 /* strbt */, ARM::STRBT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 8890 { 1376 /* strbt */, ARM::STRBT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 8891 { 1382 /* strd */, ARM::t2STRDi8, Convert__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset }, }, 8892 { 1382 /* strd */, ARM::STRD, Convert__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, Feature_IsARM|Feature_HasV5TE, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3 }, }, 8893 { 1382 /* strd */, ARM::t2STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, }, 8894 { 1382 /* strd */, ARM::t2STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__Imm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 8895 { 1382 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 8896 { 1382 /* strd */, ARM::STRD_POST, Convert__MemNoOffset1_3__Reg1_1__Reg1_2__Tie0_4_4__AM3Offset2_4__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 8897 { 1387 /* strex */, ARM::t2STREX, Convert__Reg1_1__Reg1_2__MemImm0_1020s4Offset2_3__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm0_1020s4Offset }, }, 8898 { 1387 /* strex */, ARM::STREX, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 8899 { 1393 /* strexb */, ARM::t2STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 8900 { 1393 /* strexb */, ARM::STREXB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 8901 { 1400 /* strexd */, ARM::STREXD, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPRPair, MCK_MemNoOffset }, }, 8902 { 1400 /* strexd */, ARM::t2STREXD, Convert__Reg1_1__Reg1_2__Reg1_3__MemNoOffset1_4__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 8903 { 1407 /* strexh */, ARM::t2STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemNoOffset }, }, 8904 { 1407 /* strexh */, ARM::STREXH, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_MemNoOffset }, }, 8905 { 1414 /* strh */, ARM::tSTRHi, Convert__Reg1_1__MemThumbRIs22_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRIs2 }, }, 8906 { 1414 /* strh */, ARM::tSTRHr, Convert__Reg1_1__MemThumbRR2_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_MemThumbRR }, }, 8907 { 1414 /* strh */, ARM::t2STRHi8, Convert__Reg1_1__MemNegImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNegImm8Offset }, }, 8908 { 1414 /* strh */, ARM::t2STRHi12, Convert__Reg1_1__MemUImm12Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemUImm12Offset }, }, 8909 { 1414 /* strh */, ARM::t2STRHs, Convert__Reg1_1__T2MemRegOffset3_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_T2MemRegOffset }, }, 8910 { 1414 /* strh */, ARM::STRH, Convert__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3 }, }, 8911 { 1414 /* strh */, ARM::t2STRHi12, Convert__Reg1_2__MemUImm12Offset2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_MemUImm12Offset }, }, 8912 { 1414 /* strh */, ARM::t2STRHs, Convert__Reg1_2__T2MemRegOffset3_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_T2MemRegOffset }, }, 8913 { 1414 /* strh */, ARM::t2STRH_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, }, 8914 { 1414 /* strh */, ARM::t2STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__Imm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemNoOffset, MCK_Imm }, }, 8915 { 1414 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, }, 8916 { 1414 /* strh */, ARM::STRH_POST, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM3Offset2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM3Offset }, }, 8917 { 1419 /* strht */, ARM::t2STRHT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, }, 8918 { 1419 /* strht */, ARM::STRHTi, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxImm81_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxImm8 }, }, 8919 { 1419 /* strht */, ARM::STRHTr, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxReg2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxReg }, }, 8920 { 1425 /* strt */, ARM::t2STRT, Convert__Reg1_1__MemImm8Offset2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset }, }, 8921 { 1425 /* strt */, ARM::STRT_POST, Convert__Reg1_1__MemNoOffset1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset }, }, 8922 { 1425 /* strt */, ARM::STRT_POST_IMM, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__AM2OffsetImm2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_AM2OffsetImm }, }, 8923 { 1425 /* strt */, ARM::STRT_POST_REG, Convert__MemNoOffset1_2__Reg1_1__Tie0_3_3__PostIdxRegShifted2_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemNoOffset, MCK_PostIdxRegShifted }, }, 8924 { 1430 /* sub */, ARM::tSUBspi, Convert__Reg1_1__Tie0_1_1__Imm0_508s41_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_Imm0_508s4 }, }, 8925 { 1430 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095 }, }, 8926 { 1430 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_2__Reg1_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8927 { 1430 /* sub */, ARM::tSUBi8, Convert__Reg1_2__CCOut1_0__Tie0_1_1__Imm0_2551_3__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_Imm0_255 }, }, 8928 { 1430 /* sub */, ARM::tADDi8, Convert__Reg1_2__CCOut1_0__Tie0_3_3__ThumbModImmNeg8_2551_3__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_ThumbModImmNeg8_255 }, }, 8929 { 1430 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 8930 { 1430 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 8931 { 1430 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_2__T2SOImm1_3__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 8932 { 1430 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR }, }, 8933 { 1430 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 8934 { 1430 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_2__ModImmNeg1_3__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNeg }, }, 8935 { 1430 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_2__RegShiftedImm2_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 8936 { 1430 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_2__RegShiftedReg3_3__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_RegShiftedReg }, }, 8937 { 1430 /* sub */, ARM::tSUBspi, Convert__regSP__Tie0_1_1__Imm0_508s41_3__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_GPRsp, MCK_GPRsp, MCK_Imm0_508s4 }, }, 8938 { 1430 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, }, 8939 { 1430 /* sub */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_T2SOImmNeg }, }, 8940 { 1430 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 8941 { 1430 /* sub */, ARM::tSUBrr, Convert__Reg1_2__CCOut1_0__Reg1_3__Reg1_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_tGPR }, }, 8942 { 1430 /* sub */, ARM::tSUBi3, Convert__Reg1_2__CCOut1_0__Reg1_3__Imm0_71_4__CondCode2_1, Feature_IsThumb, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_Imm0_7 }, }, 8943 { 1430 /* sub */, ARM::tADDi3, Convert__Reg1_2__CCOut1_0__Reg1_3__ThumbModImmNeg1_71_4__CondCode2_1, Feature_IsThumb|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_tGPR, MCK_tGPR, MCK_ThumbModImmNeg1_7 }, }, 8944 { 1430 /* sub */, ARM::t2SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 8945 { 1430 /* sub */, ARM::t2SUBrs, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 8946 { 1430 /* sub */, ARM::t2SUBri, Convert__Reg1_2__Reg1_3__T2SOImm1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, }, 8947 { 1430 /* sub */, ARM::t2ADDri, Convert__Reg1_2__Reg1_3__T2SOImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 8948 { 1430 /* sub */, ARM::SUBrr, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 8949 { 1430 /* sub */, ARM::SUBri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, }, 8950 { 1430 /* sub */, ARM::ADDri, Convert__Reg1_2__Reg1_3__ModImmNeg1_4__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNeg }, }, 8951 { 1430 /* sub */, ARM::SUBrsi, Convert__Reg1_2__Reg1_3__RegShiftedImm2_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedImm }, }, 8952 { 1430 /* sub */, ARM::SUBrsr, Convert__Reg1_2__Reg1_3__RegShiftedReg3_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_RegShiftedReg }, }, 8953 { 1430 /* sub */, ARM::t2SUBrr, Convert__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_rGPR }, }, 8954 { 1430 /* sub */, ARM::t2SUBrs, Convert__Reg1_3__Reg1_4__RegShiftedImm2_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_RegShiftedImm }, }, 8955 { 1430 /* sub */, ARM::t2SUBri, Convert__Reg1_3__Reg1_4__T2SOImm1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImm }, }, 8956 { 1430 /* sub */, ARM::t2ADDri, Convert__Reg1_3__Reg1_4__T2SOImmNeg1_5__CondCode2_1__CCOut1_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_GPRnopc, MCK_T2SOImmNeg }, }, 8957 { 1434 /* subs */, ARM::t2SUBS_PC_LR, Convert__Imm0_2551_3__CondCode2_0, Feature_IsThumb2|Feature_IsNotMClass, { MCK_CondCode, MCK_PC, MCK_LR, MCK_Imm0_255 }, }, 8958 { 1439 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, }, 8959 { 1439 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, }, 8960 { 1439 /* subw */, ARM::t2ADDri12, Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, Feature_IsThumb2|Feature_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_T2SOImmNeg }, }, 8961 { 1444 /* svc */, ARM::tSVC, Convert__Imm0_2551_1__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_Imm0_255 }, }, 8962 { 1444 /* svc */, ARM::SVC, Convert__Imm24bit1_1__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_Imm24bit }, }, 8963 { 1448 /* swp */, ARM::SWP, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, }, 8964 { 1452 /* swpb */, ARM::SWPB, Convert__Reg1_1__Reg1_2__MemNoOffset1_3__CondCode2_0, Feature_IsARM|Feature_PreV8, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_MemNoOffset }, }, 8965 { 1457 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8966 { 1457 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 8967 { 1457 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 8968 { 1457 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 8969 { 1463 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8970 { 1463 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 8971 { 1463 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 8972 { 1463 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 8973 { 1471 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 8974 { 1471 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 8975 { 1471 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 8976 { 1471 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 8977 { 1477 /* sxtb */, ARM::tSXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8978 { 1477 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8979 { 1477 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 8980 { 1477 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8981 { 1477 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 8982 { 1477 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 8983 { 1477 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 8984 { 1482 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8985 { 1482 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 8986 { 1482 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 8987 { 1482 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 8988 { 1482 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 8989 { 1489 /* sxth */, ARM::tSXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 8990 { 1489 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 8991 { 1489 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 8992 { 1489 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 8993 { 1489 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 8994 { 1489 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 8995 { 1489 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 8996 { 1494 /* tbb */, ARM::t2TBB, Convert__MemTBB2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemTBB }, }, 8997 { 1498 /* tbh */, ARM::t2TBH, Convert__MemTBH2_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_MemTBH }, }, 8998 { 1502 /* teq */, ARM::t2TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 8999 { 1502 /* teq */, ARM::t2TEQrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 9000 { 1502 /* teq */, ARM::TEQrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 9001 { 1502 /* teq */, ARM::t2TEQri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 9002 { 1502 /* teq */, ARM::TEQrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 9003 { 1502 /* teq */, ARM::TEQri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 9004 { 1502 /* teq */, ARM::TEQrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 9005 { 1502 /* teq */, ARM::t2TEQrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 9006 { 1502 /* teq */, ARM::t2TEQrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, }, 9007 { 1502 /* teq */, ARM::t2TEQri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, }, 9008 { 1506 /* trap */, ARM::TRAPNaCl, Convert_NoOperands, Feature_IsARM|Feature_UseNaClTrap, { }, }, 9009 { 1506 /* trap */, ARM::TRAP, Convert_NoOperands, Feature_IsARM, { }, }, 9010 { 1506 /* trap */, ARM::tTRAP, Convert_NoOperands, Feature_IsThumb, { }, }, 9011 { 1511 /* tsb */, ARM::TSB, Convert__TraceSyncBarrierOpt1_0, Feature_IsARM|Feature_HasV8_4a, { MCK_TraceSyncBarrierOpt }, }, 9012 { 1511 /* tsb */, ARM::t2TSB, Convert__TraceSyncBarrierOpt1_1__CondCode2_0, Feature_IsThumb|Feature_HasV8_4a, { MCK_CondCode, MCK_TraceSyncBarrierOpt }, }, 9013 { 1515 /* tst */, ARM::tTST, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 9014 { 1515 /* tst */, ARM::t2TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_rGPR }, }, 9015 { 1515 /* tst */, ARM::t2TSTrs, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedImm }, }, 9016 { 1515 /* tst */, ARM::TSTrsr, Convert__Reg1_1__RegShiftedReg3_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_RegShiftedReg }, }, 9017 { 1515 /* tst */, ARM::t2TSTri, Convert__Reg1_1__T2SOImm1_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_T2SOImm }, }, 9018 { 1515 /* tst */, ARM::TSTrr, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR }, }, 9019 { 1515 /* tst */, ARM::TSTri, Convert__Reg1_1__ModImm1_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_ModImm }, }, 9020 { 1515 /* tst */, ARM::TSTrsi, Convert__Reg1_1__RegShiftedImm2_2__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPR, MCK_RegShiftedImm }, }, 9021 { 1515 /* tst */, ARM::t2TSTrr, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_rGPR }, }, 9022 { 1515 /* tst */, ARM::t2TSTrs, Convert__Reg1_2__RegShiftedImm2_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_RegShiftedImm }, }, 9023 { 1515 /* tst */, ARM::t2TSTri, Convert__Reg1_2__T2SOImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPRnopc, MCK_T2SOImm }, }, 9024 { 1519 /* tt */, ARM::t2TT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 9025 { 1522 /* tta */, ARM::t2TTA, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 9026 { 1526 /* ttat */, ARM::t2TTAT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 9027 { 1531 /* ttt */, ARM::t2TTT, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_Has8MSecExt, { MCK_CondCode, MCK_rGPR, MCK_GPRnopc }, }, 9028 { 1535 /* uadd16 */, ARM::t2UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9029 { 1535 /* uadd16 */, ARM::UADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9030 { 1542 /* uadd8 */, ARM::t2UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9031 { 1542 /* uadd8 */, ARM::UADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9032 { 1548 /* uasx */, ARM::t2UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9033 { 1548 /* uasx */, ARM::UASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9034 { 1553 /* ubfx */, ARM::t2UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_Imm0_31, MCK_Imm1_32 }, }, 9035 { 1553 /* ubfx */, ARM::UBFX, Convert__Reg1_1__Reg1_2__Imm0_311_3__Imm1_321_4__CondCode2_0, Feature_IsARM|Feature_HasV6T2, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_Imm0_31, MCK_Imm1_32 }, }, 9036 { 1558 /* udf */, ARM::tUDF, Convert__Imm0_2551_0, Feature_IsThumb, { MCK_Imm0_255 }, }, 9037 { 1558 /* udf */, ARM::UDF, Convert__Imm0_655351_0, Feature_IsARM, { MCK_Imm0_65535 }, }, 9038 { 1558 /* udf */, ARM::t2UDF, Convert__Imm0_655351_1, Feature_IsThumb2, { MCK__DOT_w, MCK_Imm0_65535 }, }, 9039 { 1562 /* udiv */, ARM::t2UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasDivideInThumb|Feature_IsThumb|Feature_HasV8MBaseline, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9040 { 1562 /* udiv */, ARM::UDIV, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasDivideInARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 9041 { 1567 /* uhadd16 */, ARM::t2UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9042 { 1567 /* uhadd16 */, ARM::UHADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9043 { 1575 /* uhadd8 */, ARM::t2UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9044 { 1575 /* uhadd8 */, ARM::UHADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9045 { 1582 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9046 { 1582 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9047 { 1588 /* uhsax */, ARM::t2UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9048 { 1588 /* uhsax */, ARM::UHSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9049 { 1594 /* uhsub16 */, ARM::t2UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9050 { 1594 /* uhsub16 */, ARM::UHSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9051 { 1602 /* uhsub8 */, ARM::t2UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9052 { 1602 /* uhsub8 */, ARM::UHSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9053 { 1609 /* umaal */, ARM::t2UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9054 { 1609 /* umaal */, ARM::UMAAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 9055 { 1615 /* umlal */, ARM::t2UMLAL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9056 { 1615 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_1_1__Tie1_1_1__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 9057 { 1615 /* umlal */, ARM::UMLAL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__Tie0_3_3__Tie1_4_4__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 9058 { 1621 /* umull */, ARM::t2UMULL, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9059 { 1621 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM|Feature_HasV6, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 9060 { 1621 /* umull */, ARM::UMULL, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__CondCode2_1__CCOut1_0, Feature_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 9061 { 1627 /* uqadd16 */, ARM::t2UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9062 { 1627 /* uqadd16 */, ARM::UQADD16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9063 { 1635 /* uqadd8 */, ARM::t2UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9064 { 1635 /* uqadd8 */, ARM::UQADD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9065 { 1642 /* uqasx */, ARM::t2UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9066 { 1642 /* uqasx */, ARM::UQASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9067 { 1648 /* uqsax */, ARM::t2UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9068 { 1648 /* uqsax */, ARM::UQSAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9069 { 1654 /* uqsub16 */, ARM::t2UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9070 { 1654 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9071 { 1662 /* uqsub8 */, ARM::t2UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9072 { 1662 /* uqsub8 */, ARM::UQSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9073 { 1669 /* usad8 */, ARM::t2USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9074 { 1669 /* usad8 */, ARM::USAD8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, }, 9075 { 1675 /* usada8 */, ARM::t2USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9076 { 1675 /* usada8 */, ARM::USADA8, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR, MCK_GPR }, }, 9077 { 1682 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR }, }, 9078 { 1682 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc }, }, 9079 { 1682 /* usat */, ARM::t2USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_Imm0_31, MCK_rGPR, MCK_ShifterImm }, }, 9080 { 1682 /* usat */, ARM::USAT, Convert__Reg1_1__Imm0_311_2__Reg1_3__ShifterImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_31, MCK_GPRnopc, MCK_ShifterImm }, }, 9081 { 1687 /* usat16 */, ARM::t2USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_Imm0_15, MCK_rGPR }, }, 9082 { 1687 /* usat16 */, ARM::USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_15, MCK_GPRnopc }, }, 9083 { 1694 /* usax */, ARM::t2USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9084 { 1694 /* usax */, ARM::USAX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9085 { 1699 /* usub16 */, ARM::t2USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9086 { 1699 /* usub16 */, ARM::USUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9087 { 1706 /* usub8 */, ARM::t2USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|Feature_HasDSP, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9088 { 1706 /* usub8 */, ARM::USUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_GPRnopc }, }, 9089 { 1712 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9090 { 1712 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 9091 { 1712 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 9092 { 1712 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 9093 { 1718 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9094 { 1718 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 9095 { 1718 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 9096 { 1718 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 9097 { 1726 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR }, }, 9098 { 1726 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc }, }, 9099 { 1726 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 9100 { 1726 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, }, 9101 { 1732 /* uxtb */, ARM::tUXTB, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 9102 { 1732 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 9103 { 1732 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 9104 { 1732 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 9105 { 1732 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 9106 { 1732 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 9107 { 1732 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 9108 { 1737 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 9109 { 1737 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 9110 { 1737 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 9111 { 1737 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_HasDSP|Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 9112 { 1737 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 9113 { 1744 /* uxth */, ARM::tUXTH, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_IsThumb|Feature_HasV6, { MCK_CondCode, MCK_tGPR, MCK_tGPR }, }, 9114 { 1744 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR }, }, 9115 { 1744 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, Feature_IsARM, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc }, }, 9116 { 1744 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__imm_95_0__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR }, }, 9117 { 1744 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 9118 { 1744 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, Feature_IsARM|Feature_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, }, 9119 { 1744 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, }, 9120 { 1749 /* vaba */, ARM::VABAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9121 { 1749 /* vaba */, ARM::VABAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9122 { 1749 /* vaba */, ARM::VABAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9123 { 1749 /* vaba */, ARM::VABAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9124 { 1749 /* vaba */, ARM::VABAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9125 { 1749 /* vaba */, ARM::VABAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9126 { 1749 /* vaba */, ARM::VABAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9127 { 1749 /* vaba */, ARM::VABAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9128 { 1749 /* vaba */, ARM::VABAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9129 { 1749 /* vaba */, ARM::VABAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9130 { 1749 /* vaba */, ARM::VABAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9131 { 1749 /* vaba */, ARM::VABAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9132 { 1754 /* vabal */, ARM::VABALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9133 { 1754 /* vabal */, ARM::VABALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9134 { 1754 /* vabal */, ARM::VABALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9135 { 1754 /* vabal */, ARM::VABALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9136 { 1754 /* vabal */, ARM::VABALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9137 { 1754 /* vabal */, ARM::VABALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9138 { 1760 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 9139 { 1760 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 9140 { 1760 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 9141 { 1760 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 9142 { 1760 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 9143 { 1760 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 9144 { 1760 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 9145 { 1760 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 9146 { 1760 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 9147 { 1760 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 9148 { 1760 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 9149 { 1760 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 9150 { 1760 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9151 { 1760 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9152 { 1760 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9153 { 1760 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9154 { 1760 /* vabd */, ARM::VABDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9155 { 1760 /* vabd */, ARM::VABDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9156 { 1760 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9157 { 1760 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9158 { 1760 /* vabd */, ARM::VABDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9159 { 1760 /* vabd */, ARM::VABDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9160 { 1760 /* vabd */, ARM::VABDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9161 { 1760 /* vabd */, ARM::VABDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9162 { 1760 /* vabd */, ARM::VABDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9163 { 1760 /* vabd */, ARM::VABDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9164 { 1760 /* vabd */, ARM::VABDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9165 { 1760 /* vabd */, ARM::VABDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9166 { 1760 /* vabd */, ARM::VABDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9167 { 1760 /* vabd */, ARM::VABDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9168 { 1760 /* vabd */, ARM::VABDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9169 { 1760 /* vabd */, ARM::VABDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9170 { 1765 /* vabdl */, ARM::VABDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9171 { 1765 /* vabdl */, ARM::VABDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9172 { 1765 /* vabdl */, ARM::VABDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9173 { 1765 /* vabdl */, ARM::VABDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9174 { 1765 /* vabdl */, ARM::VABDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9175 { 1765 /* vabdl */, ARM::VABDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9176 { 1771 /* vabs */, ARM::VABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 9177 { 1771 /* vabs */, ARM::VABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 9178 { 1771 /* vabs */, ARM::VABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 9179 { 1771 /* vabs */, ARM::VABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 9180 { 1771 /* vabs */, ARM::VABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 9181 { 1771 /* vabs */, ARM::VABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 9182 { 1771 /* vabs */, ARM::VABSfq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9183 { 1771 /* vabs */, ARM::VABSfd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9184 { 1771 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9185 { 1771 /* vabs */, ARM::VABSD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 9186 { 1771 /* vabs */, ARM::VABShq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9187 { 1771 /* vabs */, ARM::VABShd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9188 { 1771 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9189 { 1776 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9190 { 1776 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9191 { 1776 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9192 { 1776 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9193 { 1776 /* vacge */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9194 { 1776 /* vacge */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9195 { 1776 /* vacge */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9196 { 1776 /* vacge */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9197 { 1782 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9198 { 1782 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9199 { 1782 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9200 { 1782 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9201 { 1782 /* vacgt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9202 { 1782 /* vacgt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9203 { 1782 /* vacgt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9204 { 1782 /* vacgt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9205 { 1788 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9206 { 1788 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9207 { 1788 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9208 { 1788 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9209 { 1788 /* vacle */, ARM::VACGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9210 { 1788 /* vacle */, ARM::VACGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9211 { 1788 /* vacle */, ARM::VACGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9212 { 1788 /* vacle */, ARM::VACGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9213 { 1794 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9214 { 1794 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9215 { 1794 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9216 { 1794 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_3__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9217 { 1794 /* vaclt */, ARM::VACGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9218 { 1794 /* vaclt */, ARM::VACGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9219 { 1794 /* vaclt */, ARM::VACGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9220 { 1794 /* vaclt */, ARM::VACGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9221 { 1800 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9222 { 1800 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9223 { 1800 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9224 { 1800 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 9225 { 1800 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 9226 { 1800 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 9227 { 1800 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 9228 { 1800 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 9229 { 1800 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, }, 9230 { 1800 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, }, 9231 { 1800 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 9232 { 1800 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 9233 { 1800 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9234 { 1800 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9235 { 1800 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9236 { 1800 /* vadd */, ARM::VADDfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9237 { 1800 /* vadd */, ARM::VADDfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9238 { 1800 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9239 { 1800 /* vadd */, ARM::VADDD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9240 { 1800 /* vadd */, ARM::VADDv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9241 { 1800 /* vadd */, ARM::VADDv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9242 { 1800 /* vadd */, ARM::VADDv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9243 { 1800 /* vadd */, ARM::VADDv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9244 { 1800 /* vadd */, ARM::VADDv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9245 { 1800 /* vadd */, ARM::VADDv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9246 { 1800 /* vadd */, ARM::VADDv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9247 { 1800 /* vadd */, ARM::VADDv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9248 { 1800 /* vadd */, ARM::VADDhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9249 { 1800 /* vadd */, ARM::VADDhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9250 { 1800 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9251 { 1805 /* vaddhn */, ARM::VADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 9252 { 1805 /* vaddhn */, ARM::VADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 9253 { 1805 /* vaddhn */, ARM::VADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 9254 { 1812 /* vaddl */, ARM::VADDLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9255 { 1812 /* vaddl */, ARM::VADDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9256 { 1812 /* vaddl */, ARM::VADDLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9257 { 1812 /* vaddl */, ARM::VADDLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9258 { 1812 /* vaddl */, ARM::VADDLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9259 { 1812 /* vaddl */, ARM::VADDLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 9260 { 1818 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, }, 9261 { 1818 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, }, 9262 { 1818 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, }, 9263 { 1818 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, }, 9264 { 1818 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, }, 9265 { 1818 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, }, 9266 { 1818 /* vaddw */, ARM::VADDWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 9267 { 1818 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 9268 { 1818 /* vaddw */, ARM::VADDWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 9269 { 1818 /* vaddw */, ARM::VADDWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 9270 { 1818 /* vaddw */, ARM::VADDWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 9271 { 1818 /* vaddw */, ARM::VADDWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 9272 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 9273 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 9274 { 1824 /* vand */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splatNot }, }, 9275 { 1824 /* vand */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splatNot1_3__Tie0_3_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splatNot }, }, 9276 { 1824 /* vand */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splatNot }, }, 9277 { 1824 /* vand */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splatNot1_3__Tie0_3_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splatNot }, }, 9278 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 9279 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 9280 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 9281 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 9282 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 9283 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 9284 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 9285 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 9286 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9287 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9288 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9289 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9290 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9291 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9292 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9293 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9294 { 1824 /* vand */, ARM::VANDq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9295 { 1824 /* vand */, ARM::VANDd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9296 { 1829 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 9297 { 1829 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 9298 { 1829 /* vbic */, ARM::VBICiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 9299 { 1829 /* vbic */, ARM::VBICiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 9300 { 1829 /* vbic */, ARM::VBICiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, }, 9301 { 1829 /* vbic */, ARM::VBICiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, }, 9302 { 1829 /* vbic */, ARM::VBICq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9303 { 1829 /* vbic */, ARM::VBICd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9304 { 1829 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9305 { 1829 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9306 { 1829 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9307 { 1829 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9308 { 1829 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9309 { 1829 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9310 { 1829 /* vbic */, ARM::VBICq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9311 { 1829 /* vbic */, ARM::VBICd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9312 { 1834 /* vbif */, ARM::VBIFq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9313 { 1834 /* vbif */, ARM::VBIFd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9314 { 1834 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9315 { 1834 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9316 { 1834 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9317 { 1834 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9318 { 1834 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9319 { 1834 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9320 { 1834 /* vbif */, ARM::VBIFq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9321 { 1834 /* vbif */, ARM::VBIFd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9322 { 1839 /* vbit */, ARM::VBITq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9323 { 1839 /* vbit */, ARM::VBITd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9324 { 1839 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9325 { 1839 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9326 { 1839 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9327 { 1839 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9328 { 1839 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9329 { 1839 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9330 { 1839 /* vbit */, ARM::VBITq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9331 { 1839 /* vbit */, ARM::VBITd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9332 { 1844 /* vbsl */, ARM::VBSLq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9333 { 1844 /* vbsl */, ARM::VBSLd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9334 { 1844 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9335 { 1844 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9336 { 1844 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9337 { 1844 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9338 { 1844 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9339 { 1844 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9340 { 1844 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9341 { 1844 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9342 { 1849 /* vcadd */, ARM::VCADDv4f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, }, 9343 { 1849 /* vcadd */, ARM::VCADDv2f32, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, }, 9344 { 1849 /* vcadd */, ARM::VCADDv8f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationOdd }, }, 9345 { 1849 /* vcadd */, ARM::VCADDv4f16, Convert__Reg1_1__Reg1_2__Reg1_3__ComplexRotationOdd1_4, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationOdd }, }, 9346 { 1855 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, }, 9347 { 1855 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9348 { 1855 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, }, 9349 { 1855 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9350 { 1855 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK__35_0 }, }, 9351 { 1855 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 9352 { 1855 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK__35_0 }, }, 9353 { 1855 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 9354 { 1855 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK__35_0 }, }, 9355 { 1855 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 9356 { 1855 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK__35_0 }, }, 9357 { 1855 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 9358 { 1855 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK__35_0 }, }, 9359 { 1855 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 9360 { 1855 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK__35_0 }, }, 9361 { 1855 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 9362 { 1855 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, }, 9363 { 1855 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9364 { 1855 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, }, 9365 { 1855 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9366 { 1855 /* vceq */, ARM::VCEQzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9367 { 1855 /* vceq */, ARM::VCEQfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9368 { 1855 /* vceq */, ARM::VCEQzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9369 { 1855 /* vceq */, ARM::VCEQfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9370 { 1855 /* vceq */, ARM::VCEQzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9371 { 1855 /* vceq */, ARM::VCEQv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9372 { 1855 /* vceq */, ARM::VCEQzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9373 { 1855 /* vceq */, ARM::VCEQv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9374 { 1855 /* vceq */, ARM::VCEQzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9375 { 1855 /* vceq */, ARM::VCEQv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9376 { 1855 /* vceq */, ARM::VCEQzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9377 { 1855 /* vceq */, ARM::VCEQv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9378 { 1855 /* vceq */, ARM::VCEQzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9379 { 1855 /* vceq */, ARM::VCEQv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9380 { 1855 /* vceq */, ARM::VCEQzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9381 { 1855 /* vceq */, ARM::VCEQv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9382 { 1855 /* vceq */, ARM::VCEQzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9383 { 1855 /* vceq */, ARM::VCEQhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9384 { 1855 /* vceq */, ARM::VCEQzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9385 { 1855 /* vceq */, ARM::VCEQhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9386 { 1860 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__35_0 }, }, 9387 { 1860 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 9388 { 1860 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__35_0 }, }, 9389 { 1860 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 9390 { 1860 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__35_0 }, }, 9391 { 1860 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 9392 { 1860 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__35_0 }, }, 9393 { 1860 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 9394 { 1860 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__35_0 }, }, 9395 { 1860 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 9396 { 1860 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__35_0 }, }, 9397 { 1860 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 9398 { 1860 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 9399 { 1860 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 9400 { 1860 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 9401 { 1860 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 9402 { 1860 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 9403 { 1860 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 9404 { 1860 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, }, 9405 { 1860 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9406 { 1860 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, }, 9407 { 1860 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9408 { 1860 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, }, 9409 { 1860 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9410 { 1860 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, }, 9411 { 1860 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9412 { 1860 /* vcge */, ARM::VCGEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9413 { 1860 /* vcge */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9414 { 1860 /* vcge */, ARM::VCGEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9415 { 1860 /* vcge */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9416 { 1860 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9417 { 1860 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9418 { 1860 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9419 { 1860 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9420 { 1860 /* vcge */, ARM::VCGEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9421 { 1860 /* vcge */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9422 { 1860 /* vcge */, ARM::VCGEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9423 { 1860 /* vcge */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9424 { 1860 /* vcge */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9425 { 1860 /* vcge */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9426 { 1860 /* vcge */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9427 { 1860 /* vcge */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9428 { 1860 /* vcge */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9429 { 1860 /* vcge */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9430 { 1860 /* vcge */, ARM::VCGEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9431 { 1860 /* vcge */, ARM::VCGEfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9432 { 1860 /* vcge */, ARM::VCGEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9433 { 1860 /* vcge */, ARM::VCGEfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9434 { 1860 /* vcge */, ARM::VCGEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9435 { 1860 /* vcge */, ARM::VCGEhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9436 { 1860 /* vcge */, ARM::VCGEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9437 { 1860 /* vcge */, ARM::VCGEhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9438 { 1865 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__35_0 }, }, 9439 { 1865 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 9440 { 1865 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__35_0 }, }, 9441 { 1865 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 9442 { 1865 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__35_0 }, }, 9443 { 1865 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 9444 { 1865 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__35_0 }, }, 9445 { 1865 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 9446 { 1865 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__35_0 }, }, 9447 { 1865 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 9448 { 1865 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__35_0 }, }, 9449 { 1865 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 9450 { 1865 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 9451 { 1865 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 9452 { 1865 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 9453 { 1865 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 9454 { 1865 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 9455 { 1865 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 9456 { 1865 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, }, 9457 { 1865 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9458 { 1865 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, }, 9459 { 1865 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9460 { 1865 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, }, 9461 { 1865 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9462 { 1865 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, }, 9463 { 1865 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9464 { 1865 /* vcgt */, ARM::VCGTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9465 { 1865 /* vcgt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9466 { 1865 /* vcgt */, ARM::VCGTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9467 { 1865 /* vcgt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9468 { 1865 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9469 { 1865 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9470 { 1865 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9471 { 1865 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9472 { 1865 /* vcgt */, ARM::VCGTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9473 { 1865 /* vcgt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9474 { 1865 /* vcgt */, ARM::VCGTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9475 { 1865 /* vcgt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9476 { 1865 /* vcgt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9477 { 1865 /* vcgt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9478 { 1865 /* vcgt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9479 { 1865 /* vcgt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9480 { 1865 /* vcgt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9481 { 1865 /* vcgt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9482 { 1865 /* vcgt */, ARM::VCGTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9483 { 1865 /* vcgt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9484 { 1865 /* vcgt */, ARM::VCGTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9485 { 1865 /* vcgt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9486 { 1865 /* vcgt */, ARM::VCGTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9487 { 1865 /* vcgt */, ARM::VCGThq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9488 { 1865 /* vcgt */, ARM::VCGTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9489 { 1865 /* vcgt */, ARM::VCGThd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9490 { 1870 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__35_0 }, }, 9491 { 1870 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__35_0 }, }, 9492 { 1870 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__35_0 }, }, 9493 { 1870 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__35_0 }, }, 9494 { 1870 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__35_0 }, }, 9495 { 1870 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__35_0 }, }, 9496 { 1870 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, }, 9497 { 1870 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, }, 9498 { 1870 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, }, 9499 { 1870 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, }, 9500 { 1870 /* vcle */, ARM::VCLEzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9501 { 1870 /* vcle */, ARM::VCGEsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9502 { 1870 /* vcle */, ARM::VCLEzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9503 { 1870 /* vcle */, ARM::VCGEsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9504 { 1870 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9505 { 1870 /* vcle */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9506 { 1870 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9507 { 1870 /* vcle */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9508 { 1870 /* vcle */, ARM::VCLEzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9509 { 1870 /* vcle */, ARM::VCGEsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9510 { 1870 /* vcle */, ARM::VCLEzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9511 { 1870 /* vcle */, ARM::VCGEsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9512 { 1870 /* vcle */, ARM::VCGEuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9513 { 1870 /* vcle */, ARM::VCGEuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9514 { 1870 /* vcle */, ARM::VCGEuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9515 { 1870 /* vcle */, ARM::VCGEuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9516 { 1870 /* vcle */, ARM::VCGEuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9517 { 1870 /* vcle */, ARM::VCGEuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9518 { 1870 /* vcle */, ARM::VCLEzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9519 { 1870 /* vcle */, ARM::VCGEfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9520 { 1870 /* vcle */, ARM::VCLEzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9521 { 1870 /* vcle */, ARM::VCGEfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9522 { 1870 /* vcle */, ARM::VCLEzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9523 { 1870 /* vcle */, ARM::VCGEhq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9524 { 1870 /* vcle */, ARM::VCLEzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9525 { 1870 /* vcle */, ARM::VCGEhd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9526 { 1875 /* vcls */, ARM::VCLSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 9527 { 1875 /* vcls */, ARM::VCLSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 9528 { 1875 /* vcls */, ARM::VCLSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 9529 { 1875 /* vcls */, ARM::VCLSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 9530 { 1875 /* vcls */, ARM::VCLSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 9531 { 1875 /* vcls */, ARM::VCLSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 9532 { 1880 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK__35_0 }, }, 9533 { 1880 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK__35_0 }, }, 9534 { 1880 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__35_0 }, }, 9535 { 1880 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__35_0 }, }, 9536 { 1880 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK__35_0 }, }, 9537 { 1880 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK__35_0 }, }, 9538 { 1880 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK__35_0 }, }, 9539 { 1880 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK__35_0 }, }, 9540 { 1880 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK__35_0 }, }, 9541 { 1880 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK__35_0 }, }, 9542 { 1880 /* vclt */, ARM::VCLTzv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9543 { 1880 /* vclt */, ARM::VCGTsv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9544 { 1880 /* vclt */, ARM::VCLTzv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9545 { 1880 /* vclt */, ARM::VCGTsv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9546 { 1880 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9547 { 1880 /* vclt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9548 { 1880 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9549 { 1880 /* vclt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9550 { 1880 /* vclt */, ARM::VCLTzv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9551 { 1880 /* vclt */, ARM::VCGTsv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9552 { 1880 /* vclt */, ARM::VCLTzv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9553 { 1880 /* vclt */, ARM::VCGTsv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9554 { 1880 /* vclt */, ARM::VCGTuv8i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9555 { 1880 /* vclt */, ARM::VCGTuv4i16, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9556 { 1880 /* vclt */, ARM::VCGTuv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9557 { 1880 /* vclt */, ARM::VCGTuv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9558 { 1880 /* vclt */, ARM::VCGTuv16i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9559 { 1880 /* vclt */, ARM::VCGTuv8i8, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9560 { 1880 /* vclt */, ARM::VCLTzv4f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9561 { 1880 /* vclt */, ARM::VCGTfq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9562 { 1880 /* vclt */, ARM::VCLTzv2f32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9563 { 1880 /* vclt */, ARM::VCGTfd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9564 { 1880 /* vclt */, ARM::VCLTzv8f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9565 { 1880 /* vclt */, ARM::VCGThq, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9566 { 1880 /* vclt */, ARM::VCLTzv4f16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9567 { 1880 /* vclt */, ARM::VCGThd, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9568 { 1885 /* vclz */, ARM::VCLZv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 9569 { 1885 /* vclz */, ARM::VCLZv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 9570 { 1885 /* vclz */, ARM::VCLZv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 9571 { 1885 /* vclz */, ARM::VCLZv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 9572 { 1885 /* vclz */, ARM::VCLZv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 9573 { 1885 /* vclz */, ARM::VCLZv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 9574 { 1890 /* vcmla */, ARM::VCMLAv4f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, }, 9575 { 1890 /* vcmla */, ARM::VCMLAv2f32, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, }, 9576 { 1890 /* vcmla */, ARM::VCMLAv8f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_ComplexRotationEven }, }, 9577 { 1890 /* vcmla */, ARM::VCMLAv4f16, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__ComplexRotationEven1_4, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_ComplexRotationEven }, }, 9578 { 1890 /* vcmla */, ARM::VCMLAv4f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, }, 9579 { 1890 /* vcmla */, ARM::VCMLAv2f32_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex641_4__ComplexRotationEven1_5, Feature_HasNEON|Feature_HasV8_3a, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_VectorIndex64, MCK_ComplexRotationEven }, }, 9580 { 1890 /* vcmla */, ARM::VCMLAv8f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, }, 9581 { 1890 /* vcmla */, ARM::VCMLAv4f16_indexed, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__VectorIndex321_4__ComplexRotationEven1_5, Feature_HasNEON|Feature_HasV8_3a|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32, MCK_ComplexRotationEven }, }, 9582 { 1896 /* vcmp */, ARM::VCMPZS, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__35_0 }, }, 9583 { 1896 /* vcmp */, ARM::VCMPS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9584 { 1896 /* vcmp */, ARM::VCMPZD, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__35_0 }, }, 9585 { 1896 /* vcmp */, ARM::VCMPD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 9586 { 1896 /* vcmp */, ARM::VCMPZH, Convert__Reg1_2__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__35_0 }, }, 9587 { 1896 /* vcmp */, ARM::VCMPH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9588 { 1901 /* vcmpe */, ARM::VCMPEZS, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__35_0 }, }, 9589 { 1901 /* vcmpe */, ARM::VCMPES, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9590 { 1901 /* vcmpe */, ARM::VCMPEZD, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK__35_0 }, }, 9591 { 1901 /* vcmpe */, ARM::VCMPED, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 9592 { 1901 /* vcmpe */, ARM::VCMPEZH, Convert__Reg1_2__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__35_0 }, }, 9593 { 1901 /* vcmpe */, ARM::VCMPEH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9594 { 1907 /* vcnt */, ARM::VCNTq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 9595 { 1907 /* vcnt */, ARM::VCNTd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 9596 { 1912 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9597 { 1912 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9598 { 1912 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9599 { 1912 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9600 { 1912 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9601 { 1912 /* vcvt */, ARM::VTOSIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9602 { 1912 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9603 { 1912 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9604 { 1912 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9605 { 1912 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9606 { 1912 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9607 { 1912 /* vcvt */, ARM::VTOUIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9608 { 1912 /* vcvt */, ARM::VTOUIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9609 { 1912 /* vcvt */, ARM::VTOUIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9610 { 1912 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 9611 { 1912 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 9612 { 1912 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, }, 9613 { 1912 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 9614 { 1912 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 9615 { 1912 /* vcvt */, ARM::VUITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR }, }, 9616 { 1912 /* vcvt */, ARM::VCVTSD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9617 { 1912 /* vcvt */, ARM::VCVTh2f, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_QPR, MCK_DPR }, }, 9618 { 1912 /* vcvt */, ARM::VSITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_HPR }, }, 9619 { 1912 /* vcvt */, ARM::VUITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_HPR }, }, 9620 { 1912 /* vcvt */, ARM::VCVTDS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f32, MCK_DPR, MCK_HPR }, }, 9621 { 1912 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 9622 { 1912 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 9623 { 1912 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, }, 9624 { 1912 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 9625 { 1912 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 9626 { 1912 /* vcvt */, ARM::VUITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR }, }, 9627 { 1912 /* vcvt */, ARM::VCVTf2h, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_DPR, MCK_QPR }, }, 9628 { 1912 /* vcvt */, ARM::VTOSHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 9629 { 1912 /* vcvt */, ARM::VTOSHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 9630 { 1912 /* vcvt */, ARM::VCVTh2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9631 { 1912 /* vcvt */, ARM::VCVTh2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 9632 { 1912 /* vcvt */, ARM::VCVTh2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9633 { 1912 /* vcvt */, ARM::VCVTh2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 9634 { 1912 /* vcvt */, ARM::VTOSHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 9635 { 1912 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9636 { 1912 /* vcvt */, ARM::VCVTf2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 9637 { 1912 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9638 { 1912 /* vcvt */, ARM::VCVTf2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 9639 { 1912 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 9640 { 1912 /* vcvt */, ARM::VTOSLD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 9641 { 1912 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 9642 { 1912 /* vcvt */, ARM::VTOUHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 9643 { 1912 /* vcvt */, ARM::VTOUHD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 9644 { 1912 /* vcvt */, ARM::VCVTh2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9645 { 1912 /* vcvt */, ARM::VCVTh2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 9646 { 1912 /* vcvt */, ARM::VCVTh2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9647 { 1912 /* vcvt */, ARM::VCVTh2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 9648 { 1912 /* vcvt */, ARM::VTOUHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 9649 { 1912 /* vcvt */, ARM::VCVTf2uq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9650 { 1912 /* vcvt */, ARM::VCVTf2xuq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 9651 { 1912 /* vcvt */, ARM::VCVTf2ud, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9652 { 1912 /* vcvt */, ARM::VCVTf2xud, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 9653 { 1912 /* vcvt */, ARM::VTOULS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 9654 { 1912 /* vcvt */, ARM::VTOULD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 9655 { 1912 /* vcvt */, ARM::VTOULH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 9656 { 1912 /* vcvt */, ARM::VSHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 9657 { 1912 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9658 { 1912 /* vcvt */, ARM::VCVTxs2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 9659 { 1912 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9660 { 1912 /* vcvt */, ARM::VCVTxs2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 9661 { 1912 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 9662 { 1912 /* vcvt */, ARM::VUHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 9663 { 1912 /* vcvt */, ARM::VCVTu2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9664 { 1912 /* vcvt */, ARM::VCVTxu2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 9665 { 1912 /* vcvt */, ARM::VCVTu2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9666 { 1912 /* vcvt */, ARM::VCVTxu2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 9667 { 1912 /* vcvt */, ARM::VULTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 9668 { 1912 /* vcvt */, ARM::VSHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 9669 { 1912 /* vcvt */, ARM::VSLTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 9670 { 1912 /* vcvt */, ARM::VUHTOD, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_FBits16 }, }, 9671 { 1912 /* vcvt */, ARM::VULTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_FBits32 }, }, 9672 { 1912 /* vcvt */, ARM::VCVTs2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9673 { 1912 /* vcvt */, ARM::VCVTxs2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 9674 { 1912 /* vcvt */, ARM::VCVTs2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9675 { 1912 /* vcvt */, ARM::VCVTxs2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 9676 { 1912 /* vcvt */, ARM::VSHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 9677 { 1912 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 9678 { 1912 /* vcvt */, ARM::VCVTu2hq, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK__35_0 }, }, 9679 { 1912 /* vcvt */, ARM::VCVTxu2hq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 9680 { 1912 /* vcvt */, ARM::VCVTu2hd, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK__35_0 }, }, 9681 { 1912 /* vcvt */, ARM::VCVTxu2hd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 9682 { 1912 /* vcvt */, ARM::VUHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, }, 9683 { 1912 /* vcvt */, ARM::VULTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, }, 9684 { 1917 /* vcvta */, ARM::VCVTANSQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9685 { 1917 /* vcvta */, ARM::VCVTANSDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9686 { 1917 /* vcvta */, ARM::VCVTANSQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9687 { 1917 /* vcvta */, ARM::VCVTANSDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9688 { 1917 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9689 { 1917 /* vcvta */, ARM::VCVTASD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9690 { 1917 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9691 { 1917 /* vcvta */, ARM::VCVTANUQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9692 { 1917 /* vcvta */, ARM::VCVTANUDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9693 { 1917 /* vcvta */, ARM::VCVTANUQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9694 { 1917 /* vcvta */, ARM::VCVTANUDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9695 { 1917 /* vcvta */, ARM::VCVTAUS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9696 { 1917 /* vcvta */, ARM::VCVTAUD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9697 { 1917 /* vcvta */, ARM::VCVTAUH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9698 { 1923 /* vcvtb */, ARM::VCVTBHS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9699 { 1923 /* vcvtb */, ARM::VCVTBHD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, }, 9700 { 1923 /* vcvtb */, ARM::VCVTBSH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9701 { 1923 /* vcvtb */, ARM::VCVTBDH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9702 { 1929 /* vcvtm */, ARM::VCVTMNSQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9703 { 1929 /* vcvtm */, ARM::VCVTMNSDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9704 { 1929 /* vcvtm */, ARM::VCVTMNSQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9705 { 1929 /* vcvtm */, ARM::VCVTMNSDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9706 { 1929 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9707 { 1929 /* vcvtm */, ARM::VCVTMSD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9708 { 1929 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9709 { 1929 /* vcvtm */, ARM::VCVTMNUQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9710 { 1929 /* vcvtm */, ARM::VCVTMNUDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9711 { 1929 /* vcvtm */, ARM::VCVTMNUQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9712 { 1929 /* vcvtm */, ARM::VCVTMNUDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9713 { 1929 /* vcvtm */, ARM::VCVTMUS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9714 { 1929 /* vcvtm */, ARM::VCVTMUD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9715 { 1929 /* vcvtm */, ARM::VCVTMUH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9716 { 1935 /* vcvtn */, ARM::VCVTNNSQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9717 { 1935 /* vcvtn */, ARM::VCVTNNSDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9718 { 1935 /* vcvtn */, ARM::VCVTNNSQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9719 { 1935 /* vcvtn */, ARM::VCVTNNSDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9720 { 1935 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9721 { 1935 /* vcvtn */, ARM::VCVTNSD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9722 { 1935 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9723 { 1935 /* vcvtn */, ARM::VCVTNNUQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9724 { 1935 /* vcvtn */, ARM::VCVTNNUDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9725 { 1935 /* vcvtn */, ARM::VCVTNNUQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9726 { 1935 /* vcvtn */, ARM::VCVTNNUDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9727 { 1935 /* vcvtn */, ARM::VCVTNUS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9728 { 1935 /* vcvtn */, ARM::VCVTNUD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9729 { 1935 /* vcvtn */, ARM::VCVTNUH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9730 { 1941 /* vcvtp */, ARM::VCVTPNSQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9731 { 1941 /* vcvtp */, ARM::VCVTPNSDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_s16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9732 { 1941 /* vcvtp */, ARM::VCVTPNSQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9733 { 1941 /* vcvtp */, ARM::VCVTPNSDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9734 { 1941 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9735 { 1941 /* vcvtp */, ARM::VCVTPSD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9736 { 1941 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9737 { 1941 /* vcvtp */, ARM::VCVTPNUQh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 9738 { 1941 /* vcvtp */, ARM::VCVTPNUDh, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_u16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 9739 { 1941 /* vcvtp */, ARM::VCVTPNUQf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 9740 { 1941 /* vcvtp */, ARM::VCVTPNUDf, Convert__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_u32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 9741 { 1941 /* vcvtp */, ARM::VCVTPUS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9742 { 1941 /* vcvtp */, ARM::VCVTPUD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9743 { 1941 /* vcvtp */, ARM::VCVTPUH, Convert__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9744 { 1947 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9745 { 1947 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9746 { 1947 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9747 { 1947 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9748 { 1947 /* vcvtr */, ARM::VTOUIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9749 { 1947 /* vcvtr */, ARM::VTOUIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9750 { 1953 /* vcvtt */, ARM::VCVTTHS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9751 { 1953 /* vcvtt */, ARM::VCVTTHD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, }, 9752 { 1953 /* vcvtt */, ARM::VCVTTSH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9753 { 1953 /* vcvtt */, ARM::VCVTTDH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9754 { 1959 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 9755 { 1959 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 9756 { 1959 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9757 { 1959 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9758 { 1959 /* vdiv */, ARM::VDIVD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9759 { 1959 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9760 { 1964 /* vdup */, ARM::VDUP16q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_GPR }, }, 9761 { 1964 /* vdup */, ARM::VDUP16d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_GPR }, }, 9762 { 1964 /* vdup */, ARM::VDUP32q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_GPR }, }, 9763 { 1964 /* vdup */, ARM::VDUP32d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_GPR }, }, 9764 { 1964 /* vdup */, ARM::VDUP8q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_GPR }, }, 9765 { 1964 /* vdup */, ARM::VDUP8d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_GPR }, }, 9766 { 1964 /* vdup */, ARM::VDUPLN16q, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_DPR, MCK_VectorIndex16 }, }, 9767 { 1964 /* vdup */, ARM::VDUPLN16d, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_VectorIndex16 }, }, 9768 { 1964 /* vdup */, ARM::VDUPLN32q, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_DPR, MCK_VectorIndex32 }, }, 9769 { 1964 /* vdup */, ARM::VDUPLN32d, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_VectorIndex32 }, }, 9770 { 1964 /* vdup */, ARM::VDUPLN8q, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_DPR, MCK_VectorIndex8 }, }, 9771 { 1964 /* vdup */, ARM::VDUPLN8d, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_VectorIndex8 }, }, 9772 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 9773 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 9774 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 9775 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 9776 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 9777 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 9778 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 9779 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 9780 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 9781 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 9782 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9783 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9784 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9785 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9786 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9787 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9788 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9789 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9790 { 1969 /* veor */, ARM::VEORq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9791 { 1969 /* veor */, ARM::VEORd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9792 { 1974 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 9793 { 1974 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_31_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, }, 9794 { 1974 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 9795 { 1974 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_11_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, }, 9796 { 1974 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 9797 { 1974 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 9798 { 1974 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_2__Reg1_3__Imm0_71_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, }, 9799 { 1974 /* vext */, ARM::VEXTq16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 9800 { 1974 /* vext */, ARM::VEXTd16, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_31_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_3 }, }, 9801 { 1974 /* vext */, ARM::VEXTq32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 9802 { 1974 /* vext */, ARM::VEXTd32, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_11_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_1 }, }, 9803 { 1974 /* vext */, ARM::VEXTq64, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 9804 { 1974 /* vext */, ARM::VEXTq8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_151_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR, MCK_Imm0_15 }, }, 9805 { 1974 /* vext */, ARM::VEXTd8, Convert__Reg1_2__Reg1_3__Reg1_4__Imm0_71_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR, MCK_Imm0_7 }, }, 9806 { 1979 /* vfma */, ARM::VFMAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9807 { 1979 /* vfma */, ARM::VFMAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9808 { 1979 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9809 { 1979 /* vfma */, ARM::VFMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9810 { 1979 /* vfma */, ARM::VFMAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9811 { 1979 /* vfma */, ARM::VFMAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9812 { 1979 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9813 { 1984 /* vfms */, ARM::VFMSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9814 { 1984 /* vfms */, ARM::VFMSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9815 { 1984 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9816 { 1984 /* vfms */, ARM::VFMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9817 { 1984 /* vfms */, ARM::VFMShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9818 { 1984 /* vfms */, ARM::VFMShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9819 { 1984 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9820 { 1989 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9821 { 1989 /* vfnma */, ARM::VFNMAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9822 { 1989 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9823 { 1995 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9824 { 1995 /* vfnms */, ARM::VFNMSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP4|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9825 { 1995 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 9826 { 2001 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 9827 { 2001 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 9828 { 2001 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 9829 { 2001 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 9830 { 2001 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 9831 { 2001 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 9832 { 2001 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 9833 { 2001 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 9834 { 2001 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 9835 { 2001 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 9836 { 2001 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 9837 { 2001 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 9838 { 2001 /* vhadd */, ARM::VHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9839 { 2001 /* vhadd */, ARM::VHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9840 { 2001 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9841 { 2001 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9842 { 2001 /* vhadd */, ARM::VHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9843 { 2001 /* vhadd */, ARM::VHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9844 { 2001 /* vhadd */, ARM::VHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9845 { 2001 /* vhadd */, ARM::VHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9846 { 2001 /* vhadd */, ARM::VHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9847 { 2001 /* vhadd */, ARM::VHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9848 { 2001 /* vhadd */, ARM::VHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9849 { 2001 /* vhadd */, ARM::VHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9850 { 2007 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 9851 { 2007 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 9852 { 2007 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 9853 { 2007 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 9854 { 2007 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 9855 { 2007 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 9856 { 2007 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 9857 { 2007 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 9858 { 2007 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 9859 { 2007 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 9860 { 2007 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 9861 { 2007 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 9862 { 2007 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9863 { 2007 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9864 { 2007 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9865 { 2007 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9866 { 2007 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9867 { 2007 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9868 { 2007 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9869 { 2007 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9870 { 2007 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9871 { 2007 /* vhsub */, ARM::VHSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9872 { 2007 /* vhsub */, ARM::VHSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 9873 { 2007 /* vhsub */, ARM::VHSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 9874 { 2013 /* vins */, ARM::VINSH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 9875 { 2018 /* vjcvt */, ARM::VJCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasV8_3a, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, }, 9876 { 2024 /* vld1 */, ARM::VLD1DUPq16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, }, 9877 { 2024 /* vld1 */, ARM::VLD1q16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 9878 { 2024 /* vld1 */, ARM::VLD1d16Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 9879 { 2024 /* vld1 */, ARM::VLD1DUPd16, Convert__VecListOneDAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16 }, }, 9880 { 2024 /* vld1 */, ARM::VLD1d16, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 9881 { 2024 /* vld1 */, ARM::VLD1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, }, 9882 { 2024 /* vld1 */, ARM::VLD1d16T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 9883 { 2024 /* vld1 */, ARM::VLD1DUPq32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, }, 9884 { 2024 /* vld1 */, ARM::VLD1q32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 9885 { 2024 /* vld1 */, ARM::VLD1d32Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 9886 { 2024 /* vld1 */, ARM::VLD1DUPd32, Convert__VecListOneDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32 }, }, 9887 { 2024 /* vld1 */, ARM::VLD1d32, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 9888 { 2024 /* vld1 */, ARM::VLD1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, }, 9889 { 2024 /* vld1 */, ARM::VLD1d32T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 9890 { 2024 /* vld1 */, ARM::VLD1q64, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 9891 { 2024 /* vld1 */, ARM::VLD1d64Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 9892 { 2024 /* vld1 */, ARM::VLD1d64, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 9893 { 2024 /* vld1 */, ARM::VLD1d64T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 9894 { 2024 /* vld1 */, ARM::VLD1DUPq8, Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone }, }, 9895 { 2024 /* vld1 */, ARM::VLD1q8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 9896 { 2024 /* vld1 */, ARM::VLD1d8Q, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 9897 { 2024 /* vld1 */, ARM::VLD1DUPd8, Convert__VecListOneDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone }, }, 9898 { 2024 /* vld1 */, ARM::VLD1d8, Convert__VecListOneD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 9899 { 2024 /* vld1 */, ARM::VLD1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, }, 9900 { 2024 /* vld1 */, ARM::VLD1d8T, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 9901 { 2024 /* vld1 */, ARM::VLD1DUPq16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 9902 { 2024 /* vld1 */, ARM::VLD1DUPq16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 9903 { 2024 /* vld1 */, ARM::VLD1q16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 9904 { 2024 /* vld1 */, ARM::VLD1q16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 9905 { 2024 /* vld1 */, ARM::VLD1d16Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 9906 { 2024 /* vld1 */, ARM::VLD1d16Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 9907 { 2024 /* vld1 */, ARM::VLD1DUPd16wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 9908 { 2024 /* vld1 */, ARM::VLD1DUPd16wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 9909 { 2024 /* vld1 */, ARM::VLD1d16wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 9910 { 2024 /* vld1 */, ARM::VLD1d16wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 9911 { 2024 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 9912 { 2024 /* vld1 */, ARM::VLD1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 9913 { 2024 /* vld1 */, ARM::VLD1d16Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 9914 { 2024 /* vld1 */, ARM::VLD1d16Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 9915 { 2024 /* vld1 */, ARM::VLD1DUPq32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 9916 { 2024 /* vld1 */, ARM::VLD1DUPq32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 9917 { 2024 /* vld1 */, ARM::VLD1q32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 9918 { 2024 /* vld1 */, ARM::VLD1q32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 9919 { 2024 /* vld1 */, ARM::VLD1d32Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 9920 { 2024 /* vld1 */, ARM::VLD1d32Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 9921 { 2024 /* vld1 */, ARM::VLD1DUPd32wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 9922 { 2024 /* vld1 */, ARM::VLD1DUPd32wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 9923 { 2024 /* vld1 */, ARM::VLD1d32wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 9924 { 2024 /* vld1 */, ARM::VLD1d32wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 9925 { 2024 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 9926 { 2024 /* vld1 */, ARM::VLD1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 9927 { 2024 /* vld1 */, ARM::VLD1d32Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 9928 { 2024 /* vld1 */, ARM::VLD1d32Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 9929 { 2024 /* vld1 */, ARM::VLD1q64wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 9930 { 2024 /* vld1 */, ARM::VLD1q64wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 9931 { 2024 /* vld1 */, ARM::VLD1d64Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 9932 { 2024 /* vld1 */, ARM::VLD1d64Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 9933 { 2024 /* vld1 */, ARM::VLD1d64wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 9934 { 2024 /* vld1 */, ARM::VLD1d64wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 9935 { 2024 /* vld1 */, ARM::VLD1d64Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 9936 { 2024 /* vld1 */, ARM::VLD1d64Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 9937 { 2024 /* vld1 */, ARM::VLD1DUPq8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 9938 { 2024 /* vld1 */, ARM::VLD1DUPq8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 9939 { 2024 /* vld1 */, ARM::VLD1q8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 9940 { 2024 /* vld1 */, ARM::VLD1q8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 9941 { 2024 /* vld1 */, ARM::VLD1d8Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 9942 { 2024 /* vld1 */, ARM::VLD1d8Qwb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 9943 { 2024 /* vld1 */, ARM::VLD1DUPd8wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 9944 { 2024 /* vld1 */, ARM::VLD1DUPd8wb_register, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 9945 { 2024 /* vld1 */, ARM::VLD1d8wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 9946 { 2024 /* vld1 */, ARM::VLD1d8wb_register, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 9947 { 2024 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 9948 { 2024 /* vld1 */, ARM::VLD1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 9949 { 2024 /* vld1 */, ARM::VLD1d8Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 9950 { 2024 /* vld1 */, ARM::VLD1d8Twb_register, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 9951 { 2024 /* vld1 */, ARM::VLD1LNd16, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 9952 { 2024 /* vld1 */, ARM::VLD1LNd8, Convert__Reg1_3__AlignedMemory2_8__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 9953 { 2024 /* vld1 */, ARM::VLD1LNd16_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 9954 { 2024 /* vld1 */, ARM::VLD1LNd32, Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, }, 9955 { 2024 /* vld1 */, ARM::VLD1LNd32_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 9956 { 2024 /* vld1 */, ARM::VLD1LNd8_UPD, Convert__Reg1_3__imm_95_0__AlignedMemory2_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 9957 { 2029 /* vld2 */, ARM::VLD2DUPd16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, }, 9958 { 2029 /* vld2 */, ARM::VLD2d16, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 9959 { 2029 /* vld2 */, ARM::VLD2DUPd16x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32 }, }, 9960 { 2029 /* vld2 */, ARM::VLD2b16, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 9961 { 2029 /* vld2 */, ARM::VLD2q16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 9962 { 2029 /* vld2 */, ARM::VLD2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, }, 9963 { 2029 /* vld2 */, ARM::VLD2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, }, 9964 { 2029 /* vld2 */, ARM::VLD2DUPd32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64 }, }, 9965 { 2029 /* vld2 */, ARM::VLD2d32, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 9966 { 2029 /* vld2 */, ARM::VLD2DUPd32x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64 }, }, 9967 { 2029 /* vld2 */, ARM::VLD2b32, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 9968 { 2029 /* vld2 */, ARM::VLD2q32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 9969 { 2029 /* vld2 */, ARM::VLD2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, }, 9970 { 2029 /* vld2 */, ARM::VLD2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, }, 9971 { 2029 /* vld2 */, ARM::VLD2DUPd8, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, }, 9972 { 2029 /* vld2 */, ARM::VLD2d8, Convert__VecListDPair1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 9973 { 2029 /* vld2 */, ARM::VLD2DUPd8x2, Convert__VecListDPairSpacedAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16 }, }, 9974 { 2029 /* vld2 */, ARM::VLD2b8, Convert__VecListDPairSpaced1_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 9975 { 2029 /* vld2 */, ARM::VLD2q8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 9976 { 2029 /* vld2 */, ARM::VLD2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, }, 9977 { 2029 /* vld2 */, ARM::VLD2DUPd16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 9978 { 2029 /* vld2 */, ARM::VLD2DUPd16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 9979 { 2029 /* vld2 */, ARM::VLD2d16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 9980 { 2029 /* vld2 */, ARM::VLD2d16wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 9981 { 2029 /* vld2 */, ARM::VLD2DUPd16x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 9982 { 2029 /* vld2 */, ARM::VLD2DUPd16x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 9983 { 2029 /* vld2 */, ARM::VLD2b16wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 9984 { 2029 /* vld2 */, ARM::VLD2b16wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 9985 { 2029 /* vld2 */, ARM::VLD2q16wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 9986 { 2029 /* vld2 */, ARM::VLD2q16wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 9987 { 2029 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 9988 { 2029 /* vld2 */, ARM::VLD2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 9989 { 2029 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 9990 { 2029 /* vld2 */, ARM::VLD2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 9991 { 2029 /* vld2 */, ARM::VLD2DUPd32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 9992 { 2029 /* vld2 */, ARM::VLD2DUPd32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 9993 { 2029 /* vld2 */, ARM::VLD2d32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 9994 { 2029 /* vld2 */, ARM::VLD2d32wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 9995 { 2029 /* vld2 */, ARM::VLD2DUPd32x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 9996 { 2029 /* vld2 */, ARM::VLD2DUPd32x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 9997 { 2029 /* vld2 */, ARM::VLD2b32wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 9998 { 2029 /* vld2 */, ARM::VLD2b32wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 9999 { 2029 /* vld2 */, ARM::VLD2q32wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 10000 { 2029 /* vld2 */, ARM::VLD2q32wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 10001 { 2029 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10002 { 2029 /* vld2 */, ARM::VLD2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 10003 { 2029 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10004 { 2029 /* vld2 */, ARM::VLD2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 10005 { 2029 /* vld2 */, ARM::VLD2DUPd8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 10006 { 2029 /* vld2 */, ARM::VLD2DUPd8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 10007 { 2029 /* vld2 */, ARM::VLD2d8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 10008 { 2029 /* vld2 */, ARM::VLD2d8wb_register, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 10009 { 2029 /* vld2 */, ARM::VLD2DUPd8x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 10010 { 2029 /* vld2 */, ARM::VLD2DUPd8x2wb_register, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 10011 { 2029 /* vld2 */, ARM::VLD2b8wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 10012 { 2029 /* vld2 */, ARM::VLD2b8wb_register, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 10013 { 2029 /* vld2 */, ARM::VLD2q8wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 10014 { 2029 /* vld2 */, ARM::VLD2q8wb_register, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 10015 { 2029 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 10016 { 2029 /* vld2 */, ARM::VLD2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 10017 { 2034 /* vld3 */, ARM::VLD3DUPdAsm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, }, 10018 { 2034 /* vld3 */, ARM::VLD3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 10019 { 2034 /* vld3 */, ARM::VLD3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, }, 10020 { 2034 /* vld3 */, ARM::VLD3DUPqAsm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, }, 10021 { 2034 /* vld3 */, ARM::VLD3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 10022 { 2034 /* vld3 */, ARM::VLD3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, }, 10023 { 2034 /* vld3 */, ARM::VLD3DUPdAsm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, }, 10024 { 2034 /* vld3 */, ARM::VLD3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 10025 { 2034 /* vld3 */, ARM::VLD3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, }, 10026 { 2034 /* vld3 */, ARM::VLD3DUPqAsm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, }, 10027 { 2034 /* vld3 */, ARM::VLD3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 10028 { 2034 /* vld3 */, ARM::VLD3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, }, 10029 { 2034 /* vld3 */, ARM::VLD3DUPdAsm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone }, }, 10030 { 2034 /* vld3 */, ARM::VLD3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 10031 { 2034 /* vld3 */, ARM::VLD3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, }, 10032 { 2034 /* vld3 */, ARM::VLD3DUPqAsm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, }, 10033 { 2034 /* vld3 */, ARM::VLD3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 10034 { 2034 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 10035 { 2034 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 10036 { 2034 /* vld3 */, ARM::VLD3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10037 { 2034 /* vld3 */, ARM::VLD3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 10038 { 2034 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 10039 { 2034 /* vld3 */, ARM::VLD3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 10040 { 2034 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 10041 { 2034 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 10042 { 2034 /* vld3 */, ARM::VLD3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10043 { 2034 /* vld3 */, ARM::VLD3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 10044 { 2034 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 10045 { 2034 /* vld3 */, ARM::VLD3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 10046 { 2034 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 10047 { 2034 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 10048 { 2034 /* vld3 */, ARM::VLD3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10049 { 2034 /* vld3 */, ARM::VLD3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 10050 { 2034 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 10051 { 2034 /* vld3 */, ARM::VLD3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 10052 { 2034 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 10053 { 2034 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 10054 { 2034 /* vld3 */, ARM::VLD3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10055 { 2034 /* vld3 */, ARM::VLD3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 10056 { 2034 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 10057 { 2034 /* vld3 */, ARM::VLD3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 10058 { 2034 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 10059 { 2034 /* vld3 */, ARM::VLD3DUPdWB_register_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 10060 { 2034 /* vld3 */, ARM::VLD3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10061 { 2034 /* vld3 */, ARM::VLD3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 10062 { 2034 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 10063 { 2034 /* vld3 */, ARM::VLD3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 10064 { 2034 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 10065 { 2034 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 10066 { 2034 /* vld3 */, ARM::VLD3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10067 { 2034 /* vld3 */, ARM::VLD3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 10068 { 2034 /* vld3 */, ARM::VLD3d16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10069 { 2034 /* vld3 */, ARM::VLD3q16, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10070 { 2034 /* vld3 */, ARM::VLD3d32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10071 { 2034 /* vld3 */, ARM::VLD3q32, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10072 { 2034 /* vld3 */, ARM::VLD3d8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10073 { 2034 /* vld3 */, ARM::VLD3q8, Convert__Reg1_3__Reg1_4__Reg1_5__AlignedMemory2_7__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10074 { 2034 /* vld3 */, ARM::VLD3d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10075 { 2034 /* vld3 */, ARM::VLD3q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10076 { 2034 /* vld3 */, ARM::VLD3d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10077 { 2034 /* vld3 */, ARM::VLD3q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10078 { 2034 /* vld3 */, ARM::VLD3d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10079 { 2034 /* vld3 */, ARM::VLD3q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__imm_95_0__AlignedMemory2_7__Imm1_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10080 { 2034 /* vld3 */, ARM::VLD3DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10081 { 2034 /* vld3 */, ARM::VLD3DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10082 { 2034 /* vld3 */, ARM::VLD3DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10083 { 2034 /* vld3 */, ARM::VLD3DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10084 { 2034 /* vld3 */, ARM::VLD3DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10085 { 2034 /* vld3 */, ARM::VLD3DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__AlignedMemory2_13__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10086 { 2034 /* vld3 */, ARM::VLD3DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 10087 { 2034 /* vld3 */, ARM::VLD3DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 10088 { 2034 /* vld3 */, ARM::VLD3DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 10089 { 2034 /* vld3 */, ARM::VLD3DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 10090 { 2034 /* vld3 */, ARM::VLD3DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 10091 { 2034 /* vld3 */, ARM::VLD3DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__imm_95_0__DupAlignedMemory642_13__Imm1_14__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_DupAlignedMemory64, MCK_Imm }, }, 10092 { 2039 /* vld4 */, ARM::VLD4DUPdAsm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64 }, }, 10093 { 2039 /* vld4 */, ARM::VLD4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 10094 { 2039 /* vld4 */, ARM::VLD4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, }, 10095 { 2039 /* vld4 */, ARM::VLD4DUPqAsm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64 }, }, 10096 { 2039 /* vld4 */, ARM::VLD4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 10097 { 2039 /* vld4 */, ARM::VLD4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, }, 10098 { 2039 /* vld4 */, ARM::VLD4DUPdAsm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128 }, }, 10099 { 2039 /* vld4 */, ARM::VLD4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 10100 { 2039 /* vld4 */, ARM::VLD4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, }, 10101 { 2039 /* vld4 */, ARM::VLD4DUPqAsm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128 }, }, 10102 { 2039 /* vld4 */, ARM::VLD4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 10103 { 2039 /* vld4 */, ARM::VLD4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, }, 10104 { 2039 /* vld4 */, ARM::VLD4DUPdAsm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32 }, }, 10105 { 2039 /* vld4 */, ARM::VLD4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 10106 { 2039 /* vld4 */, ARM::VLD4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, }, 10107 { 2039 /* vld4 */, ARM::VLD4DUPqAsm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32 }, }, 10108 { 2039 /* vld4 */, ARM::VLD4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 10109 { 2039 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 10110 { 2039 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 10111 { 2039 /* vld4 */, ARM::VLD4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 10112 { 2039 /* vld4 */, ARM::VLD4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 10113 { 2039 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10114 { 2039 /* vld4 */, ARM::VLD4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 10115 { 2039 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 10116 { 2039 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 10117 { 2039 /* vld4 */, ARM::VLD4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 10118 { 2039 /* vld4 */, ARM::VLD4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 10119 { 2039 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 10120 { 2039 /* vld4 */, ARM::VLD4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 10121 { 2039 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, }, 10122 { 2039 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, }, 10123 { 2039 /* vld4 */, ARM::VLD4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 10124 { 2039 /* vld4 */, ARM::VLD4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 10125 { 2039 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 10126 { 2039 /* vld4 */, ARM::VLD4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 10127 { 2039 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, }, 10128 { 2039 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, }, 10129 { 2039 /* vld4 */, ARM::VLD4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 10130 { 2039 /* vld4 */, ARM::VLD4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 10131 { 2039 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 10132 { 2039 /* vld4 */, ARM::VLD4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 10133 { 2039 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 10134 { 2039 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 10135 { 2039 /* vld4 */, ARM::VLD4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 10136 { 2039 /* vld4 */, ARM::VLD4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 10137 { 2039 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 10138 { 2039 /* vld4 */, ARM::VLD4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 10139 { 2039 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 10140 { 2039 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 10141 { 2039 /* vld4 */, ARM::VLD4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 10142 { 2039 /* vld4 */, ARM::VLD4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 10143 { 2039 /* vld4 */, ARM::VLD4d16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10144 { 2039 /* vld4 */, ARM::VLD4q16, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10145 { 2039 /* vld4 */, ARM::VLD4d32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10146 { 2039 /* vld4 */, ARM::VLD4q32, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10147 { 2039 /* vld4 */, ARM::VLD4d8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10148 { 2039 /* vld4 */, ARM::VLD4q8, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__AlignedMemory2_8__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 10149 { 2039 /* vld4 */, ARM::VLD4d16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10150 { 2039 /* vld4 */, ARM::VLD4q16_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10151 { 2039 /* vld4 */, ARM::VLD4d32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10152 { 2039 /* vld4 */, ARM::VLD4q32_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10153 { 2039 /* vld4 */, ARM::VLD4d8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10154 { 2039 /* vld4 */, ARM::VLD4q8_UPD, Convert__Reg1_3__Reg1_4__Reg1_5__Reg1_6__imm_95_0__AlignedMemory2_8__Imm1_9__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10155 { 2039 /* vld4 */, ARM::VLD4DUPd16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10156 { 2039 /* vld4 */, ARM::VLD4DUPq16, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10157 { 2039 /* vld4 */, ARM::VLD4DUPd32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10158 { 2039 /* vld4 */, ARM::VLD4DUPq32, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10159 { 2039 /* vld4 */, ARM::VLD4DUPd8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10160 { 2039 /* vld4 */, ARM::VLD4DUPq8, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__AlignedMemory2_16__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 10161 { 2039 /* vld4 */, ARM::VLD4DUPd16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10162 { 2039 /* vld4 */, ARM::VLD4DUPq16_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10163 { 2039 /* vld4 */, ARM::VLD4DUPd32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10164 { 2039 /* vld4 */, ARM::VLD4DUPq32_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10165 { 2039 /* vld4 */, ARM::VLD4DUPd8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10166 { 2039 /* vld4 */, ARM::VLD4DUPq8_UPD, Convert__Reg1_3__Reg1_6__Reg1_9__Reg1_12__imm_95_0__AlignedMemory2_16__Imm1_17__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK_DPR, MCK__91_, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 10167 { 2044 /* vldmdb */, ARM::VLDMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 10168 { 2044 /* vldmdb */, ARM::VLDMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 10169 { 2051 /* vldmia */, ARM::VLDMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 10170 { 2051 /* vldmia */, ARM::VLDMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, }, 10171 { 2051 /* vldmia */, ARM::VLDMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 10172 { 2051 /* vldmia */, ARM::VLDMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 10173 { 2058 /* vldr */, ARM::VLDRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, }, 10174 { 2058 /* vldr */, ARM::VLDRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, }, 10175 { 2058 /* vldr */, ARM::VLDRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, }, 10176 { 2058 /* vldr */, ARM::VLDRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, }, 10177 { 2058 /* vldr */, ARM::VLDRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, }, 10178 { 2063 /* vlldm */, ARM::VLLDM, Convert__Reg1_1__CondCode2_0, Feature_HasV8MMainline|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, }, 10179 { 2069 /* vlstm */, ARM::VLSTM, Convert__Reg1_1__CondCode2_0, Feature_HasV8MMainline|Feature_Has8MSecExt, { MCK_CondCode, MCK_GPRnopc }, }, 10180 { 2075 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10181 { 2075 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10182 { 2075 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10183 { 2075 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10184 { 2075 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10185 { 2075 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10186 { 2075 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 10187 { 2075 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10188 { 2075 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10189 { 2075 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10190 { 2075 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 10191 { 2075 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10192 { 2075 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10193 { 2075 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10194 { 2075 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10195 { 2075 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10196 { 2075 /* vmax */, ARM::VMAXsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10197 { 2075 /* vmax */, ARM::VMAXsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10198 { 2075 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10199 { 2075 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10200 { 2075 /* vmax */, ARM::VMAXsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10201 { 2075 /* vmax */, ARM::VMAXsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10202 { 2075 /* vmax */, ARM::VMAXuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10203 { 2075 /* vmax */, ARM::VMAXuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10204 { 2075 /* vmax */, ARM::VMAXuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10205 { 2075 /* vmax */, ARM::VMAXuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10206 { 2075 /* vmax */, ARM::VMAXuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10207 { 2075 /* vmax */, ARM::VMAXuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10208 { 2075 /* vmax */, ARM::VMAXfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10209 { 2075 /* vmax */, ARM::VMAXfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10210 { 2075 /* vmax */, ARM::VMAXhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10211 { 2075 /* vmax */, ARM::VMAXhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10212 { 2080 /* vmaxnm */, ARM::VMAXNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10213 { 2080 /* vmaxnm */, ARM::VMAXNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10214 { 2080 /* vmaxnm */, ARM::VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10215 { 2080 /* vmaxnm */, ARM::VMAXNMD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10216 { 2080 /* vmaxnm */, ARM::VMAXNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10217 { 2080 /* vmaxnm */, ARM::VMAXNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10218 { 2080 /* vmaxnm */, ARM::VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10219 { 2087 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10220 { 2087 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10221 { 2087 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10222 { 2087 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10223 { 2087 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10224 { 2087 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10225 { 2087 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 10226 { 2087 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10227 { 2087 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10228 { 2087 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10229 { 2087 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 10230 { 2087 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10231 { 2087 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10232 { 2087 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10233 { 2087 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10234 { 2087 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10235 { 2087 /* vmin */, ARM::VMINsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10236 { 2087 /* vmin */, ARM::VMINsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10237 { 2087 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10238 { 2087 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10239 { 2087 /* vmin */, ARM::VMINsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10240 { 2087 /* vmin */, ARM::VMINsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10241 { 2087 /* vmin */, ARM::VMINuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10242 { 2087 /* vmin */, ARM::VMINuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10243 { 2087 /* vmin */, ARM::VMINuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10244 { 2087 /* vmin */, ARM::VMINuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10245 { 2087 /* vmin */, ARM::VMINuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10246 { 2087 /* vmin */, ARM::VMINuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10247 { 2087 /* vmin */, ARM::VMINfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10248 { 2087 /* vmin */, ARM::VMINfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10249 { 2087 /* vmin */, ARM::VMINhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10250 { 2087 /* vmin */, ARM::VMINhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10251 { 2092 /* vminnm */, ARM::VMINNMNQf, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10252 { 2092 /* vminnm */, ARM::VMINNMNDf, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10253 { 2092 /* vminnm */, ARM::VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10254 { 2092 /* vminnm */, ARM::VMINNMD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10255 { 2092 /* vminnm */, ARM::VMINNMNQh, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10256 { 2092 /* vminnm */, ARM::VMINNMNDh, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10257 { 2092 /* vminnm */, ARM::VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10258 { 2099 /* vmla */, ARM::VMLAfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10259 { 2099 /* vmla */, ARM::VMLAfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10260 { 2099 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10261 { 2099 /* vmla */, ARM::VMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10262 { 2099 /* vmla */, ARM::VMLAv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10263 { 2099 /* vmla */, ARM::VMLAv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10264 { 2099 /* vmla */, ARM::VMLAv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10265 { 2099 /* vmla */, ARM::VMLAv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10266 { 2099 /* vmla */, ARM::VMLAv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10267 { 2099 /* vmla */, ARM::VMLAv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10268 { 2099 /* vmla */, ARM::VMLAhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10269 { 2099 /* vmla */, ARM::VMLAhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10270 { 2099 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10271 { 2099 /* vmla */, ARM::VMLAslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10272 { 2099 /* vmla */, ARM::VMLAslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10273 { 2099 /* vmla */, ARM::VMLAslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10274 { 2099 /* vmla */, ARM::VMLAslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10275 { 2099 /* vmla */, ARM::VMLAslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10276 { 2099 /* vmla */, ARM::VMLAslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10277 { 2099 /* vmla */, ARM::VMLAslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10278 { 2099 /* vmla */, ARM::VMLAslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10279 { 2104 /* vmlal */, ARM::VMLALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10280 { 2104 /* vmlal */, ARM::VMLALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10281 { 2104 /* vmlal */, ARM::VMLALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10282 { 2104 /* vmlal */, ARM::VMLALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10283 { 2104 /* vmlal */, ARM::VMLALuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10284 { 2104 /* vmlal */, ARM::VMLALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10285 { 2104 /* vmlal */, ARM::VMLALslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10286 { 2104 /* vmlal */, ARM::VMLALslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10287 { 2104 /* vmlal */, ARM::VMLALsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10288 { 2104 /* vmlal */, ARM::VMLALsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10289 { 2110 /* vmls */, ARM::VMLSfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10290 { 2110 /* vmls */, ARM::VMLSfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10291 { 2110 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10292 { 2110 /* vmls */, ARM::VMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10293 { 2110 /* vmls */, ARM::VMLSv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10294 { 2110 /* vmls */, ARM::VMLSv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10295 { 2110 /* vmls */, ARM::VMLSv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10296 { 2110 /* vmls */, ARM::VMLSv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10297 { 2110 /* vmls */, ARM::VMLSv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10298 { 2110 /* vmls */, ARM::VMLSv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10299 { 2110 /* vmls */, ARM::VMLShq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10300 { 2110 /* vmls */, ARM::VMLShd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10301 { 2110 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10302 { 2110 /* vmls */, ARM::VMLSslfq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10303 { 2110 /* vmls */, ARM::VMLSslfd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10304 { 2110 /* vmls */, ARM::VMLSslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10305 { 2110 /* vmls */, ARM::VMLSslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10306 { 2110 /* vmls */, ARM::VMLSslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10307 { 2110 /* vmls */, ARM::VMLSslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10308 { 2110 /* vmls */, ARM::VMLSslhq, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10309 { 2110 /* vmls */, ARM::VMLSslhd, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10310 { 2115 /* vmlsl */, ARM::VMLSLsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10311 { 2115 /* vmlsl */, ARM::VMLSLsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10312 { 2115 /* vmlsl */, ARM::VMLSLsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10313 { 2115 /* vmlsl */, ARM::VMLSLuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10314 { 2115 /* vmlsl */, ARM::VMLSLuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10315 { 2115 /* vmlsl */, ARM::VMLSLuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10316 { 2115 /* vmlsl */, ARM::VMLSLslsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10317 { 2115 /* vmlsl */, ARM::VMLSLslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10318 { 2115 /* vmlsl */, ARM::VMLSLsluv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10319 { 2115 /* vmlsl */, ARM::VMLSLsluv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10320 { 2121 /* vmov */, ARM::VMOVRS, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_HPR }, }, 10321 { 2121 /* vmov */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 10322 { 2121 /* vmov */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 10323 { 2121 /* vmov */, ARM::VMOVSR, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_GPR }, }, 10324 { 2121 /* vmov */, ARM::VMOVS, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, }, 10325 { 2121 /* vmov */, ARM::VMOVv4f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_FPImm }, }, 10326 { 2121 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_NEONi32vmov }, }, 10327 { 2121 /* vmov */, ARM::VMOVv2f32, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_FPImm }, }, 10328 { 2121 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_NEONi32vmov }, }, 10329 { 2121 /* vmov */, ARM::VMOVS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10330 { 2121 /* vmov */, ARM::FCONSTS, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasVFP3, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_FPImm }, }, 10331 { 2121 /* vmov */, ARM::VMOVD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10332 { 2121 /* vmov */, ARM::FCONSTD, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasVFP3|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_FPImm }, }, 10333 { 2121 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16vmovi8Replicate }, }, 10334 { 2121 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 10335 { 2121 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16vmovi8Replicate }, }, 10336 { 2121 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 10337 { 2121 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi8Replicate }, }, 10338 { 2121 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, }, 10339 { 2121 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, }, 10340 { 2121 /* vmov */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, }, 10341 { 2121 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi8Replicate }, }, 10342 { 2121 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, }, 10343 { 2121 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, }, 10344 { 2121 /* vmov */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, }, 10345 { 2121 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi8Replicate }, }, 10346 { 2121 /* vmov */, ARM::VMOVv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, }, 10347 { 2121 /* vmov */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, }, 10348 { 2121 /* vmov */, ARM::VMOVv2i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64splat }, }, 10349 { 2121 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64vmovi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi8Replicate }, }, 10350 { 2121 /* vmov */, ARM::VMOVv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, }, 10351 { 2121 /* vmov */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, }, 10352 { 2121 /* vmov */, ARM::VMOVv1i64, Convert__Reg1_2__NEONi64splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64splat }, }, 10353 { 2121 /* vmov */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_NEONi8splat }, }, 10354 { 2121 /* vmov */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi8splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_NEONi8splat }, }, 10355 { 2121 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_GPR, MCK_HPR }, }, 10356 { 2121 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 10357 { 2121 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 10358 { 2121 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_GPR }, }, 10359 { 2121 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_HPR }, }, 10360 { 2121 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 10361 { 2121 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 10362 { 2121 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_GPR }, }, 10363 { 2121 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 10364 { 2121 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 10365 { 2121 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_GPR, MCK_HPR }, }, 10366 { 2121 /* vmov */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10367 { 2121 /* vmov */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 10368 { 2121 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_HPR, MCK_GPR }, }, 10369 { 2121 /* vmov */, ARM::VMOVRH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_GPR, MCK_HPR }, }, 10370 { 2121 /* vmov */, ARM::VMOVHR, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_GPR }, }, 10371 { 2121 /* vmov */, ARM::FCONSTH, Convert__Reg1_2__FPImm1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_FPImm }, }, 10372 { 2121 /* vmov */, ARM::VMOVRRD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_DPR }, }, 10373 { 2121 /* vmov */, ARM::VMOVDRR, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_GPR, MCK_GPR }, }, 10374 { 2121 /* vmov */, ARM::VGETLNs16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, }, 10375 { 2121 /* vmov */, ARM::VGETLNs8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, }, 10376 { 2121 /* vmov */, ARM::VGETLNu16, Convert__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_GPR, MCK_DPR, MCK_VectorIndex16 }, }, 10377 { 2121 /* vmov */, ARM::VGETLNu8, Convert__Reg1_2__Reg1_3__VectorIndex81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_GPR, MCK_DPR, MCK_VectorIndex8 }, }, 10378 { 2121 /* vmov */, ARM::VMOVRRD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_GPR, MCK_GPR, MCK_DPR }, }, 10379 { 2121 /* vmov */, ARM::VMOVDRR, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_GPR, MCK_GPR }, }, 10380 { 2121 /* vmov */, ARM::VSETLNi16, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_VectorIndex16, MCK_GPR }, }, 10381 { 2121 /* vmov */, ARM::VGETLNi32, Convert__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_DPR, MCK_VectorIndex32 }, }, 10382 { 2121 /* vmov */, ARM::VSETLNi32, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex321_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_VectorIndex32, MCK_GPR }, }, 10383 { 2121 /* vmov */, ARM::VSETLNi8, Convert__Reg1_2__Tie0_1_1__Reg1_4__VectorIndex81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VectorIndex8, MCK_GPR }, }, 10384 { 2121 /* vmov */, ARM::VMOVRRS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_HPR, MCK_HPR }, }, 10385 { 2121 /* vmov */, ARM::VMOVSRR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_GPR, MCK_GPR }, }, 10386 { 2126 /* vmovl */, ARM::VMOVLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, }, 10387 { 2126 /* vmovl */, ARM::VMOVLsv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, }, 10388 { 2126 /* vmovl */, ARM::VMOVLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, }, 10389 { 2126 /* vmovl */, ARM::VMOVLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, }, 10390 { 2126 /* vmovl */, ARM::VMOVLuv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, }, 10391 { 2126 /* vmovl */, ARM::VMOVLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, }, 10392 { 2132 /* vmovn */, ARM::VMOVNv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR }, }, 10393 { 2132 /* vmovn */, ARM::VMOVNv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR }, }, 10394 { 2132 /* vmovn */, ARM::VMOVNv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR }, }, 10395 { 2138 /* vmovx */, ARM::VMOVH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 10396 { 2144 /* vmrs */, ARM::FMSTAT, Convert__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_APSR_NZCV, MCK_FPSCR }, }, 10397 { 2144 /* vmrs */, ARM::VMRS_FPEXC, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPEXC }, }, 10398 { 2144 /* vmrs */, ARM::VMRS_FPINST, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST }, }, 10399 { 2144 /* vmrs */, ARM::VMRS_FPINST2, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPINST2 }, }, 10400 { 2144 /* vmrs */, ARM::VMRS, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPSCR }, }, 10401 { 2144 /* vmrs */, ARM::VMRS_FPSID, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_FPSID }, }, 10402 { 2144 /* vmrs */, ARM::VMRS_MVFR0, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR0 }, }, 10403 { 2144 /* vmrs */, ARM::VMRS_MVFR1, Convert__Reg1_1__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR1 }, }, 10404 { 2144 /* vmrs */, ARM::VMRS_MVFR2, Convert__Reg1_1__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK_GPRnopc, MCK_MVFR2 }, }, 10405 { 2149 /* vmsr */, ARM::VMSR_FPEXC, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPEXC, MCK_GPRnopc }, }, 10406 { 2149 /* vmsr */, ARM::VMSR_FPINST, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPINST, MCK_GPRnopc }, }, 10407 { 2149 /* vmsr */, ARM::VMSR_FPINST2, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPINST2, MCK_GPRnopc }, }, 10408 { 2149 /* vmsr */, ARM::VMSR, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPSCR, MCK_GPRnopc }, }, 10409 { 2149 /* vmsr */, ARM::VMSR_FPSID, Convert__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_FPSID, MCK_GPRnopc }, }, 10410 { 2154 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10411 { 2154 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10412 { 2154 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10413 { 2154 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10414 { 2154 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 10415 { 2154 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 10416 { 2154 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 10417 { 2154 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 10418 { 2154 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 10419 { 2154 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 10420 { 2154 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR }, }, 10421 { 2154 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR }, }, 10422 { 2154 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10423 { 2154 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10424 { 2154 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 10425 { 2154 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10426 { 2154 /* vmul */, ARM::VMULfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10427 { 2154 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10428 { 2154 /* vmul */, ARM::VMULfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10429 { 2154 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10430 { 2154 /* vmul */, ARM::VMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10431 { 2154 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10432 { 2154 /* vmul */, ARM::VMULv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10433 { 2154 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10434 { 2154 /* vmul */, ARM::VMULv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10435 { 2154 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10436 { 2154 /* vmul */, ARM::VMULv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10437 { 2154 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10438 { 2154 /* vmul */, ARM::VMULv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10439 { 2154 /* vmul */, ARM::VMULv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10440 { 2154 /* vmul */, ARM::VMULv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10441 { 2154 /* vmul */, ARM::VMULpq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10442 { 2154 /* vmul */, ARM::VMULpd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10443 { 2154 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10444 { 2154 /* vmul */, ARM::VMULhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10445 { 2154 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_2__Reg1_3__VectorIndex161_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10446 { 2154 /* vmul */, ARM::VMULhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10447 { 2154 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10448 { 2154 /* vmul */, ARM::VMULslfq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10449 { 2154 /* vmul */, ARM::VMULslfd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10450 { 2154 /* vmul */, ARM::VMULslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10451 { 2154 /* vmul */, ARM::VMULslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10452 { 2154 /* vmul */, ARM::VMULslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10453 { 2154 /* vmul */, ARM::VMULslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10454 { 2154 /* vmul */, ARM::VMULslhq, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10455 { 2154 /* vmul */, ARM::VMULslhd, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10456 { 2159 /* vmull */, ARM::VMULLp64, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasV8|Feature_HasCrypto, { MCK__DOT_p64, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10457 { 2159 /* vmull */, ARM::VMULLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10458 { 2159 /* vmull */, ARM::VMULLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10459 { 2159 /* vmull */, ARM::VMULLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10460 { 2159 /* vmull */, ARM::VMULLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10461 { 2159 /* vmull */, ARM::VMULLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10462 { 2159 /* vmull */, ARM::VMULLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10463 { 2159 /* vmull */, ARM::VMULLp8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_p8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10464 { 2159 /* vmull */, ARM::VMULLslsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10465 { 2159 /* vmull */, ARM::VMULLslsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10466 { 2159 /* vmull */, ARM::VMULLsluv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10467 { 2159 /* vmull */, ARM::VMULLsluv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10468 { 2165 /* vmvn */, ARM::VMVNq, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 10469 { 2165 /* vmvn */, ARM::VMVNd, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 10470 { 2165 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16invi8Replicate }, }, 10471 { 2165 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 10472 { 2165 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi16invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16invi8Replicate }, }, 10473 { 2165 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi16splat1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 10474 { 2165 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32invi8Replicate }, }, 10475 { 2165 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovi16Replicate }, }, 10476 { 2165 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmov }, }, 10477 { 2165 /* vmvn */, ARM::VMOVv4i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32vmovNeg }, }, 10478 { 2165 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi32invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32invi8Replicate }, }, 10479 { 2165 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi32vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovi16Replicate }, }, 10480 { 2165 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi32vmov1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmov }, }, 10481 { 2165 /* vmvn */, ARM::VMOVv2i32, Convert__Reg1_2__NEONi32vmovNeg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32vmovNeg }, }, 10482 { 2165 /* vmvn */, ARM::VMOVv16i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64invi8Replicate }, }, 10483 { 2165 /* vmvn */, ARM::VMVNv8i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi16Replicate }, }, 10484 { 2165 /* vmvn */, ARM::VMVNv4i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_NEONi64vmovi32Replicate }, }, 10485 { 2165 /* vmvn */, ARM::VMOVv8i8, Convert__Reg1_2__NEONi64invi8Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64invi8Replicate }, }, 10486 { 2165 /* vmvn */, ARM::VMVNv4i16, Convert__Reg1_2__NEONi64vmovi16Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi16Replicate }, }, 10487 { 2165 /* vmvn */, ARM::VMVNv2i32, Convert__Reg1_2__NEONi64vmovi32Replicate1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_NEONi64vmovi32Replicate }, }, 10488 { 2165 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 10489 { 2165 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 10490 { 2165 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 10491 { 2165 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 10492 { 2165 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 10493 { 2165 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 10494 { 2165 /* vmvn */, ARM::VMVNq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10495 { 2165 /* vmvn */, ARM::VMVNd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 10496 { 2170 /* vneg */, ARM::VNEGs16q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10497 { 2170 /* vneg */, ARM::VNEGs16d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10498 { 2170 /* vneg */, ARM::VNEGs32q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10499 { 2170 /* vneg */, ARM::VNEGs32d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10500 { 2170 /* vneg */, ARM::VNEGs8q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10501 { 2170 /* vneg */, ARM::VNEGs8d, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10502 { 2170 /* vneg */, ARM::VNEGf32q, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10503 { 2170 /* vneg */, ARM::VNEGfd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10504 { 2170 /* vneg */, ARM::VNEGS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10505 { 2170 /* vneg */, ARM::VNEGD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10506 { 2170 /* vneg */, ARM::VNEGhq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10507 { 2170 /* vneg */, ARM::VNEGhd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10508 { 2170 /* vneg */, ARM::VNEGH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 10509 { 2175 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10510 { 2175 /* vnmla */, ARM::VNMLAD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10511 { 2175 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10512 { 2181 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10513 { 2181 /* vnmls */, ARM::VNMLSD, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10514 { 2181 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10515 { 2187 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10516 { 2187 /* vnmul */, ARM::VNMULD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10517 { 2187 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 10518 { 2193 /* vorn */, ARM::VORNq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10519 { 2193 /* vorn */, ARM::VORNd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10520 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 10521 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_1__Reg1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 10522 { 2198 /* vorr */, ARM::VORRiv8i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_NEONi16splat }, }, 10523 { 2198 /* vorr */, ARM::VORRiv4i16, Convert__Reg1_2__NEONi16splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_NEONi16splat }, }, 10524 { 2198 /* vorr */, ARM::VORRiv4i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_NEONi32splat }, }, 10525 { 2198 /* vorr */, ARM::VORRiv2i32, Convert__Reg1_2__NEONi32splat1_3__Tie0_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_NEONi32splat }, }, 10526 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 10527 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 10528 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 10529 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 10530 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 10531 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 10532 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10533 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 10534 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10535 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10536 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10537 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10538 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10539 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10540 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10541 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10542 { 2198 /* vorr */, ARM::VORRq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10543 { 2198 /* vorr */, ARM::VORRd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10544 { 2203 /* vpadal */, ARM::VPADALsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10545 { 2203 /* vpadal */, ARM::VPADALsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10546 { 2203 /* vpadal */, ARM::VPADALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10547 { 2203 /* vpadal */, ARM::VPADALsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10548 { 2203 /* vpadal */, ARM::VPADALsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10549 { 2203 /* vpadal */, ARM::VPADALsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10550 { 2203 /* vpadal */, ARM::VPADALuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 10551 { 2203 /* vpadal */, ARM::VPADALuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10552 { 2203 /* vpadal */, ARM::VPADALuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10553 { 2203 /* vpadal */, ARM::VPADALuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10554 { 2203 /* vpadal */, ARM::VPADALuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 10555 { 2203 /* vpadal */, ARM::VPADALuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10556 { 2210 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10557 { 2210 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 10558 { 2210 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 10559 { 2210 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 10560 { 2210 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10561 { 2210 /* vpadd */, ARM::VPADDf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10562 { 2210 /* vpadd */, ARM::VPADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10563 { 2210 /* vpadd */, ARM::VPADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10564 { 2210 /* vpadd */, ARM::VPADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10565 { 2210 /* vpadd */, ARM::VPADDh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10566 { 2216 /* vpaddl */, ARM::VPADDLsv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10567 { 2216 /* vpaddl */, ARM::VPADDLsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10568 { 2216 /* vpaddl */, ARM::VPADDLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10569 { 2216 /* vpaddl */, ARM::VPADDLsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10570 { 2216 /* vpaddl */, ARM::VPADDLsv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10571 { 2216 /* vpaddl */, ARM::VPADDLsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10572 { 2216 /* vpaddl */, ARM::VPADDLuv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 10573 { 2216 /* vpaddl */, ARM::VPADDLuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10574 { 2216 /* vpaddl */, ARM::VPADDLuv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10575 { 2216 /* vpaddl */, ARM::VPADDLuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10576 { 2216 /* vpaddl */, ARM::VPADDLuv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 10577 { 2216 /* vpaddl */, ARM::VPADDLuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10578 { 2223 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10579 { 2223 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10580 { 2223 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10581 { 2223 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10582 { 2223 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10583 { 2223 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10584 { 2223 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10585 { 2223 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10586 { 2223 /* vpmax */, ARM::VPMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10587 { 2223 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10588 { 2223 /* vpmax */, ARM::VPMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10589 { 2223 /* vpmax */, ARM::VPMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10590 { 2223 /* vpmax */, ARM::VPMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10591 { 2223 /* vpmax */, ARM::VPMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10592 { 2223 /* vpmax */, ARM::VPMAXf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10593 { 2223 /* vpmax */, ARM::VPMAXh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10594 { 2229 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10595 { 2229 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10596 { 2229 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10597 { 2229 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10598 { 2229 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10599 { 2229 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10600 { 2229 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10601 { 2229 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10602 { 2229 /* vpmin */, ARM::VPMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10603 { 2229 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10604 { 2229 /* vpmin */, ARM::VPMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10605 { 2229 /* vpmin */, ARM::VPMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10606 { 2229 /* vpmin */, ARM::VPMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10607 { 2229 /* vpmin */, ARM::VPMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10608 { 2229 /* vpmin */, ARM::VPMINf, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10609 { 2229 /* vpmin */, ARM::VPMINh, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10610 { 2235 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, Feature_HasVFP2, { MCK_CondCode, MCK_DPRRegList }, }, 10611 { 2235 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, Feature_HasVFP2, { MCK_CondCode, MCK_SPRRegList }, }, 10612 { 2235 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, }, 10613 { 2235 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, }, 10614 { 2235 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, }, 10615 { 2235 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, }, 10616 { 2235 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, }, 10617 { 2235 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, }, 10618 { 2235 /* vpop */, ARM::VLDMDIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, }, 10619 { 2235 /* vpop */, ARM::VLDMSIA_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, }, 10620 { 2240 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_1, Feature_HasVFP2, { MCK_CondCode, MCK_DPRRegList }, }, 10621 { 2240 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_1, Feature_HasVFP2, { MCK_CondCode, MCK_SPRRegList }, }, 10622 { 2240 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_DPRRegList }, }, 10623 { 2240 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_SPRRegList }, }, 10624 { 2240 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_DPRRegList }, }, 10625 { 2240 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_SPRRegList }, }, 10626 { 2240 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPRRegList }, }, 10627 { 2240 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_SPRRegList }, }, 10628 { 2240 /* vpush */, ARM::VSTMDDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_DPRRegList }, }, 10629 { 2240 /* vpush */, ARM::VSTMSDB_UPD, Convert__regSP__Tie0_1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_SPRRegList }, }, 10630 { 2246 /* vqabs */, ARM::VQABSv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10631 { 2246 /* vqabs */, ARM::VQABSv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10632 { 2246 /* vqabs */, ARM::VQABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10633 { 2246 /* vqabs */, ARM::VQABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10634 { 2246 /* vqabs */, ARM::VQABSv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10635 { 2246 /* vqabs */, ARM::VQABSv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10636 { 2252 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10637 { 2252 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10638 { 2252 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10639 { 2252 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10640 { 2252 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 10641 { 2252 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 10642 { 2252 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10643 { 2252 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10644 { 2252 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 10645 { 2252 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10646 { 2252 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10647 { 2252 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10648 { 2252 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 10649 { 2252 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 10650 { 2252 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 10651 { 2252 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10652 { 2252 /* vqadd */, ARM::VQADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10653 { 2252 /* vqadd */, ARM::VQADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10654 { 2252 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10655 { 2252 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10656 { 2252 /* vqadd */, ARM::VQADDsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10657 { 2252 /* vqadd */, ARM::VQADDsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10658 { 2252 /* vqadd */, ARM::VQADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10659 { 2252 /* vqadd */, ARM::VQADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10660 { 2252 /* vqadd */, ARM::VQADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10661 { 2252 /* vqadd */, ARM::VQADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10662 { 2252 /* vqadd */, ARM::VQADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10663 { 2252 /* vqadd */, ARM::VQADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10664 { 2252 /* vqadd */, ARM::VQADDuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10665 { 2252 /* vqadd */, ARM::VQADDuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10666 { 2252 /* vqadd */, ARM::VQADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10667 { 2252 /* vqadd */, ARM::VQADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10668 { 2258 /* vqdmlal */, ARM::VQDMLALv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10669 { 2258 /* vqdmlal */, ARM::VQDMLALv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10670 { 2258 /* vqdmlal */, ARM::VQDMLALslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10671 { 2258 /* vqdmlal */, ARM::VQDMLALslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10672 { 2266 /* vqdmlsl */, ARM::VQDMLSLv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10673 { 2266 /* vqdmlsl */, ARM::VQDMLSLv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10674 { 2266 /* vqdmlsl */, ARM::VQDMLSLslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10675 { 2266 /* vqdmlsl */, ARM::VQDMLSLslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10676 { 2274 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10677 { 2274 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10678 { 2274 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10679 { 2274 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10680 { 2274 /* vqdmulh */, ARM::VQDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10681 { 2274 /* vqdmulh */, ARM::VQDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10682 { 2274 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10683 { 2274 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10684 { 2274 /* vqdmulh */, ARM::VQDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10685 { 2274 /* vqdmulh */, ARM::VQDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10686 { 2274 /* vqdmulh */, ARM::VQDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10687 { 2274 /* vqdmulh */, ARM::VQDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10688 { 2282 /* vqdmull */, ARM::VQDMULLv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10689 { 2282 /* vqdmull */, ARM::VQDMULLv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 10690 { 2282 /* vqdmull */, ARM::VQDMULLslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10691 { 2282 /* vqdmull */, ARM::VQDMULLslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10692 { 2290 /* vqmovn */, ARM::VQMOVNsv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, }, 10693 { 2290 /* vqmovn */, ARM::VQMOVNsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, }, 10694 { 2290 /* vqmovn */, ARM::VQMOVNsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, }, 10695 { 2290 /* vqmovn */, ARM::VQMOVNuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR }, }, 10696 { 2290 /* vqmovn */, ARM::VQMOVNuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR }, }, 10697 { 2290 /* vqmovn */, ARM::VQMOVNuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR }, }, 10698 { 2297 /* vqmovun */, ARM::VQMOVNsuv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR }, }, 10699 { 2297 /* vqmovun */, ARM::VQMOVNsuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, }, 10700 { 2297 /* vqmovun */, ARM::VQMOVNsuv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR }, }, 10701 { 2305 /* vqneg */, ARM::VQNEGv8i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10702 { 2305 /* vqneg */, ARM::VQNEGv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10703 { 2305 /* vqneg */, ARM::VQNEGv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10704 { 2305 /* vqneg */, ARM::VQNEGv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10705 { 2305 /* vqneg */, ARM::VQNEGv16i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10706 { 2305 /* vqneg */, ARM::VQNEGv8i8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10707 { 2311 /* vqrdmlah */, ARM::VQRDMLAHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10708 { 2311 /* vqrdmlah */, ARM::VQRDMLAHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10709 { 2311 /* vqrdmlah */, ARM::VQRDMLAHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10710 { 2311 /* vqrdmlah */, ARM::VQRDMLAHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10711 { 2311 /* vqrdmlah */, ARM::VQRDMLAHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10712 { 2311 /* vqrdmlah */, ARM::VQRDMLAHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10713 { 2311 /* vqrdmlah */, ARM::VQRDMLAHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10714 { 2311 /* vqrdmlah */, ARM::VQRDMLAHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10715 { 2320 /* vqrdmlsh */, ARM::VQRDMLSHv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10716 { 2320 /* vqrdmlsh */, ARM::VQRDMLSHv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10717 { 2320 /* vqrdmlsh */, ARM::VQRDMLSHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10718 { 2320 /* vqrdmlsh */, ARM::VQRDMLSHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10719 { 2320 /* vqrdmlsh */, ARM::VQRDMLSHslv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10720 { 2320 /* vqrdmlsh */, ARM::VQRDMLSHslv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10721 { 2320 /* vqrdmlsh */, ARM::VQRDMLSHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10722 { 2320 /* vqrdmlsh */, ARM::VQRDMLSHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON|Feature_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10723 { 2329 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10724 { 2329 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10725 { 2329 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10726 { 2329 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10727 { 2329 /* vqrdmulh */, ARM::VQRDMULHv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10728 { 2329 /* vqrdmulh */, ARM::VQRDMULHv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10729 { 2329 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10730 { 2329 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10731 { 2329 /* vqrdmulh */, ARM::VQRDMULHslv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10732 { 2329 /* vqrdmulh */, ARM::VQRDMULHslv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex161_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR_8, MCK_VectorIndex16 }, }, 10733 { 2329 /* vqrdmulh */, ARM::VQRDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10734 { 2329 /* vqrdmulh */, ARM::VQRDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 10735 { 2338 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10736 { 2338 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10737 { 2338 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10738 { 2338 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10739 { 2338 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 10740 { 2338 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 10741 { 2338 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10742 { 2338 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10743 { 2338 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 10744 { 2338 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10745 { 2338 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10746 { 2338 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10747 { 2338 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 10748 { 2338 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 10749 { 2338 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 10750 { 2338 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10751 { 2338 /* vqrshl */, ARM::VQRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10752 { 2338 /* vqrshl */, ARM::VQRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10753 { 2338 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10754 { 2338 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10755 { 2338 /* vqrshl */, ARM::VQRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10756 { 2338 /* vqrshl */, ARM::VQRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10757 { 2338 /* vqrshl */, ARM::VQRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10758 { 2338 /* vqrshl */, ARM::VQRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10759 { 2338 /* vqrshl */, ARM::VQRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10760 { 2338 /* vqrshl */, ARM::VQRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10761 { 2338 /* vqrshl */, ARM::VQRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10762 { 2338 /* vqrshl */, ARM::VQRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10763 { 2338 /* vqrshl */, ARM::VQRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10764 { 2338 /* vqrshl */, ARM::VQRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10765 { 2338 /* vqrshl */, ARM::VQRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10766 { 2338 /* vqrshl */, ARM::VQRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10767 { 2345 /* vqrshrn */, ARM::VQRSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 10768 { 2345 /* vqrshrn */, ARM::VQRSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 10769 { 2345 /* vqrshrn */, ARM::VQRSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 10770 { 2345 /* vqrshrn */, ARM::VQRSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 10771 { 2345 /* vqrshrn */, ARM::VQRSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 10772 { 2345 /* vqrshrn */, ARM::VQRSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 10773 { 2353 /* vqrshrun */, ARM::VQRSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 10774 { 2353 /* vqrshrun */, ARM::VQRSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 10775 { 2353 /* vqrshrun */, ARM::VQRSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 10776 { 2362 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10777 { 2362 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, }, 10778 { 2362 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10779 { 2362 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, }, 10780 { 2362 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10781 { 2362 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, }, 10782 { 2362 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10783 { 2362 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, }, 10784 { 2362 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 10785 { 2362 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, }, 10786 { 2362 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 10787 { 2362 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, }, 10788 { 2362 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10789 { 2362 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, }, 10790 { 2362 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10791 { 2362 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, }, 10792 { 2362 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 10793 { 2362 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_Imm }, }, 10794 { 2362 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10795 { 2362 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_Imm }, }, 10796 { 2362 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10797 { 2362 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_Imm }, }, 10798 { 2362 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10799 { 2362 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_Imm }, }, 10800 { 2362 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 10801 { 2362 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_Imm }, }, 10802 { 2362 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 10803 { 2362 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_Imm }, }, 10804 { 2362 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 10805 { 2362 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_Imm }, }, 10806 { 2362 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10807 { 2362 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_Imm }, }, 10808 { 2362 /* vqshl */, ARM::VQSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10809 { 2362 /* vqshl */, ARM::VQSHLsiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10810 { 2362 /* vqshl */, ARM::VQSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10811 { 2362 /* vqshl */, ARM::VQSHLsiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10812 { 2362 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10813 { 2362 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10814 { 2362 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10815 { 2362 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10816 { 2362 /* vqshl */, ARM::VQSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10817 { 2362 /* vqshl */, ARM::VQSHLsiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10818 { 2362 /* vqshl */, ARM::VQSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10819 { 2362 /* vqshl */, ARM::VQSHLsiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10820 { 2362 /* vqshl */, ARM::VQSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10821 { 2362 /* vqshl */, ARM::VQSHLsiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10822 { 2362 /* vqshl */, ARM::VQSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10823 { 2362 /* vqshl */, ARM::VQSHLsiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10824 { 2362 /* vqshl */, ARM::VQSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10825 { 2362 /* vqshl */, ARM::VQSHLuiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10826 { 2362 /* vqshl */, ARM::VQSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10827 { 2362 /* vqshl */, ARM::VQSHLuiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10828 { 2362 /* vqshl */, ARM::VQSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10829 { 2362 /* vqshl */, ARM::VQSHLuiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10830 { 2362 /* vqshl */, ARM::VQSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10831 { 2362 /* vqshl */, ARM::VQSHLuiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10832 { 2362 /* vqshl */, ARM::VQSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10833 { 2362 /* vqshl */, ARM::VQSHLuiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10834 { 2362 /* vqshl */, ARM::VQSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10835 { 2362 /* vqshl */, ARM::VQSHLuiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10836 { 2362 /* vqshl */, ARM::VQSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10837 { 2362 /* vqshl */, ARM::VQSHLuiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10838 { 2362 /* vqshl */, ARM::VQSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10839 { 2362 /* vqshl */, ARM::VQSHLuiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10840 { 2368 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_Imm }, }, 10841 { 2368 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_Imm }, }, 10842 { 2368 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, }, 10843 { 2368 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, }, 10844 { 2368 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_Imm }, }, 10845 { 2368 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_Imm }, }, 10846 { 2368 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_Imm }, }, 10847 { 2368 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_Imm }, }, 10848 { 2368 /* vqshlu */, ARM::VQSHLsuv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10849 { 2368 /* vqshlu */, ARM::VQSHLsuv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10850 { 2368 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10851 { 2368 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10852 { 2368 /* vqshlu */, ARM::VQSHLsuv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10853 { 2368 /* vqshlu */, ARM::VQSHLsuv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10854 { 2368 /* vqshlu */, ARM::VQSHLsuv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 10855 { 2368 /* vqshlu */, ARM::VQSHLsuv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 10856 { 2375 /* vqshrn */, ARM::VQSHRNsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 10857 { 2375 /* vqshrn */, ARM::VQSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 10858 { 2375 /* vqshrn */, ARM::VQSHRNsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 10859 { 2375 /* vqshrn */, ARM::VQSHRNuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 10860 { 2375 /* vqshrn */, ARM::VQSHRNuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 10861 { 2375 /* vqshrn */, ARM::VQSHRNuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 10862 { 2382 /* vqshrun */, ARM::VQSHRUNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 10863 { 2382 /* vqshrun */, ARM::VQSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 10864 { 2382 /* vqshrun */, ARM::VQSHRUNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 10865 { 2390 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10866 { 2390 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10867 { 2390 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10868 { 2390 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10869 { 2390 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 10870 { 2390 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 10871 { 2390 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10872 { 2390 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10873 { 2390 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 10874 { 2390 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10875 { 2390 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10876 { 2390 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10877 { 2390 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 10878 { 2390 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 10879 { 2390 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 10880 { 2390 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10881 { 2390 /* vqsub */, ARM::VQSUBsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10882 { 2390 /* vqsub */, ARM::VQSUBsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10883 { 2390 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10884 { 2390 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10885 { 2390 /* vqsub */, ARM::VQSUBsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10886 { 2390 /* vqsub */, ARM::VQSUBsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10887 { 2390 /* vqsub */, ARM::VQSUBsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10888 { 2390 /* vqsub */, ARM::VQSUBsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10889 { 2390 /* vqsub */, ARM::VQSUBuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10890 { 2390 /* vqsub */, ARM::VQSUBuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10891 { 2390 /* vqsub */, ARM::VQSUBuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10892 { 2390 /* vqsub */, ARM::VQSUBuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10893 { 2390 /* vqsub */, ARM::VQSUBuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10894 { 2390 /* vqsub */, ARM::VQSUBuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10895 { 2390 /* vqsub */, ARM::VQSUBuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10896 { 2390 /* vqsub */, ARM::VQSUBuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10897 { 2396 /* vraddhn */, ARM::VRADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 10898 { 2396 /* vraddhn */, ARM::VRADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 10899 { 2396 /* vraddhn */, ARM::VRADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 10900 { 2404 /* vrecpe */, ARM::VRECPEq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10901 { 2404 /* vrecpe */, ARM::VRECPEd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10902 { 2404 /* vrecpe */, ARM::VRECPEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10903 { 2404 /* vrecpe */, ARM::VRECPEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10904 { 2404 /* vrecpe */, ARM::VRECPEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10905 { 2404 /* vrecpe */, ARM::VRECPEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10906 { 2411 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10907 { 2411 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10908 { 2411 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10909 { 2411 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10910 { 2411 /* vrecps */, ARM::VRECPSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10911 { 2411 /* vrecps */, ARM::VRECPSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10912 { 2411 /* vrecps */, ARM::VRECPShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10913 { 2411 /* vrecps */, ARM::VRECPShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10914 { 2418 /* vrev16 */, ARM::VREV16q8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10915 { 2418 /* vrev16 */, ARM::VREV16d8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 10916 { 2425 /* vrev32 */, ARM::VREV32q16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 10917 { 2425 /* vrev32 */, ARM::VREV32d16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 10918 { 2425 /* vrev32 */, ARM::VREV32q8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10919 { 2425 /* vrev32 */, ARM::VREV32d8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 10920 { 2432 /* vrev64 */, ARM::VREV64q16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 10921 { 2432 /* vrev64 */, ARM::VREV64d16, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 10922 { 2432 /* vrev64 */, ARM::VREV64q32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 10923 { 2432 /* vrev64 */, ARM::VREV64d32, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 10924 { 2432 /* vrev64 */, ARM::VREV64q8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 10925 { 2432 /* vrev64 */, ARM::VREV64d8, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 10926 { 2439 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 10927 { 2439 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 10928 { 2439 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 10929 { 2439 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 10930 { 2439 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 10931 { 2439 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 10932 { 2439 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 10933 { 2439 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 10934 { 2439 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 10935 { 2439 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 10936 { 2439 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 10937 { 2439 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 10938 { 2439 /* vrhadd */, ARM::VRHADDsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10939 { 2439 /* vrhadd */, ARM::VRHADDsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10940 { 2439 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10941 { 2439 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10942 { 2439 /* vrhadd */, ARM::VRHADDsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10943 { 2439 /* vrhadd */, ARM::VRHADDsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10944 { 2439 /* vrhadd */, ARM::VRHADDuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10945 { 2439 /* vrhadd */, ARM::VRHADDuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10946 { 2439 /* vrhadd */, ARM::VRHADDuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10947 { 2439 /* vrhadd */, ARM::VRHADDuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10948 { 2439 /* vrhadd */, ARM::VRHADDuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 10949 { 2439 /* vrhadd */, ARM::VRHADDuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 10950 { 2446 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10951 { 2446 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10952 { 2446 /* vrinta */, ARM::VRINTAS, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10953 { 2446 /* vrinta */, ARM::VRINTAD, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10954 { 2446 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10955 { 2446 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10956 { 2446 /* vrinta */, ARM::VRINTAH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 10957 { 2446 /* vrinta */, ARM::VRINTANQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10958 { 2446 /* vrinta */, ARM::VRINTANDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10959 { 2446 /* vrinta */, ARM::VRINTAS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10960 { 2446 /* vrinta */, ARM::VRINTAD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10961 { 2446 /* vrinta */, ARM::VRINTANQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10962 { 2446 /* vrinta */, ARM::VRINTANDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10963 { 2453 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10964 { 2453 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10965 { 2453 /* vrintm */, ARM::VRINTMS, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10966 { 2453 /* vrintm */, ARM::VRINTMD, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10967 { 2453 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10968 { 2453 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10969 { 2453 /* vrintm */, ARM::VRINTMH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 10970 { 2453 /* vrintm */, ARM::VRINTMNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10971 { 2453 /* vrintm */, ARM::VRINTMNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10972 { 2453 /* vrintm */, ARM::VRINTMS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10973 { 2453 /* vrintm */, ARM::VRINTMD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10974 { 2453 /* vrintm */, ARM::VRINTMNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10975 { 2453 /* vrintm */, ARM::VRINTMNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10976 { 2460 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10977 { 2460 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10978 { 2460 /* vrintn */, ARM::VRINTNS, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10979 { 2460 /* vrintn */, ARM::VRINTND, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10980 { 2460 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10981 { 2460 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10982 { 2460 /* vrintn */, ARM::VRINTNH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 10983 { 2460 /* vrintn */, ARM::VRINTNNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10984 { 2460 /* vrintn */, ARM::VRINTNNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10985 { 2460 /* vrintn */, ARM::VRINTNS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10986 { 2460 /* vrintn */, ARM::VRINTND, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10987 { 2460 /* vrintn */, ARM::VRINTNNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10988 { 2460 /* vrintn */, ARM::VRINTNNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10989 { 2467 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10990 { 2467 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10991 { 2467 /* vrintp */, ARM::VRINTPS, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10992 { 2467 /* vrintp */, ARM::VRINTPD, Convert__Reg1_1__Reg1_2, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 10993 { 2467 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 10994 { 2467 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 10995 { 2467 /* vrintp */, ARM::VRINTPH, Convert__Reg1_1__Reg1_2, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 10996 { 2467 /* vrintp */, ARM::VRINTPNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 10997 { 2467 /* vrintp */, ARM::VRINTPNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 10998 { 2467 /* vrintp */, ARM::VRINTPS, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 10999 { 2467 /* vrintp */, ARM::VRINTPD, Convert__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11000 { 2467 /* vrintp */, ARM::VRINTPNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11001 { 2467 /* vrintp */, ARM::VRINTPNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11002 { 2474 /* vrintr */, ARM::VRINTRS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11003 { 2474 /* vrintr */, ARM::VRINTRD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11004 { 2474 /* vrintr */, ARM::VRINTRH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11005 { 2474 /* vrintr */, ARM::VRINTRS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11006 { 2474 /* vrintr */, ARM::VRINTRD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11007 { 2474 /* vrintr */, ARM::VRINTRH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11008 { 2481 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11009 { 2481 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11010 { 2481 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11011 { 2481 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11012 { 2481 /* vrintx */, ARM::VRINTXNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11013 { 2481 /* vrintx */, ARM::VRINTXNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11014 { 2481 /* vrintx */, ARM::VRINTXNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11015 { 2481 /* vrintx */, ARM::VRINTXNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11016 { 2481 /* vrintx */, ARM::VRINTXS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11017 { 2481 /* vrintx */, ARM::VRINTXD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11018 { 2481 /* vrintx */, ARM::VRINTXH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11019 { 2481 /* vrintx */, ARM::VRINTXS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11020 { 2481 /* vrintx */, ARM::VRINTXD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11021 { 2481 /* vrintx */, ARM::VRINTXH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11022 { 2488 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11023 { 2488 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON, { MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11024 { 2488 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11025 { 2488 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_1__Reg1_2, Feature_HasV8|Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11026 { 2488 /* vrintz */, ARM::VRINTZNQf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11027 { 2488 /* vrintz */, ARM::VRINTZNDf, Convert__Reg1_2__Reg1_3, Feature_HasNEON, { MCK__DOT_f32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11028 { 2488 /* vrintz */, ARM::VRINTZNQh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11029 { 2488 /* vrintz */, ARM::VRINTZNDh, Convert__Reg1_2__Reg1_3, Feature_HasNEON|Feature_HasFullFP16, { MCK__DOT_f16, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11030 { 2488 /* vrintz */, ARM::VRINTZS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11031 { 2488 /* vrintz */, ARM::VRINTZD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11032 { 2488 /* vrintz */, ARM::VRINTZH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11033 { 2488 /* vrintz */, ARM::VRINTZS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11034 { 2488 /* vrintz */, ARM::VRINTZD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11035 { 2488 /* vrintz */, ARM::VRINTZH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11036 { 2495 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 11037 { 2495 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 11038 { 2495 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 11039 { 2495 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 11040 { 2495 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 11041 { 2495 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 11042 { 2495 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 11043 { 2495 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 11044 { 2495 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 11045 { 2495 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 11046 { 2495 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 11047 { 2495 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 11048 { 2495 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 11049 { 2495 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 11050 { 2495 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 11051 { 2495 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 11052 { 2495 /* vrshl */, ARM::VRSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11053 { 2495 /* vrshl */, ARM::VRSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11054 { 2495 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11055 { 2495 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11056 { 2495 /* vrshl */, ARM::VRSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11057 { 2495 /* vrshl */, ARM::VRSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11058 { 2495 /* vrshl */, ARM::VRSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11059 { 2495 /* vrshl */, ARM::VRSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11060 { 2495 /* vrshl */, ARM::VRSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11061 { 2495 /* vrshl */, ARM::VRSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11062 { 2495 /* vrshl */, ARM::VRSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11063 { 2495 /* vrshl */, ARM::VRSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11064 { 2495 /* vrshl */, ARM::VRSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11065 { 2495 /* vrshl */, ARM::VRSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11066 { 2495 /* vrshl */, ARM::VRSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11067 { 2495 /* vrshl */, ARM::VRSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11068 { 2501 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 11069 { 2501 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 11070 { 2501 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 11071 { 2501 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 11072 { 2501 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 11073 { 2501 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 11074 { 2501 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 11075 { 2501 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 11076 { 2501 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 11077 { 2501 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 11078 { 2501 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 11079 { 2501 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 11080 { 2501 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 11081 { 2501 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 11082 { 2501 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 11083 { 2501 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 11084 { 2501 /* vrshr */, ARM::VRSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 11085 { 2501 /* vrshr */, ARM::VRSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 11086 { 2501 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 11087 { 2501 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 11088 { 2501 /* vrshr */, ARM::VRSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 11089 { 2501 /* vrshr */, ARM::VRSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 11090 { 2501 /* vrshr */, ARM::VRSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 11091 { 2501 /* vrshr */, ARM::VRSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 11092 { 2501 /* vrshr */, ARM::VRSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 11093 { 2501 /* vrshr */, ARM::VRSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 11094 { 2501 /* vrshr */, ARM::VRSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 11095 { 2501 /* vrshr */, ARM::VRSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 11096 { 2501 /* vrshr */, ARM::VRSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 11097 { 2501 /* vrshr */, ARM::VRSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 11098 { 2501 /* vrshr */, ARM::VRSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 11099 { 2501 /* vrshr */, ARM::VRSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 11100 { 2507 /* vrshrn */, ARM::VRSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 11101 { 2507 /* vrshrn */, ARM::VRSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 11102 { 2507 /* vrshrn */, ARM::VRSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 11103 { 2514 /* vrsqrte */, ARM::VRSQRTEq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 11104 { 2514 /* vrsqrte */, ARM::VRSQRTEd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 11105 { 2514 /* vrsqrte */, ARM::VRSQRTEfq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11106 { 2514 /* vrsqrte */, ARM::VRSQRTEfd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11107 { 2514 /* vrsqrte */, ARM::VRSQRTEhq, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11108 { 2514 /* vrsqrte */, ARM::VRSQRTEhd, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11109 { 2522 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11110 { 2522 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11111 { 2522 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11112 { 2522 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11113 { 2522 /* vrsqrts */, ARM::VRSQRTSfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11114 { 2522 /* vrsqrts */, ARM::VRSQRTSfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11115 { 2522 /* vrsqrts */, ARM::VRSQRTShq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11116 { 2522 /* vrsqrts */, ARM::VRSQRTShd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11117 { 2530 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 11118 { 2530 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 11119 { 2530 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 11120 { 2530 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 11121 { 2530 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 11122 { 2530 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 11123 { 2530 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 11124 { 2530 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 11125 { 2530 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 11126 { 2530 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 11127 { 2530 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 11128 { 2530 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 11129 { 2530 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 11130 { 2530 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 11131 { 2530 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 11132 { 2530 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 11133 { 2530 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 11134 { 2530 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 11135 { 2530 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 11136 { 2530 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 11137 { 2530 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 11138 { 2530 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 11139 { 2530 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 11140 { 2530 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 11141 { 2530 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 11142 { 2530 /* vrsra */, ARM::VRSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 11143 { 2530 /* vrsra */, ARM::VRSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 11144 { 2530 /* vrsra */, ARM::VRSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 11145 { 2530 /* vrsra */, ARM::VRSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 11146 { 2530 /* vrsra */, ARM::VRSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 11147 { 2530 /* vrsra */, ARM::VRSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 11148 { 2530 /* vrsra */, ARM::VRSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 11149 { 2536 /* vrsubhn */, ARM::VRSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 11150 { 2536 /* vrsubhn */, ARM::VRSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 11151 { 2536 /* vrsubhn */, ARM::VRSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 11152 { 2544 /* vsdot */, ARM::VSDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, Feature_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11153 { 2544 /* vsdot */, ARM::VSDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, Feature_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11154 { 2544 /* vsdot */, ARM::VSDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasDotProd, { MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 11155 { 2544 /* vsdot */, ARM::VSDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasDotProd, { MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 11156 { 2550 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11157 { 2550 /* vseleq */, ARM::VSELEQD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11158 { 2550 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11159 { 2557 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11160 { 2557 /* vselge */, ARM::VSELGED, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11161 { 2557 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11162 { 2564 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11163 { 2564 /* vselgt */, ARM::VSELGTD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11164 { 2564 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11165 { 2571 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11166 { 2571 /* vselvs */, ARM::VSELVSD, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFPARMv8|Feature_HasDPVFP, { MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11167 { 2571 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, Feature_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11168 { 2578 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR }, }, 11169 { 2578 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR }, }, 11170 { 2578 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, }, 11171 { 2578 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, }, 11172 { 2578 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR }, }, 11173 { 2578 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR }, }, 11174 { 2578 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR }, }, 11175 { 2578 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR }, }, 11176 { 2578 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR }, }, 11177 { 2578 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR }, }, 11178 { 2578 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR }, }, 11179 { 2578 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR }, }, 11180 { 2578 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR }, }, 11181 { 2578 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR }, }, 11182 { 2578 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR }, }, 11183 { 2578 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR }, }, 11184 { 2578 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_Imm }, }, 11185 { 2578 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_Imm }, }, 11186 { 2578 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_Imm }, }, 11187 { 2578 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_Imm }, }, 11188 { 2578 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_Imm }, }, 11189 { 2578 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_Imm }, }, 11190 { 2578 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_Imm }, }, 11191 { 2578 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_Imm }, }, 11192 { 2578 /* vshl */, ARM::VSHLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11193 { 2578 /* vshl */, ARM::VSHLsv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11194 { 2578 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11195 { 2578 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11196 { 2578 /* vshl */, ARM::VSHLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11197 { 2578 /* vshl */, ARM::VSHLsv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11198 { 2578 /* vshl */, ARM::VSHLsv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11199 { 2578 /* vshl */, ARM::VSHLsv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11200 { 2578 /* vshl */, ARM::VSHLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11201 { 2578 /* vshl */, ARM::VSHLuv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11202 { 2578 /* vshl */, ARM::VSHLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11203 { 2578 /* vshl */, ARM::VSHLuv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11204 { 2578 /* vshl */, ARM::VSHLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11205 { 2578 /* vshl */, ARM::VSHLuv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11206 { 2578 /* vshl */, ARM::VSHLuv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11207 { 2578 /* vshl */, ARM::VSHLuv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11208 { 2578 /* vshl */, ARM::VSHLiv8i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 11209 { 2578 /* vshl */, ARM::VSHLiv4i16, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 11210 { 2578 /* vshl */, ARM::VSHLiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 11211 { 2578 /* vshl */, ARM::VSHLiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 11212 { 2578 /* vshl */, ARM::VSHLiv2i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 11213 { 2578 /* vshl */, ARM::VSHLiv1i64, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 11214 { 2578 /* vshl */, ARM::VSHLiv16i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 11215 { 2578 /* vshl */, ARM::VSHLiv8i8, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 11216 { 2583 /* vshll */, ARM::VSHLLsv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, }, 11217 { 2583 /* vshll */, ARM::VSHLLsv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, }, 11218 { 2583 /* vshll */, ARM::VSHLLsv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, }, 11219 { 2583 /* vshll */, ARM::VSHLLuv4i32, Convert__Reg1_2__Reg1_3__Imm1_151_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_Imm1_15 }, }, 11220 { 2583 /* vshll */, ARM::VSHLLuv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, }, 11221 { 2583 /* vshll */, ARM::VSHLLuv8i16, Convert__Reg1_2__Reg1_3__Imm1_71_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_Imm1_7 }, }, 11222 { 2583 /* vshll */, ARM::VSHLLi16, Convert__Reg1_2__Reg1_3__Imm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_DPR, MCK_Imm16 }, }, 11223 { 2583 /* vshll */, ARM::VSHLLi32, Convert__Reg1_2__Reg1_3__Imm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_DPR, MCK_Imm32 }, }, 11224 { 2583 /* vshll */, ARM::VSHLLi8, Convert__Reg1_2__Reg1_3__Imm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_DPR, MCK_Imm8 }, }, 11225 { 2589 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 11226 { 2589 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 11227 { 2589 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 11228 { 2589 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 11229 { 2589 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 11230 { 2589 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 11231 { 2589 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 11232 { 2589 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 11233 { 2589 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 11234 { 2589 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 11235 { 2589 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 11236 { 2589 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 11237 { 2589 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 11238 { 2589 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 11239 { 2589 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 11240 { 2589 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 11241 { 2589 /* vshr */, ARM::VSHRsv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 11242 { 2589 /* vshr */, ARM::VSHRsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 11243 { 2589 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 11244 { 2589 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 11245 { 2589 /* vshr */, ARM::VSHRsv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 11246 { 2589 /* vshr */, ARM::VSHRsv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 11247 { 2589 /* vshr */, ARM::VSHRsv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 11248 { 2589 /* vshr */, ARM::VSHRsv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 11249 { 2589 /* vshr */, ARM::VSHRuv8i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 11250 { 2589 /* vshr */, ARM::VSHRuv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 11251 { 2589 /* vshr */, ARM::VSHRuv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 11252 { 2589 /* vshr */, ARM::VSHRuv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 11253 { 2589 /* vshr */, ARM::VSHRuv2i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 11254 { 2589 /* vshr */, ARM::VSHRuv1i64, Convert__Reg1_2__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 11255 { 2589 /* vshr */, ARM::VSHRuv16i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 11256 { 2589 /* vshr */, ARM::VSHRuv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 11257 { 2594 /* vshrn */, ARM::VSHRNv8i8, Convert__Reg1_2__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_ShrImm8 }, }, 11258 { 2594 /* vshrn */, ARM::VSHRNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, }, 11259 { 2594 /* vshrn */, ARM::VSHRNv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_ShrImm32 }, }, 11260 { 2600 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_Imm }, }, 11261 { 2600 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_Imm }, }, 11262 { 2600 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_Imm }, }, 11263 { 2600 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_Imm }, }, 11264 { 2600 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_Imm }, }, 11265 { 2600 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_Imm }, }, 11266 { 2600 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_Imm }, }, 11267 { 2600 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__Imm1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_Imm }, }, 11268 { 2600 /* vsli */, ARM::VSLIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_Imm }, }, 11269 { 2600 /* vsli */, ARM::VSLIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_Imm }, }, 11270 { 2600 /* vsli */, ARM::VSLIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_Imm }, }, 11271 { 2600 /* vsli */, ARM::VSLIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_Imm }, }, 11272 { 2600 /* vsli */, ARM::VSLIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_Imm }, }, 11273 { 2600 /* vsli */, ARM::VSLIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_Imm }, }, 11274 { 2600 /* vsli */, ARM::VSLIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_Imm }, }, 11275 { 2600 /* vsli */, ARM::VSLIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__Imm1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_Imm }, }, 11276 { 2605 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 11277 { 2605 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_1__Reg1_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, }, 11278 { 2605 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11279 { 2605 /* vsqrt */, ARM::VSQRTD, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11280 { 2605 /* vsqrt */, ARM::VSQRTH, Convert__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11281 { 2611 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_ShrImm16 }, }, 11282 { 2611 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_ShrImm16 }, }, 11283 { 2611 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, }, 11284 { 2611 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, }, 11285 { 2611 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_ShrImm64 }, }, 11286 { 2611 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_ShrImm64 }, }, 11287 { 2611 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_ShrImm8 }, }, 11288 { 2611 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_ShrImm8 }, }, 11289 { 2611 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_ShrImm16 }, }, 11290 { 2611 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_ShrImm16 }, }, 11291 { 2611 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_ShrImm32 }, }, 11292 { 2611 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_ShrImm32 }, }, 11293 { 2611 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_ShrImm64 }, }, 11294 { 2611 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_ShrImm64 }, }, 11295 { 2611 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_ShrImm8 }, }, 11296 { 2611 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_ShrImm8 }, }, 11297 { 2611 /* vsra */, ARM::VSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 11298 { 2611 /* vsra */, ARM::VSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 11299 { 2611 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 11300 { 2611 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 11301 { 2611 /* vsra */, ARM::VSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 11302 { 2611 /* vsra */, ARM::VSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 11303 { 2611 /* vsra */, ARM::VSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 11304 { 2611 /* vsra */, ARM::VSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 11305 { 2611 /* vsra */, ARM::VSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 11306 { 2611 /* vsra */, ARM::VSRAuv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 11307 { 2611 /* vsra */, ARM::VSRAuv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 11308 { 2611 /* vsra */, ARM::VSRAuv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 11309 { 2611 /* vsra */, ARM::VSRAuv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 11310 { 2611 /* vsra */, ARM::VSRAuv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 11311 { 2611 /* vsra */, ARM::VSRAuv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 11312 { 2611 /* vsra */, ARM::VSRAuv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 11313 { 2616 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_ShrImm16 }, }, 11314 { 2616 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_ShrImm16 }, }, 11315 { 2616 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_ShrImm32 }, }, 11316 { 2616 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_ShrImm32 }, }, 11317 { 2616 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_ShrImm64 }, }, 11318 { 2616 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_ShrImm64 }, }, 11319 { 2616 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_ShrImm8 }, }, 11320 { 2616 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_ShrImm8 }, }, 11321 { 2616 /* vsri */, ARM::VSRIv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_ShrImm16 }, }, 11322 { 2616 /* vsri */, ARM::VSRIv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_ShrImm16 }, }, 11323 { 2616 /* vsri */, ARM::VSRIv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, }, 11324 { 2616 /* vsri */, ARM::VSRIv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, }, 11325 { 2616 /* vsri */, ARM::VSRIv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_ShrImm64 }, }, 11326 { 2616 /* vsri */, ARM::VSRIv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm641_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_ShrImm64 }, }, 11327 { 2616 /* vsri */, ARM::VSRIv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_ShrImm8 }, }, 11328 { 2616 /* vsri */, ARM::VSRIv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm81_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_ShrImm8 }, }, 11329 { 2621 /* vst1 */, ARM::VST1q16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 11330 { 2621 /* vst1 */, ARM::VST1d16Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11331 { 2621 /* vst1 */, ARM::VST1d16, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 11332 { 2621 /* vst1 */, ARM::VST1LNdAsm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16 }, }, 11333 { 2621 /* vst1 */, ARM::VST1d16T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 11334 { 2621 /* vst1 */, ARM::VST1q32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 11335 { 2621 /* vst1 */, ARM::VST1d32Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11336 { 2621 /* vst1 */, ARM::VST1d32, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 11337 { 2621 /* vst1 */, ARM::VST1LNdAsm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32 }, }, 11338 { 2621 /* vst1 */, ARM::VST1d32T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 11339 { 2621 /* vst1 */, ARM::VST1q64, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 11340 { 2621 /* vst1 */, ARM::VST1d64Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11341 { 2621 /* vst1 */, ARM::VST1d64, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 11342 { 2621 /* vst1 */, ARM::VST1d64T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 11343 { 2621 /* vst1 */, ARM::VST1q8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 11344 { 2621 /* vst1 */, ARM::VST1d8Q, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11345 { 2621 /* vst1 */, ARM::VST1d8, Convert__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64 }, }, 11346 { 2621 /* vst1 */, ARM::VST1LNdAsm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone }, }, 11347 { 2621 /* vst1 */, ARM::VST1d8T, Convert__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 11348 { 2621 /* vst1 */, ARM::VST1q16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11349 { 2621 /* vst1 */, ARM::VST1q16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11350 { 2621 /* vst1 */, ARM::VST1d16Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11351 { 2621 /* vst1 */, ARM::VST1d16Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11352 { 2621 /* vst1 */, ARM::VST1d16wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11353 { 2621 /* vst1 */, ARM::VST1d16wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 11354 { 2621 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 11355 { 2621 /* vst1 */, ARM::VST1LNdWB_register_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 11356 { 2621 /* vst1 */, ARM::VST1d16Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11357 { 2621 /* vst1 */, ARM::VST1d16Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 11358 { 2621 /* vst1 */, ARM::VST1q32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11359 { 2621 /* vst1 */, ARM::VST1q32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11360 { 2621 /* vst1 */, ARM::VST1d32Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11361 { 2621 /* vst1 */, ARM::VST1d32Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11362 { 2621 /* vst1 */, ARM::VST1d32wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11363 { 2621 /* vst1 */, ARM::VST1d32wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 11364 { 2621 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 11365 { 2621 /* vst1 */, ARM::VST1LNdWB_register_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 11366 { 2621 /* vst1 */, ARM::VST1d32Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11367 { 2621 /* vst1 */, ARM::VST1d32Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 11368 { 2621 /* vst1 */, ARM::VST1q64wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11369 { 2621 /* vst1 */, ARM::VST1q64wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11370 { 2621 /* vst1 */, ARM::VST1d64Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11371 { 2621 /* vst1 */, ARM::VST1d64Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11372 { 2621 /* vst1 */, ARM::VST1d64wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11373 { 2621 /* vst1 */, ARM::VST1d64wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 11374 { 2621 /* vst1 */, ARM::VST1d64Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11375 { 2621 /* vst1 */, ARM::VST1d64Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 11376 { 2621 /* vst1 */, ARM::VST1q8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11377 { 2621 /* vst1 */, ARM::VST1q8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11378 { 2621 /* vst1 */, ARM::VST1d8Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11379 { 2621 /* vst1 */, ARM::VST1d8Qwb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11380 { 2621 /* vst1 */, ARM::VST1d8wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11381 { 2621 /* vst1 */, ARM::VST1d8wb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListOneD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK_rGPR }, }, 11382 { 2621 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 11383 { 2621 /* vst1 */, ARM::VST1LNdWB_register_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 11384 { 2621 /* vst1 */, ARM::VST1d8Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11385 { 2621 /* vst1 */, ARM::VST1d8Twb_register, Convert__imm_95_0__AlignedMemory642_3__Reg1_4__VecListThreeD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 11386 { 2621 /* vst1 */, ARM::VST1LNd16, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 11387 { 2621 /* vst1 */, ARM::VST1LNd8, Convert__AlignedMemory2_8__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory }, }, 11388 { 2621 /* vst1 */, ARM::VST1LNd16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11389 { 2621 /* vst1 */, ARM::VST1LNd32, Convert__Reg1_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, }, 11390 { 2621 /* vst1 */, ARM::VST1LNd8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11391 { 2621 /* vst1 */, ARM::VST1LNd32_UPD, Convert__imm_95_0__Reg1_8__Imm1_9__Imm1_10__Reg1_3__Imm1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm, MCK_Imm }, }, 11392 { 2626 /* vst2 */, ARM::VST2d16, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 11393 { 2626 /* vst2 */, ARM::VST2b16, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 11394 { 2626 /* vst2 */, ARM::VST2q16, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11395 { 2626 /* vst2 */, ARM::VST2LNdAsm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32 }, }, 11396 { 2626 /* vst2 */, ARM::VST2LNqAsm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32 }, }, 11397 { 2626 /* vst2 */, ARM::VST2d32, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 11398 { 2626 /* vst2 */, ARM::VST2b32, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 11399 { 2626 /* vst2 */, ARM::VST2q32, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11400 { 2626 /* vst2 */, ARM::VST2LNdAsm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64 }, }, 11401 { 2626 /* vst2 */, ARM::VST2LNqAsm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64 }, }, 11402 { 2626 /* vst2 */, ARM::VST2d8, Convert__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128 }, }, 11403 { 2626 /* vst2 */, ARM::VST2b8, Convert__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128 }, }, 11404 { 2626 /* vst2 */, ARM::VST2q8, Convert__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11405 { 2626 /* vst2 */, ARM::VST2LNdAsm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16 }, }, 11406 { 2626 /* vst2 */, ARM::VST2d16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11407 { 2626 /* vst2 */, ARM::VST2d16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11408 { 2626 /* vst2 */, ARM::VST2b16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11409 { 2626 /* vst2 */, ARM::VST2b16wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11410 { 2626 /* vst2 */, ARM::VST2q16wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11411 { 2626 /* vst2 */, ARM::VST2q16wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11412 { 2626 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 11413 { 2626 /* vst2 */, ARM::VST2LNdWB_register_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 11414 { 2626 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 11415 { 2626 /* vst2 */, ARM::VST2LNqWB_register_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 11416 { 2626 /* vst2 */, ARM::VST2d32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11417 { 2626 /* vst2 */, ARM::VST2d32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11418 { 2626 /* vst2 */, ARM::VST2b32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11419 { 2626 /* vst2 */, ARM::VST2b32wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11420 { 2626 /* vst2 */, ARM::VST2q32wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11421 { 2626 /* vst2 */, ARM::VST2q32wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11422 { 2626 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11423 { 2626 /* vst2 */, ARM::VST2LNdWB_register_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 11424 { 2626 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11425 { 2626 /* vst2 */, ARM::VST2LNqWB_register_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 11426 { 2626 /* vst2 */, ARM::VST2d8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11427 { 2626 /* vst2 */, ARM::VST2d8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPair1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11428 { 2626 /* vst2 */, ARM::VST2b8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11429 { 2626 /* vst2 */, ARM::VST2b8wb_register, Convert__imm_95_0__AlignedMemory64or1282_3__Reg1_4__VecListDPairSpaced1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11430 { 2626 /* vst2 */, ARM::VST2q8wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11431 { 2626 /* vst2 */, ARM::VST2q8wb_register, Convert__imm_95_0__AlignedMemory64or128or2562_3__Reg1_4__VecListFourD1_2__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11432 { 2626 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, }, 11433 { 2626 /* vst2 */, ARM::VST2LNdWB_register_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK_rGPR }, }, 11434 { 2631 /* vst3 */, ARM::VST3dAsm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 11435 { 2631 /* vst3 */, ARM::VST3LNdAsm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone }, }, 11436 { 2631 /* vst3 */, ARM::VST3qAsm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 11437 { 2631 /* vst3 */, ARM::VST3LNqAsm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone }, }, 11438 { 2631 /* vst3 */, ARM::VST3dAsm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 11439 { 2631 /* vst3 */, ARM::VST3LNdAsm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone }, }, 11440 { 2631 /* vst3 */, ARM::VST3qAsm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 11441 { 2631 /* vst3 */, ARM::VST3LNqAsm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone }, }, 11442 { 2631 /* vst3 */, ARM::VST3dAsm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64 }, }, 11443 { 2631 /* vst3 */, ARM::VST3LNdAsm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone }, }, 11444 { 2631 /* vst3 */, ARM::VST3qAsm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64 }, }, 11445 { 2631 /* vst3 */, ARM::VST3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11446 { 2631 /* vst3 */, ARM::VST3dWB_register_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 11447 { 2631 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 11448 { 2631 /* vst3 */, ARM::VST3LNdWB_register_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 11449 { 2631 /* vst3 */, ARM::VST3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11450 { 2631 /* vst3 */, ARM::VST3qWB_register_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 11451 { 2631 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 11452 { 2631 /* vst3 */, ARM::VST3LNqWB_register_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 11453 { 2631 /* vst3 */, ARM::VST3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11454 { 2631 /* vst3 */, ARM::VST3dWB_register_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 11455 { 2631 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 11456 { 2631 /* vst3 */, ARM::VST3LNdWB_register_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 11457 { 2631 /* vst3 */, ARM::VST3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11458 { 2631 /* vst3 */, ARM::VST3qWB_register_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 11459 { 2631 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 11460 { 2631 /* vst3 */, ARM::VST3LNqWB_register_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 11461 { 2631 /* vst3 */, ARM::VST3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11462 { 2631 /* vst3 */, ARM::VST3dWB_register_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK_rGPR }, }, 11463 { 2631 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, }, 11464 { 2631 /* vst3 */, ARM::VST3LNdWB_register_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK_rGPR }, }, 11465 { 2631 /* vst3 */, ARM::VST3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11466 { 2631 /* vst3 */, ARM::VST3qWB_register_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK_rGPR }, }, 11467 { 2631 /* vst3 */, ARM::VST3d16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11468 { 2631 /* vst3 */, ARM::VST3q16, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11469 { 2631 /* vst3 */, ARM::VST3d32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11470 { 2631 /* vst3 */, ARM::VST3q32, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11471 { 2631 /* vst3 */, ARM::VST3d8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11472 { 2631 /* vst3 */, ARM::VST3q8, Convert__AlignedMemory2_7__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11473 { 2631 /* vst3 */, ARM::VST3d16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11474 { 2631 /* vst3 */, ARM::VST3q16_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11475 { 2631 /* vst3 */, ARM::VST3d32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11476 { 2631 /* vst3 */, ARM::VST3q32_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11477 { 2631 /* vst3 */, ARM::VST3d8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11478 { 2631 /* vst3 */, ARM::VST3q8_UPD, Convert__imm_95_0__AlignedMemory2_7__Imm1_8__Reg1_3__Reg1_4__Reg1_5__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11479 { 2636 /* vst4 */, ARM::VST4dAsm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11480 { 2636 /* vst4 */, ARM::VST4LNdAsm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64 }, }, 11481 { 2636 /* vst4 */, ARM::VST4qAsm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 11482 { 2636 /* vst4 */, ARM::VST4LNqAsm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64 }, }, 11483 { 2636 /* vst4 */, ARM::VST4dAsm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11484 { 2636 /* vst4 */, ARM::VST4LNdAsm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128 }, }, 11485 { 2636 /* vst4 */, ARM::VST4qAsm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 11486 { 2636 /* vst4 */, ARM::VST4LNqAsm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128 }, }, 11487 { 2636 /* vst4 */, ARM::VST4dAsm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256 }, }, 11488 { 2636 /* vst4 */, ARM::VST4LNdAsm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32 }, }, 11489 { 2636 /* vst4 */, ARM::VST4qAsm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256 }, }, 11490 { 2636 /* vst4 */, ARM::VST4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11491 { 2636 /* vst4 */, ARM::VST4dWB_register_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11492 { 2636 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11493 { 2636 /* vst4 */, ARM::VST4LNdWB_register_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 11494 { 2636 /* vst4 */, ARM::VST4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11495 { 2636 /* vst4 */, ARM::VST4qWB_register_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11496 { 2636 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, }, 11497 { 2636 /* vst4 */, ARM::VST4LNqWB_register_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK_rGPR }, }, 11498 { 2636 /* vst4 */, ARM::VST4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11499 { 2636 /* vst4 */, ARM::VST4dWB_register_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11500 { 2636 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11501 { 2636 /* vst4 */, ARM::VST4LNdWB_register_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11502 { 2636 /* vst4 */, ARM::VST4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11503 { 2636 /* vst4 */, ARM::VST4qWB_register_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11504 { 2636 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, }, 11505 { 2636 /* vst4 */, ARM::VST4LNqWB_register_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK_rGPR }, }, 11506 { 2636 /* vst4 */, ARM::VST4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11507 { 2636 /* vst4 */, ARM::VST4dWB_register_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11508 { 2636 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, }, 11509 { 2636 /* vst4 */, ARM::VST4LNdWB_register_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK_rGPR }, }, 11510 { 2636 /* vst4 */, ARM::VST4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, }, 11511 { 2636 /* vst4 */, ARM::VST4qWB_register_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK_rGPR }, }, 11512 { 2636 /* vst4 */, ARM::VST4d16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11513 { 2636 /* vst4 */, ARM::VST4q16, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11514 { 2636 /* vst4 */, ARM::VST4d32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11515 { 2636 /* vst4 */, ARM::VST4q32, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11516 { 2636 /* vst4 */, ARM::VST4d8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11517 { 2636 /* vst4 */, ARM::VST4q8, Convert__AlignedMemory2_8__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory }, }, 11518 { 2636 /* vst4 */, ARM::VST4d16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11519 { 2636 /* vst4 */, ARM::VST4q16_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11520 { 2636 /* vst4 */, ARM::VST4d32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11521 { 2636 /* vst4 */, ARM::VST4q32_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11522 { 2636 /* vst4 */, ARM::VST4d8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11523 { 2636 /* vst4 */, ARM::VST4q8_UPD, Convert__imm_95_0__AlignedMemory2_8__Imm1_9__Reg1_3__Reg1_4__Reg1_5__Reg1_6__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK__123_, MCK_DPR, MCK_DPR, MCK_DPR, MCK_DPR, MCK__125_, MCK_AlignedMemory, MCK_Imm }, }, 11524 { 2641 /* vstmdb */, ARM::VSTMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 11525 { 2641 /* vstmdb */, ARM::VSTMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 11526 { 2648 /* vstmia */, ARM::VSTMDIA, Convert__Reg1_1__CondCode2_0__DPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_DPRRegList }, }, 11527 { 2648 /* vstmia */, ARM::VSTMSIA, Convert__Reg1_1__CondCode2_0__SPRRegList1_2, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK_SPRRegList }, }, 11528 { 2648 /* vstmia */, ARM::VSTMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, }, 11529 { 2648 /* vstmia */, ARM::VSTMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, Feature_HasVFP2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, }, 11530 { 2655 /* vstr */, ARM::VSTRD, Convert__Reg1_1__AddrMode52_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_DPR, MCK_AddrMode5 }, }, 11531 { 2655 /* vstr */, ARM::VSTRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, }, 11532 { 2655 /* vstr */, ARM::VSTRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, }, 11533 { 2655 /* vstr */, ARM::VSTRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, }, 11534 { 2655 /* vstr */, ARM::VSTRD, Convert__Reg1_2__AddrMode52_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_AddrMode5 }, }, 11535 { 2660 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR }, }, 11536 { 2660 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR }, }, 11537 { 2660 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, }, 11538 { 2660 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR }, }, 11539 { 2660 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR }, }, 11540 { 2660 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR }, }, 11541 { 2660 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR }, }, 11542 { 2660 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR }, }, 11543 { 2660 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR }, }, 11544 { 2660 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR }, }, 11545 { 2660 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR }, }, 11546 { 2660 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR }, }, 11547 { 2660 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR }, }, 11548 { 2660 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR }, }, 11549 { 2660 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, }, 11550 { 2660 /* vsub */, ARM::VSUBfq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11551 { 2660 /* vsub */, ARM::VSUBfd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11552 { 2660 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11553 { 2660 /* vsub */, ARM::VSUBD, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11554 { 2660 /* vsub */, ARM::VSUBv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11555 { 2660 /* vsub */, ARM::VSUBv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11556 { 2660 /* vsub */, ARM::VSUBv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11557 { 2660 /* vsub */, ARM::VSUBv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11558 { 2660 /* vsub */, ARM::VSUBv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11559 { 2660 /* vsub */, ARM::VSUBv1i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11560 { 2660 /* vsub */, ARM::VSUBv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11561 { 2660 /* vsub */, ARM::VSUBv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11562 { 2660 /* vsub */, ARM::VSUBhq, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11563 { 2660 /* vsub */, ARM::VSUBhd, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON|Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11564 { 2660 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, }, 11565 { 2665 /* vsubhn */, ARM::VSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i16, MCK_DPR, MCK_QPR, MCK_QPR }, }, 11566 { 2665 /* vsubhn */, ARM::VSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i32, MCK_DPR, MCK_QPR, MCK_QPR }, }, 11567 { 2665 /* vsubhn */, ARM::VSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_i64, MCK_DPR, MCK_QPR, MCK_QPR }, }, 11568 { 2672 /* vsubl */, ARM::VSUBLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11569 { 2672 /* vsubl */, ARM::VSUBLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11570 { 2672 /* vsubl */, ARM::VSUBLsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11571 { 2672 /* vsubl */, ARM::VSUBLuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11572 { 2672 /* vsubl */, ARM::VSUBLuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11573 { 2672 /* vsubl */, ARM::VSUBLuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR, MCK_DPR }, }, 11574 { 2678 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_DPR }, }, 11575 { 2678 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, }, 11576 { 2678 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_DPR }, }, 11577 { 2678 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_DPR }, }, 11578 { 2678 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_DPR }, }, 11579 { 2678 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_DPR }, }, 11580 { 2678 /* vsubw */, ARM::VSUBWsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11581 { 2678 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11582 { 2678 /* vsubw */, ARM::VSUBWsv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_s8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11583 { 2678 /* vsubw */, ARM::VSUBWuv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u16, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11584 { 2678 /* vsubw */, ARM::VSUBWuv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u32, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11585 { 2678 /* vsubw */, ARM::VSUBWuv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR }, }, 11586 { 2684 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR }, }, 11587 { 2684 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR }, }, 11588 { 2684 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 11589 { 2684 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 11590 { 2684 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11591 { 2684 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 11592 { 2684 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR }, }, 11593 { 2684 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR }, }, 11594 { 2684 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 11595 { 2684 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 11596 { 2689 /* vtbl */, ARM::VTBL2, Convert__Reg1_2__VecListDPair1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, }, 11597 { 2689 /* vtbl */, ARM::VTBL4, Convert__Reg1_2__VecListFourD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, }, 11598 { 2689 /* vtbl */, ARM::VTBL1, Convert__Reg1_2__VecListOneD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, }, 11599 { 2689 /* vtbl */, ARM::VTBL3, Convert__Reg1_2__VecListThreeD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, }, 11600 { 2694 /* vtbx */, ARM::VTBX2, Convert__Reg1_2__Tie0_1_1__VecListDPair1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListDPair, MCK_DPR }, }, 11601 { 2694 /* vtbx */, ARM::VTBX4, Convert__Reg1_2__Tie0_1_1__VecListFourD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListFourD, MCK_DPR }, }, 11602 { 2694 /* vtbx */, ARM::VTBX1, Convert__Reg1_2__Tie0_1_1__VecListOneD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListOneD, MCK_DPR }, }, 11603 { 2694 /* vtbx */, ARM::VTBX3, Convert__Reg1_2__Tie0_1_1__VecListThreeD1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_VecListThreeD, MCK_DPR }, }, 11604 { 2699 /* vtrn */, ARM::VTRNq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 11605 { 2699 /* vtrn */, ARM::VTRNd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 11606 { 2699 /* vtrn */, ARM::VTRNq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11607 { 2699 /* vtrn */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 11608 { 2699 /* vtrn */, ARM::VTRNq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 11609 { 2699 /* vtrn */, ARM::VTRNd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 11610 { 2704 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 11611 { 2704 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 11612 { 2704 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11613 { 2704 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 11614 { 2704 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 11615 { 2704 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 11616 { 2704 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11617 { 2704 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11618 { 2704 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11619 { 2704 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11620 { 2704 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11621 { 2704 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11622 { 2709 /* vudot */, ARM::VUDOTQ, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, Feature_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_QPR }, }, 11623 { 2709 /* vudot */, ARM::VUDOTD, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3, Feature_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR }, }, 11624 { 2709 /* vudot */, ARM::VUDOTQI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasDotProd, { MCK__DOT_u8, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 11625 { 2709 /* vudot */, ARM::VUDOTDI, Convert__Reg1_1__Tie0_2_2__Reg1_2__Reg1_3__VectorIndex321_4, Feature_HasDotProd, { MCK__DOT_u8, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, }, 11626 { 2715 /* vuzp */, ARM::VUZPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 11627 { 2715 /* vuzp */, ARM::VUZPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 11628 { 2715 /* vuzp */, ARM::VUZPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11629 { 2715 /* vuzp */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 11630 { 2715 /* vuzp */, ARM::VUZPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 11631 { 2715 /* vuzp */, ARM::VUZPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 11632 { 2720 /* vzip */, ARM::VZIPq16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, }, 11633 { 2720 /* vzip */, ARM::VZIPd16, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, }, 11634 { 2720 /* vzip */, ARM::VZIPq32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, }, 11635 { 2720 /* vzip */, ARM::VTRNd32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, }, 11636 { 2720 /* vzip */, ARM::VZIPq8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR }, }, 11637 { 2720 /* vzip */, ARM::VZIPd8, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR }, }, 11638 { 2725 /* wfe */, ARM::HINT, Convert__imm_95_2__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, }, 11639 { 2725 /* wfe */, ARM::tHINT, Convert__imm_95_2__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, }, 11640 { 2725 /* wfe */, ARM::t2HINT, Convert__imm_95_2__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 11641 { 2729 /* wfi */, ARM::HINT, Convert__imm_95_3__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, }, 11642 { 2729 /* wfi */, ARM::tHINT, Convert__imm_95_3__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, }, 11643 { 2729 /* wfi */, ARM::t2HINT, Convert__imm_95_3__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 11644 { 2733 /* yield */, ARM::HINT, Convert__imm_95_1__CondCode2_0, Feature_IsARM|Feature_HasV6K, { MCK_CondCode }, }, 11645 { 2733 /* yield */, ARM::tHINT, Convert__imm_95_1__CondCode2_0, Feature_IsThumb|Feature_HasV6M, { MCK_CondCode }, }, 11646 { 2733 /* yield */, ARM::t2HINT, Convert__imm_95_1__CondCode2_0, Feature_IsThumb2, { MCK_CondCode, MCK__DOT_w }, }, 11647}; 11648 11649#include "llvm/Support/Debug.h" 11650#include "llvm/Support/Format.h" 11651 11652unsigned ARMAsmParser:: 11653MatchInstructionImpl(const OperandVector &Operands, 11654 MCInst &Inst, 11655 SmallVectorImpl<NearMissInfo> *NearMisses, 11656 bool matchingInlineAsm, unsigned VariantID) { 11657 // Get the current feature set. 11658 uint64_t AvailableFeatures = getAvailableFeatures(); 11659 11660 // Get the instruction mnemonic, which is the first token. 11661 StringRef Mnemonic = ((ARMOperand&)*Operands[0]).getToken(); 11662 11663 // Process all MnemonicAliases to remap the mnemonic. 11664 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); 11665 11666 // Find the appropriate table for this asm variant. 11667 const MatchEntry *Start, *End; 11668 switch (VariantID) { 11669 default: llvm_unreachable("invalid variant!"); 11670 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 11671 } 11672 // Search the table. 11673 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 11674 11675 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " << 11676 std::distance(MnemonicRange.first, MnemonicRange.second) << 11677 " encodings with mnemonic '" << Mnemonic << "'\n"); 11678 11679 // Return a more specific error code if no mnemonics match. 11680 if (MnemonicRange.first == MnemonicRange.second) 11681 return Match_MnemonicFail; 11682 11683 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 11684 it != ie; ++it) { 11685 bool HasRequiredFeatures = 11686 (AvailableFeatures & it->RequiredFeatures) == it->RequiredFeatures; 11687 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " 11688 << MII.getName(it->Opcode) << "\n"); 11689 // Some state to record ways in which this instruction did not match. 11690 NearMissInfo OperandNearMiss = NearMissInfo::getSuccess(); 11691 NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess(); 11692 NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess(); 11693 NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess(); 11694 bool MultipleInvalidOperands = false; 11695 // equal_range guarantees that instruction mnemonic matches. 11696 assert(Mnemonic == it->getMnemonic()); 11697 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 18; ++FormalIdx) { 11698 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); 11699 DEBUG_WITH_TYPE("asm-matcher", 11700 dbgs() << " Matching formal operand class " << getMatchClassName(Formal) 11701 << " against actual operand at index " << ActualIdx); 11702 if (ActualIdx < Operands.size()) 11703 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " ("; 11704 Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); 11705 else 11706 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": "); 11707 if (ActualIdx >= Operands.size()) { 11708 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range "); 11709 bool ThisOperandValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass); 11710 if (!ThisOperandValid) { 11711 if (!OperandNearMiss) { 11712 // Record info about match failure for later use. 11713 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "recording too-few-operands near miss\n"); 11714 OperandNearMiss = 11715 NearMissInfo::getTooFewOperands(Formal, it->Opcode); 11716 } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) { 11717 // If more than one operand is invalid, give up on this match entry. 11718 DEBUG_WITH_TYPE( 11719 "asm-matcher", 11720 dbgs() << "second invalid operand, giving up on this opcode\n"); 11721 MultipleInvalidOperands = true; 11722 break; 11723 } 11724 } else { 11725 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "but formal operand not required\n"); 11726 break; 11727 } 11728 continue; 11729 } 11730 MCParsedAsmOperand &Actual = *Operands[ActualIdx]; 11731 unsigned Diag = validateOperandClass(Actual, Formal); 11732 if (Diag == Match_Success) { 11733 DEBUG_WITH_TYPE("asm-matcher", 11734 dbgs() << "match success using generic matcher\n"); 11735 ++ActualIdx; 11736 continue; 11737 } 11738 // If the generic handler indicates an invalid operand 11739 // failure, check for a special case. 11740 if (Diag != Match_Success) { 11741 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); 11742 if (TargetDiag == Match_Success) { 11743 DEBUG_WITH_TYPE("asm-matcher", 11744 dbgs() << "match success using target matcher\n"); 11745 ++ActualIdx; 11746 continue; 11747 } 11748 // If the target matcher returned a specific error code use 11749 // that, else use the one from the generic matcher. 11750 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures) 11751 Diag = TargetDiag; 11752 } 11753 // If current formal operand wasn't matched and it is optional 11754 // then try to match next formal operand 11755 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { 11756 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); 11757 continue; 11758 } 11759 if (!OperandNearMiss) { 11760 // If this is the first invalid operand we have seen, record some 11761 // information about it. 11762 DEBUG_WITH_TYPE( 11763 "asm-matcher", 11764 dbgs() 11765 << "operand match failed, recording near-miss with diag code " 11766 << Diag << "\n"); 11767 OperandNearMiss = 11768 NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx); 11769 ++ActualIdx; 11770 } else { 11771 // If more than one operand is invalid, give up on this match entry. 11772 DEBUG_WITH_TYPE( 11773 "asm-matcher", 11774 dbgs() << "second operand mismatch, skipping this opcode\n"); 11775 MultipleInvalidOperands = true; 11776 break; 11777 } 11778 } 11779 11780 if (MultipleInvalidOperands) { 11781 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 11782 "operand mismatches, ignoring " 11783 "this opcode\n"); 11784 continue; 11785 } 11786 if (!HasRequiredFeatures) { 11787 uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures; 11788 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features: " 11789 << format_hex(NewMissingFeatures, 18) 11790 << "\n"); 11791 FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures); 11792 } 11793 11794 Inst.clear(); 11795 11796 Inst.setOpcode(it->Opcode); 11797 // We have a potential match but have not rendered the operands. 11798 // Check the target predicate to handle any context sensitive 11799 // constraints. 11800 // For example, Ties that are referenced multiple times must be 11801 // checked here to ensure the input is the same for each match 11802 // constraints. If we leave it any later the ties will have been 11803 // canonicalized 11804 unsigned MatchResult; 11805 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { 11806 Inst.clear(); 11807 DEBUG_WITH_TYPE( 11808 "asm-matcher", 11809 dbgs() << "Early target match predicate failed with diag code " 11810 << MatchResult << "\n"); 11811 EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult); 11812 } 11813 11814 // If we did not successfully match the operands, then we can't convert to 11815 // an MCInst, so bail out on this instruction variant now. 11816 if (OperandNearMiss) { 11817 // If the operand mismatch was the only problem, reprrt it as a near-miss. 11818 if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) { 11819 DEBUG_WITH_TYPE( 11820 "asm-matcher", 11821 dbgs() 11822 << "Opcode result: one mismatched operand, adding near-miss\n"); 11823 NearMisses->push_back(OperandNearMiss); 11824 } else { 11825 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 11826 "types of mismatch, so not " 11827 "reporting near-miss\n"); 11828 } 11829 continue; 11830 } 11831 11832 if (matchingInlineAsm) { 11833 convertToMapAndConstraints(it->ConvertFn, Operands); 11834 return Match_Success; 11835 } 11836 11837 // We have selected a definite instruction, convert the parsed 11838 // operands into the appropriate MCInst. 11839 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); 11840 11841 // We have a potential match. Check the target predicate to 11842 // handle any context sensitive constraints. 11843 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { 11844 DEBUG_WITH_TYPE("asm-matcher", 11845 dbgs() << "Target match predicate failed with diag code " 11846 << MatchResult << "\n"); 11847 Inst.clear(); 11848 LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult); 11849 } 11850 11851 int NumNearMisses = ((int)(bool)OperandNearMiss + 11852 (int)(bool)FeaturesNearMiss + 11853 (int)(bool)EarlyPredicateNearMiss + 11854 (int)(bool)LatePredicateNearMiss); 11855 if (NumNearMisses == 1) { 11856 // We had exactly one type of near-miss, so add that to the list. 11857 assert(!OperandNearMiss && "OperandNearMiss was handled earlier"); 11858 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: found one type of " 11859 "mismatch, so reporting a " 11860 "near-miss\n"); 11861 if (NearMisses && FeaturesNearMiss) 11862 NearMisses->push_back(FeaturesNearMiss); 11863 else if (NearMisses && EarlyPredicateNearMiss) 11864 NearMisses->push_back(EarlyPredicateNearMiss); 11865 else if (NearMisses && LatePredicateNearMiss) 11866 NearMisses->push_back(LatePredicateNearMiss); 11867 11868 continue; 11869 } else if (NumNearMisses > 1) { 11870 // This instruction missed in more than one way, so ignore it. 11871 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 11872 "types of mismatch, so not " 11873 "reporting near-miss\n"); 11874 continue; 11875 } 11876 std::string Info; 11877 if (!getParser().getTargetParser(). 11878 getTargetOptions().MCNoDeprecatedWarn && 11879 MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) { 11880 SMLoc Loc = ((ARMOperand&)*Operands[0]).getStartLoc(); 11881 getParser().Warning(Loc, Info, None); 11882 } 11883 DEBUG_WITH_TYPE( 11884 "asm-matcher", 11885 dbgs() << "Opcode result: complete match, selecting this opcode\n"); 11886 return Match_Success; 11887 } 11888 11889 // No instruction variants matched exactly. 11890 return Match_NearMisses; 11891} 11892 11893namespace { 11894 struct OperandMatchEntry { 11895 uint64_t RequiredFeatures; 11896 uint16_t Mnemonic; 11897 uint16_t Class; 11898 uint8_t OperandMask; 11899 11900 StringRef getMnemonic() const { 11901 return StringRef(MnemonicTable + Mnemonic + 1, 11902 MnemonicTable[Mnemonic]); 11903 } 11904 }; 11905 11906 // Predicate for searching for an opcode. 11907 struct LessOpcodeOperand { 11908 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { 11909 return LHS.getMnemonic() < RHS; 11910 } 11911 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { 11912 return LHS < RHS.getMnemonic(); 11913 } 11914 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { 11915 return LHS.getMnemonic() < RHS.getMnemonic(); 11916 } 11917 }; 11918} // end anonymous namespace. 11919 11920static const OperandMatchEntry OperandMatchTable[731] = { 11921 /* Operand List Mask, Mnemonic, Operand Class, Features */ 11922 { Feature_IsARM, 10 /* adc */, MCK_ModImm, 8 /* 3 */ }, 11923 { Feature_IsARM, 10 /* adc */, MCK_ModImm, 16 /* 4 */ }, 11924 { Feature_IsARM, 14 /* add */, MCK_ModImm, 8 /* 3 */ }, 11925 { Feature_IsARM, 14 /* add */, MCK_ModImm, 16 /* 4 */ }, 11926 { Feature_IsARM, 50 /* and */, MCK_ModImm, 8 /* 3 */ }, 11927 { Feature_IsARM, 50 /* and */, MCK_ModImm, 16 /* 4 */ }, 11928 { Feature_IsThumb2, 60 /* bfc */, MCK_Bitfield, 4 /* 2 */ }, 11929 { Feature_IsARM|Feature_HasV6T2, 60 /* bfc */, MCK_Bitfield, 4 /* 2 */ }, 11930 { Feature_IsThumb2, 64 /* bfi */, MCK_Bitfield, 8 /* 3 */ }, 11931 { Feature_IsARM|Feature_HasV6T2, 64 /* bfi */, MCK_Bitfield, 8 /* 3 */ }, 11932 { Feature_IsARM, 68 /* bic */, MCK_ModImm, 8 /* 3 */ }, 11933 { Feature_IsARM, 68 /* bic */, MCK_ModImm, 16 /* 4 */ }, 11934 { Feature_IsARM|Feature_PreV8, 111 /* cdp */, MCK_CoprocNum, 2 /* 1 */ }, 11935 { Feature_IsARM|Feature_PreV8, 111 /* cdp */, MCK_CoprocReg, 56 /* 3, 4, 5 */ }, 11936 { Feature_IsThumb2|Feature_PreV8, 111 /* cdp */, MCK_CoprocNum, 2 /* 1 */ }, 11937 { Feature_IsThumb2|Feature_PreV8, 111 /* cdp */, MCK_CoprocReg, 56 /* 3, 4, 5 */ }, 11938 { Feature_IsARM|Feature_PreV8, 115 /* cdp2 */, MCK_CoprocNum, 1 /* 0 */ }, 11939 { Feature_IsARM|Feature_PreV8, 115 /* cdp2 */, MCK_CoprocReg, 28 /* 2, 3, 4 */ }, 11940 { Feature_IsThumb2|Feature_PreV8, 115 /* cdp2 */, MCK_CoprocNum, 2 /* 1 */ }, 11941 { Feature_IsThumb2|Feature_PreV8, 115 /* cdp2 */, MCK_CoprocReg, 56 /* 3, 4, 5 */ }, 11942 { Feature_IsARM, 130 /* cmn */, MCK_ModImm, 4 /* 2 */ }, 11943 { Feature_IsARM, 134 /* cmp */, MCK_ModImm, 4 /* 2 */ }, 11944 { Feature_IsARM, 138 /* cps */, MCK_ProcIFlags, 2 /* 1 */ }, 11945 { Feature_IsThumb, 138 /* cps */, MCK_ProcIFlags, 2 /* 1 */ }, 11946 { Feature_IsThumb2|Feature_IsNotMClass, 138 /* cps */, MCK_ProcIFlags, 4 /* 2 */ }, 11947 { Feature_IsARM, 138 /* cps */, MCK_ProcIFlags, 2 /* 1 */ }, 11948 { Feature_IsThumb2|Feature_IsNotMClass, 138 /* cps */, MCK_ProcIFlags, 2 /* 1 */ }, 11949 { Feature_IsThumb2, 138 /* cps */, MCK_ProcIFlags, 4 /* 2 */ }, 11950 { Feature_IsARM|Feature_HasDB, 218 /* dmb */, MCK_MemBarrierOpt, 1 /* 0 */ }, 11951 { Feature_IsThumb|Feature_HasDB, 218 /* dmb */, MCK_MemBarrierOpt, 2 /* 1 */ }, 11952 { Feature_IsARM|Feature_HasDB, 222 /* dsb */, MCK_MemBarrierOpt, 1 /* 0 */ }, 11953 { Feature_IsThumb|Feature_HasDB, 222 /* dsb */, MCK_MemBarrierOpt, 2 /* 1 */ }, 11954 { Feature_IsARM, 226 /* eor */, MCK_ModImm, 8 /* 3 */ }, 11955 { Feature_IsARM, 226 /* eor */, MCK_ModImm, 16 /* 4 */ }, 11956 { Feature_HasVFP3, 265 /* fconstd */, MCK_FPImm, 4 /* 2 */ }, 11957 { Feature_HasVFP3, 273 /* fconsts */, MCK_FPImm, 4 /* 2 */ }, 11958 { Feature_IsARM|Feature_HasDB, 357 /* isb */, MCK_InstSyncBarrierOpt, 1 /* 0 */ }, 11959 { Feature_IsThumb|Feature_HasDB, 357 /* isb */, MCK_InstSyncBarrierOpt, 2 /* 1 */ }, 11960 { Feature_IsARM, 361 /* it */, MCK_ITCondCode, 2 /* 1 */ }, 11961 { Feature_IsThumb2, 361 /* it */, MCK_ITCondCode, 2 /* 1 */ }, 11962 { Feature_IsARM, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ }, 11963 { Feature_IsARM, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ }, 11964 { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ }, 11965 { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ }, 11966 { Feature_IsARM, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ }, 11967 { Feature_IsARM, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ }, 11968 { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ }, 11969 { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ }, 11970 { Feature_IsARM, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ }, 11971 { Feature_IsARM, 405 /* ldc */, MCK_CoprocOption, 16 /* 4 */ }, 11972 { Feature_IsARM, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ }, 11973 { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ }, 11974 { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocOption, 16 /* 4 */ }, 11975 { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ }, 11976 { Feature_IsARM, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ }, 11977 { Feature_IsARM, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ }, 11978 { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocNum, 2 /* 1 */ }, 11979 { Feature_IsThumb2, 405 /* ldc */, MCK_CoprocReg, 4 /* 2 */ }, 11980 { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocNum, 1 /* 0 */ }, 11981 { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocReg, 2 /* 1 */ }, 11982 { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocNum, 2 /* 1 */ }, 11983 { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocReg, 4 /* 2 */ }, 11984 { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocNum, 1 /* 0 */ }, 11985 { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocReg, 2 /* 1 */ }, 11986 { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocNum, 1 /* 0 */ }, 11987 { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocOption, 8 /* 3 */ }, 11988 { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocReg, 2 /* 1 */ }, 11989 { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocNum, 1 /* 0 */ }, 11990 { Feature_IsARM|Feature_PreV8, 409 /* ldc2 */, MCK_CoprocReg, 2 /* 1 */ }, 11991 { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocNum, 2 /* 1 */ }, 11992 { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocReg, 4 /* 2 */ }, 11993 { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocNum, 2 /* 1 */ }, 11994 { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocOption, 16 /* 4 */ }, 11995 { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocReg, 4 /* 2 */ }, 11996 { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocNum, 2 /* 1 */ }, 11997 { Feature_PreV8|Feature_IsThumb2, 409 /* ldc2 */, MCK_CoprocReg, 4 /* 2 */ }, 11998 { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocNum, 1 /* 0 */ }, 11999 { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocReg, 2 /* 1 */ }, 12000 { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocNum, 2 /* 1 */ }, 12001 { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocReg, 4 /* 2 */ }, 12002 { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocNum, 1 /* 0 */ }, 12003 { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocReg, 2 /* 1 */ }, 12004 { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocNum, 1 /* 0 */ }, 12005 { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocOption, 8 /* 3 */ }, 12006 { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocReg, 2 /* 1 */ }, 12007 { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocNum, 1 /* 0 */ }, 12008 { Feature_IsARM|Feature_PreV8, 414 /* ldc2l */, MCK_CoprocReg, 2 /* 1 */ }, 12009 { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocNum, 2 /* 1 */ }, 12010 { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocReg, 4 /* 2 */ }, 12011 { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocNum, 2 /* 1 */ }, 12012 { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocOption, 16 /* 4 */ }, 12013 { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocReg, 4 /* 2 */ }, 12014 { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocNum, 2 /* 1 */ }, 12015 { Feature_PreV8|Feature_IsThumb2, 414 /* ldc2l */, MCK_CoprocReg, 4 /* 2 */ }, 12016 { Feature_IsARM, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ }, 12017 { Feature_IsARM, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ }, 12018 { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ }, 12019 { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ }, 12020 { Feature_IsARM, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ }, 12021 { Feature_IsARM, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ }, 12022 { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ }, 12023 { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ }, 12024 { Feature_IsARM, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ }, 12025 { Feature_IsARM, 420 /* ldcl */, MCK_CoprocOption, 16 /* 4 */ }, 12026 { Feature_IsARM, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ }, 12027 { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ }, 12028 { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocOption, 16 /* 4 */ }, 12029 { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ }, 12030 { Feature_IsARM, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ }, 12031 { Feature_IsARM, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ }, 12032 { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocNum, 2 /* 1 */ }, 12033 { Feature_IsThumb2, 420 /* ldcl */, MCK_CoprocReg, 4 /* 2 */ }, 12034 { Feature_IsARM, 447 /* ldr */, MCK_PostIdxRegShifted, 8 /* 3 */ }, 12035 { Feature_IsARM, 451 /* ldrb */, MCK_PostIdxRegShifted, 8 /* 3 */ }, 12036 { Feature_IsARM, 456 /* ldrbt */, MCK_PostIdxRegShifted, 8 /* 3 */ }, 12037 { Feature_IsARM, 462 /* ldrd */, MCK_AM3Offset, 16 /* 4 */ }, 12038 { Feature_IsARM, 494 /* ldrh */, MCK_AM3Offset, 8 /* 3 */ }, 12039 { Feature_IsARM, 499 /* ldrht */, MCK_PostIdxReg, 8 /* 3 */ }, 12040 { Feature_IsARM, 505 /* ldrsb */, MCK_AM3Offset, 8 /* 3 */ }, 12041 { Feature_IsARM, 511 /* ldrsbt */, MCK_PostIdxReg, 8 /* 3 */ }, 12042 { Feature_IsARM, 518 /* ldrsh */, MCK_AM3Offset, 8 /* 3 */ }, 12043 { Feature_IsARM, 524 /* ldrsht */, MCK_PostIdxReg, 8 /* 3 */ }, 12044 { Feature_IsARM, 531 /* ldrt */, MCK_PostIdxRegShifted, 8 /* 3 */ }, 12045 { Feature_IsARM, 544 /* mcr */, MCK_CoprocNum, 2 /* 1 */ }, 12046 { Feature_IsARM, 544 /* mcr */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12047 { Feature_IsThumb2, 544 /* mcr */, MCK_CoprocNum, 2 /* 1 */ }, 12048 { Feature_IsThumb2, 544 /* mcr */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12049 { Feature_IsARM, 544 /* mcr */, MCK_CoprocNum, 2 /* 1 */ }, 12050 { Feature_IsARM, 544 /* mcr */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12051 { Feature_IsThumb2, 544 /* mcr */, MCK_CoprocNum, 2 /* 1 */ }, 12052 { Feature_IsThumb2, 544 /* mcr */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12053 { Feature_IsARM, 548 /* mcr2 */, MCK_CoprocNum, 1 /* 0 */ }, 12054 { Feature_IsARM, 548 /* mcr2 */, MCK_CoprocReg, 24 /* 3, 4 */ }, 12055 { Feature_IsThumb2, 548 /* mcr2 */, MCK_CoprocNum, 2 /* 1 */ }, 12056 { Feature_IsThumb2, 548 /* mcr2 */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12057 { Feature_IsARM|Feature_PreV8, 548 /* mcr2 */, MCK_CoprocNum, 1 /* 0 */ }, 12058 { Feature_IsARM|Feature_PreV8, 548 /* mcr2 */, MCK_CoprocReg, 24 /* 3, 4 */ }, 12059 { Feature_IsThumb2|Feature_PreV8, 548 /* mcr2 */, MCK_CoprocNum, 2 /* 1 */ }, 12060 { Feature_IsThumb2|Feature_PreV8, 548 /* mcr2 */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12061 { Feature_IsARM, 553 /* mcrr */, MCK_CoprocNum, 2 /* 1 */ }, 12062 { Feature_IsARM, 553 /* mcrr */, MCK_CoprocReg, 32 /* 5 */ }, 12063 { Feature_IsThumb2, 553 /* mcrr */, MCK_CoprocNum, 2 /* 1 */ }, 12064 { Feature_IsThumb2, 553 /* mcrr */, MCK_CoprocReg, 32 /* 5 */ }, 12065 { Feature_IsARM|Feature_PreV8, 558 /* mcrr2 */, MCK_CoprocNum, 1 /* 0 */ }, 12066 { Feature_IsARM|Feature_PreV8, 558 /* mcrr2 */, MCK_CoprocReg, 16 /* 4 */ }, 12067 { Feature_IsThumb2|Feature_PreV8, 558 /* mcrr2 */, MCK_CoprocNum, 2 /* 1 */ }, 12068 { Feature_IsThumb2|Feature_PreV8, 558 /* mcrr2 */, MCK_CoprocReg, 32 /* 5 */ }, 12069 { Feature_IsARM, 572 /* mov */, MCK_ModImm, 8 /* 3 */ }, 12070 { Feature_IsARM, 591 /* mrc */, MCK_CoprocNum, 2 /* 1 */ }, 12071 { Feature_IsARM, 591 /* mrc */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12072 { Feature_IsThumb2, 591 /* mrc */, MCK_CoprocNum, 2 /* 1 */ }, 12073 { Feature_IsThumb2, 591 /* mrc */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12074 { Feature_IsARM, 591 /* mrc */, MCK_CoprocNum, 2 /* 1 */ }, 12075 { Feature_IsARM, 591 /* mrc */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12076 { Feature_IsThumb2, 591 /* mrc */, MCK_CoprocNum, 2 /* 1 */ }, 12077 { Feature_IsThumb2, 591 /* mrc */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12078 { Feature_IsARM, 595 /* mrc2 */, MCK_CoprocNum, 1 /* 0 */ }, 12079 { Feature_IsARM, 595 /* mrc2 */, MCK_CoprocReg, 24 /* 3, 4 */ }, 12080 { Feature_IsThumb2, 595 /* mrc2 */, MCK_CoprocNum, 2 /* 1 */ }, 12081 { Feature_IsThumb2, 595 /* mrc2 */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12082 { Feature_IsARM|Feature_PreV8, 595 /* mrc2 */, MCK_CoprocNum, 1 /* 0 */ }, 12083 { Feature_IsARM|Feature_PreV8, 595 /* mrc2 */, MCK_CoprocReg, 24 /* 3, 4 */ }, 12084 { Feature_IsThumb2|Feature_PreV8, 595 /* mrc2 */, MCK_CoprocNum, 2 /* 1 */ }, 12085 { Feature_IsThumb2|Feature_PreV8, 595 /* mrc2 */, MCK_CoprocReg, 48 /* 4, 5 */ }, 12086 { Feature_IsARM, 600 /* mrrc */, MCK_CoprocNum, 2 /* 1 */ }, 12087 { Feature_IsARM, 600 /* mrrc */, MCK_CoprocReg, 32 /* 5 */ }, 12088 { Feature_IsThumb2, 600 /* mrrc */, MCK_CoprocNum, 2 /* 1 */ }, 12089 { Feature_IsThumb2, 600 /* mrrc */, MCK_CoprocReg, 32 /* 5 */ }, 12090 { Feature_IsARM|Feature_PreV8, 605 /* mrrc2 */, MCK_CoprocNum, 1 /* 0 */ }, 12091 { Feature_IsARM|Feature_PreV8, 605 /* mrrc2 */, MCK_CoprocReg, 16 /* 4 */ }, 12092 { Feature_IsThumb2|Feature_PreV8, 605 /* mrrc2 */, MCK_CoprocNum, 2 /* 1 */ }, 12093 { Feature_IsThumb2|Feature_PreV8, 605 /* mrrc2 */, MCK_CoprocReg, 32 /* 5 */ }, 12094 { Feature_IsThumb|Feature_HasVirtualization, 611 /* mrs */, MCK_BankedReg, 4 /* 2 */ }, 12095 { Feature_IsThumb|Feature_IsMClass, 611 /* mrs */, MCK_MSRMask, 4 /* 2 */ }, 12096 { Feature_IsARM|Feature_HasVirtualization, 611 /* mrs */, MCK_BankedReg, 4 /* 2 */ }, 12097 { Feature_IsThumb|Feature_HasVirtualization, 615 /* msr */, MCK_BankedReg, 2 /* 1 */ }, 12098 { Feature_IsARM|Feature_HasVirtualization, 615 /* msr */, MCK_BankedReg, 2 /* 1 */ }, 12099 { Feature_IsThumb2|Feature_IsNotMClass, 615 /* msr */, MCK_MSRMask, 2 /* 1 */ }, 12100 { Feature_IsThumb|Feature_IsMClass, 615 /* msr */, MCK_MSRMask, 2 /* 1 */ }, 12101 { Feature_IsARM, 615 /* msr */, MCK_MSRMask, 2 /* 1 */ }, 12102 { Feature_IsARM, 615 /* msr */, MCK_MSRMask, 2 /* 1 */ }, 12103 { Feature_IsARM, 615 /* msr */, MCK_ModImm, 4 /* 2 */ }, 12104 { Feature_IsARM, 623 /* mvn */, MCK_ModImm, 8 /* 3 */ }, 12105 { Feature_IsARM, 639 /* orr */, MCK_ModImm, 8 /* 3 */ }, 12106 { Feature_IsARM, 639 /* orr */, MCK_ModImm, 16 /* 4 */ }, 12107 { Feature_HasDSP|Feature_IsThumb2, 643 /* pkhbt */, MCK_PKHLSLImm, 16 /* 4 */ }, 12108 { Feature_IsARM|Feature_HasV6, 643 /* pkhbt */, MCK_PKHLSLImm, 16 /* 4 */ }, 12109 { Feature_HasDSP|Feature_IsThumb2, 649 /* pkhtb */, MCK_PKHASRImm, 16 /* 4 */ }, 12110 { Feature_IsARM|Feature_HasV6, 649 /* pkhtb */, MCK_PKHASRImm, 16 /* 4 */ }, 12111 { Feature_IsARM, 788 /* rsb */, MCK_ModImm, 8 /* 3 */ }, 12112 { Feature_IsARM, 788 /* rsb */, MCK_ModImm, 16 /* 4 */ }, 12113 { Feature_IsARM, 792 /* rsc */, MCK_ModImm, 8 /* 3 */ }, 12114 { Feature_IsARM, 792 /* rsc */, MCK_ModImm, 16 /* 4 */ }, 12115 { Feature_IsARM, 814 /* sbc */, MCK_ModImm, 8 /* 3 */ }, 12116 { Feature_IsARM, 814 /* sbc */, MCK_ModImm, 16 /* 4 */ }, 12117 { Feature_IsThumb|Feature_IsNotMClass, 832 /* setend */, MCK_SetEndImm, 1 /* 0 */ }, 12118 { Feature_IsARM, 832 /* setend */, MCK_SetEndImm, 1 /* 0 */ }, 12119 { Feature_IsThumb2, 1254 /* ssat */, MCK_ShifterImm, 16 /* 4 */ }, 12120 { Feature_IsARM|Feature_HasV6, 1254 /* ssat */, MCK_ShifterImm, 16 /* 4 */ }, 12121 { Feature_IsARM, 1284 /* stc */, MCK_CoprocNum, 2 /* 1 */ }, 12122 { Feature_IsARM, 1284 /* stc */, MCK_CoprocReg, 4 /* 2 */ }, 12123 { Feature_IsThumb2, 1284 /* stc */, MCK_CoprocNum, 2 /* 1 */ }, 12124 { Feature_IsThumb2, 1284 /* stc */, MCK_CoprocReg, 4 /* 2 */ }, 12125 { Feature_IsARM, 1284 /* stc */, MCK_CoprocNum, 2 /* 1 */ }, 12126 { Feature_IsARM, 1284 /* stc */, MCK_CoprocReg, 4 /* 2 */ }, 12127 { Feature_IsThumb2, 1284 /* stc */, MCK_CoprocNum, 2 /* 1 */ }, 12128 { Feature_IsThumb2, 1284 /* stc */, MCK_CoprocReg, 4 /* 2 */ }, 12129 { Feature_IsARM, 1284 /* stc */, MCK_CoprocNum, 2 /* 1 */ }, 12130 { Feature_IsARM, 1284 /* stc */, MCK_CoprocOption, 16 /* 4 */ }, 12131 { Feature_IsARM, 1284 /* stc */, MCK_CoprocReg, 4 /* 2 */ }, 12132 { Feature_IsThumb2, 1284 /* stc */, MCK_CoprocNum, 2 /* 1 */ }, 12133 { Feature_IsThumb2, 1284 /* stc */, MCK_CoprocOption, 16 /* 4 */ }, 12134 { Feature_IsThumb2, 1284 /* stc */, MCK_CoprocReg, 4 /* 2 */ }, 12135 { Feature_IsARM, 1284 /* stc */, MCK_CoprocNum, 2 /* 1 */ }, 12136 { Feature_IsARM, 1284 /* stc */, MCK_CoprocReg, 4 /* 2 */ }, 12137 { Feature_IsThumb2, 1284 /* stc */, MCK_CoprocNum, 2 /* 1 */ }, 12138 { Feature_IsThumb2, 1284 /* stc */, MCK_CoprocReg, 4 /* 2 */ }, 12139 { Feature_IsARM|Feature_PreV8, 1288 /* stc2 */, MCK_CoprocNum, 1 /* 0 */ }, 12140 { Feature_IsARM|Feature_PreV8, 1288 /* stc2 */, MCK_CoprocReg, 2 /* 1 */ }, 12141 { Feature_PreV8|Feature_IsThumb2, 1288 /* stc2 */, MCK_CoprocNum, 2 /* 1 */ }, 12142 { Feature_PreV8|Feature_IsThumb2, 1288 /* stc2 */, MCK_CoprocReg, 4 /* 2 */ }, 12143 { Feature_IsARM|Feature_PreV8, 1288 /* stc2 */, MCK_CoprocNum, 1 /* 0 */ }, 12144 { Feature_IsARM|Feature_PreV8, 1288 /* stc2 */, MCK_CoprocReg, 2 /* 1 */ }, 12145 { Feature_IsARM|Feature_PreV8, 1288 /* stc2 */, MCK_CoprocNum, 1 /* 0 */ }, 12146 { Feature_IsARM|Feature_PreV8, 1288 /* stc2 */, MCK_CoprocOption, 8 /* 3 */ }, 12147 { Feature_IsARM|Feature_PreV8, 1288 /* stc2 */, MCK_CoprocReg, 2 /* 1 */ }, 12148 { Feature_IsARM|Feature_PreV8, 1288 /* stc2 */, MCK_CoprocNum, 1 /* 0 */ }, 12149 { Feature_IsARM|Feature_PreV8, 1288 /* stc2 */, MCK_CoprocReg, 2 /* 1 */ }, 12150 { Feature_PreV8|Feature_IsThumb2, 1288 /* stc2 */, MCK_CoprocNum, 2 /* 1 */ }, 12151 { Feature_PreV8|Feature_IsThumb2, 1288 /* stc2 */, MCK_CoprocReg, 4 /* 2 */ }, 12152 { Feature_PreV8|Feature_IsThumb2, 1288 /* stc2 */, MCK_CoprocNum, 2 /* 1 */ }, 12153 { Feature_PreV8|Feature_IsThumb2, 1288 /* stc2 */, MCK_CoprocOption, 16 /* 4 */ }, 12154 { Feature_PreV8|Feature_IsThumb2, 1288 /* stc2 */, MCK_CoprocReg, 4 /* 2 */ }, 12155 { Feature_PreV8|Feature_IsThumb2, 1288 /* stc2 */, MCK_CoprocNum, 2 /* 1 */ }, 12156 { Feature_PreV8|Feature_IsThumb2, 1288 /* stc2 */, MCK_CoprocReg, 4 /* 2 */ }, 12157 { Feature_IsARM|Feature_PreV8, 1293 /* stc2l */, MCK_CoprocNum, 1 /* 0 */ }, 12158 { Feature_IsARM|Feature_PreV8, 1293 /* stc2l */, MCK_CoprocReg, 2 /* 1 */ }, 12159 { Feature_PreV8|Feature_IsThumb2, 1293 /* stc2l */, MCK_CoprocNum, 2 /* 1 */ }, 12160 { Feature_PreV8|Feature_IsThumb2, 1293 /* stc2l */, MCK_CoprocReg, 4 /* 2 */ }, 12161 { Feature_IsARM|Feature_PreV8, 1293 /* stc2l */, MCK_CoprocNum, 1 /* 0 */ }, 12162 { Feature_IsARM|Feature_PreV8, 1293 /* stc2l */, MCK_CoprocReg, 2 /* 1 */ }, 12163 { Feature_IsARM|Feature_PreV8, 1293 /* stc2l */, MCK_CoprocNum, 1 /* 0 */ }, 12164 { Feature_IsARM|Feature_PreV8, 1293 /* stc2l */, MCK_CoprocOption, 8 /* 3 */ }, 12165 { Feature_IsARM|Feature_PreV8, 1293 /* stc2l */, MCK_CoprocReg, 2 /* 1 */ }, 12166 { Feature_IsARM|Feature_PreV8, 1293 /* stc2l */, MCK_CoprocNum, 1 /* 0 */ }, 12167 { Feature_IsARM|Feature_PreV8, 1293 /* stc2l */, MCK_CoprocReg, 2 /* 1 */ }, 12168 { Feature_PreV8|Feature_IsThumb2, 1293 /* stc2l */, MCK_CoprocNum, 2 /* 1 */ }, 12169 { Feature_PreV8|Feature_IsThumb2, 1293 /* stc2l */, MCK_CoprocReg, 4 /* 2 */ }, 12170 { Feature_PreV8|Feature_IsThumb2, 1293 /* stc2l */, MCK_CoprocNum, 2 /* 1 */ }, 12171 { Feature_PreV8|Feature_IsThumb2, 1293 /* stc2l */, MCK_CoprocOption, 16 /* 4 */ }, 12172 { Feature_PreV8|Feature_IsThumb2, 1293 /* stc2l */, MCK_CoprocReg, 4 /* 2 */ }, 12173 { Feature_PreV8|Feature_IsThumb2, 1293 /* stc2l */, MCK_CoprocNum, 2 /* 1 */ }, 12174 { Feature_PreV8|Feature_IsThumb2, 1293 /* stc2l */, MCK_CoprocReg, 4 /* 2 */ }, 12175 { Feature_IsARM, 1299 /* stcl */, MCK_CoprocNum, 2 /* 1 */ }, 12176 { Feature_IsARM, 1299 /* stcl */, MCK_CoprocReg, 4 /* 2 */ }, 12177 { Feature_IsThumb2, 1299 /* stcl */, MCK_CoprocNum, 2 /* 1 */ }, 12178 { Feature_IsThumb2, 1299 /* stcl */, MCK_CoprocReg, 4 /* 2 */ }, 12179 { Feature_IsARM, 1299 /* stcl */, MCK_CoprocNum, 2 /* 1 */ }, 12180 { Feature_IsARM, 1299 /* stcl */, MCK_CoprocReg, 4 /* 2 */ }, 12181 { Feature_IsThumb2, 1299 /* stcl */, MCK_CoprocNum, 2 /* 1 */ }, 12182 { Feature_IsThumb2, 1299 /* stcl */, MCK_CoprocReg, 4 /* 2 */ }, 12183 { Feature_IsARM, 1299 /* stcl */, MCK_CoprocNum, 2 /* 1 */ }, 12184 { Feature_IsARM, 1299 /* stcl */, MCK_CoprocOption, 16 /* 4 */ }, 12185 { Feature_IsARM, 1299 /* stcl */, MCK_CoprocReg, 4 /* 2 */ }, 12186 { Feature_IsThumb2, 1299 /* stcl */, MCK_CoprocNum, 2 /* 1 */ }, 12187 { Feature_IsThumb2, 1299 /* stcl */, MCK_CoprocOption, 16 /* 4 */ }, 12188 { Feature_IsThumb2, 1299 /* stcl */, MCK_CoprocReg, 4 /* 2 */ }, 12189 { Feature_IsARM, 1299 /* stcl */, MCK_CoprocNum, 2 /* 1 */ }, 12190 { Feature_IsARM, 1299 /* stcl */, MCK_CoprocReg, 4 /* 2 */ }, 12191 { Feature_IsThumb2, 1299 /* stcl */, MCK_CoprocNum, 2 /* 1 */ }, 12192 { Feature_IsThumb2, 1299 /* stcl */, MCK_CoprocReg, 4 /* 2 */ }, 12193 { Feature_IsARM, 1367 /* str */, MCK_PostIdxRegShifted, 8 /* 3 */ }, 12194 { Feature_IsARM, 1371 /* strb */, MCK_PostIdxRegShifted, 8 /* 3 */ }, 12195 { Feature_IsARM, 1376 /* strbt */, MCK_PostIdxRegShifted, 8 /* 3 */ }, 12196 { Feature_IsARM, 1382 /* strd */, MCK_AM3Offset, 16 /* 4 */ }, 12197 { Feature_IsARM, 1414 /* strh */, MCK_AM3Offset, 8 /* 3 */ }, 12198 { Feature_IsARM, 1419 /* strht */, MCK_PostIdxReg, 8 /* 3 */ }, 12199 { Feature_IsARM, 1425 /* strt */, MCK_PostIdxRegShifted, 8 /* 3 */ }, 12200 { Feature_IsARM, 1430 /* sub */, MCK_ModImm, 8 /* 3 */ }, 12201 { Feature_IsARM, 1430 /* sub */, MCK_ModImm, 16 /* 4 */ }, 12202 { Feature_HasDSP|Feature_IsThumb2, 1457 /* sxtab */, MCK_RotImm, 16 /* 4 */ }, 12203 { Feature_IsARM|Feature_HasV6, 1457 /* sxtab */, MCK_RotImm, 16 /* 4 */ }, 12204 { Feature_HasDSP|Feature_IsThumb2, 1463 /* sxtab16 */, MCK_RotImm, 16 /* 4 */ }, 12205 { Feature_IsARM|Feature_HasV6, 1463 /* sxtab16 */, MCK_RotImm, 16 /* 4 */ }, 12206 { Feature_HasDSP|Feature_IsThumb2, 1471 /* sxtah */, MCK_RotImm, 16 /* 4 */ }, 12207 { Feature_IsARM|Feature_HasV6, 1471 /* sxtah */, MCK_RotImm, 16 /* 4 */ }, 12208 { Feature_IsThumb2, 1477 /* sxtb */, MCK_RotImm, 8 /* 3 */ }, 12209 { Feature_IsARM|Feature_HasV6, 1477 /* sxtb */, MCK_RotImm, 8 /* 3 */ }, 12210 { Feature_IsThumb2, 1477 /* sxtb */, MCK_RotImm, 16 /* 4 */ }, 12211 { Feature_HasDSP|Feature_IsThumb2, 1482 /* sxtb16 */, MCK_RotImm, 8 /* 3 */ }, 12212 { Feature_HasDSP|Feature_IsThumb2, 1482 /* sxtb16 */, MCK_RotImm, 8 /* 3 */ }, 12213 { Feature_IsARM|Feature_HasV6, 1482 /* sxtb16 */, MCK_RotImm, 8 /* 3 */ }, 12214 { Feature_IsThumb2, 1489 /* sxth */, MCK_RotImm, 8 /* 3 */ }, 12215 { Feature_IsARM|Feature_HasV6, 1489 /* sxth */, MCK_RotImm, 8 /* 3 */ }, 12216 { Feature_IsThumb2, 1489 /* sxth */, MCK_RotImm, 16 /* 4 */ }, 12217 { Feature_IsARM, 1502 /* teq */, MCK_ModImm, 4 /* 2 */ }, 12218 { Feature_IsARM|Feature_HasV8_4a, 1511 /* tsb */, MCK_TraceSyncBarrierOpt, 1 /* 0 */ }, 12219 { Feature_IsThumb|Feature_HasV8_4a, 1511 /* tsb */, MCK_TraceSyncBarrierOpt, 2 /* 1 */ }, 12220 { Feature_IsARM, 1515 /* tst */, MCK_ModImm, 4 /* 2 */ }, 12221 { Feature_IsThumb2, 1682 /* usat */, MCK_ShifterImm, 16 /* 4 */ }, 12222 { Feature_IsARM|Feature_HasV6, 1682 /* usat */, MCK_ShifterImm, 16 /* 4 */ }, 12223 { Feature_HasDSP|Feature_IsThumb2, 1712 /* uxtab */, MCK_RotImm, 16 /* 4 */ }, 12224 { Feature_IsARM|Feature_HasV6, 1712 /* uxtab */, MCK_RotImm, 16 /* 4 */ }, 12225 { Feature_HasDSP|Feature_IsThumb2, 1718 /* uxtab16 */, MCK_RotImm, 16 /* 4 */ }, 12226 { Feature_IsARM|Feature_HasV6, 1718 /* uxtab16 */, MCK_RotImm, 16 /* 4 */ }, 12227 { Feature_HasDSP|Feature_IsThumb2, 1726 /* uxtah */, MCK_RotImm, 16 /* 4 */ }, 12228 { Feature_IsARM|Feature_HasV6, 1726 /* uxtah */, MCK_RotImm, 16 /* 4 */ }, 12229 { Feature_IsThumb2, 1732 /* uxtb */, MCK_RotImm, 8 /* 3 */ }, 12230 { Feature_IsARM|Feature_HasV6, 1732 /* uxtb */, MCK_RotImm, 8 /* 3 */ }, 12231 { Feature_IsThumb2, 1732 /* uxtb */, MCK_RotImm, 16 /* 4 */ }, 12232 { Feature_HasDSP|Feature_IsThumb2, 1737 /* uxtb16 */, MCK_RotImm, 8 /* 3 */ }, 12233 { Feature_HasDSP|Feature_IsThumb2, 1737 /* uxtb16 */, MCK_RotImm, 8 /* 3 */ }, 12234 { Feature_IsARM|Feature_HasV6, 1737 /* uxtb16 */, MCK_RotImm, 8 /* 3 */ }, 12235 { Feature_IsThumb2, 1744 /* uxth */, MCK_RotImm, 8 /* 3 */ }, 12236 { Feature_IsARM|Feature_HasV6, 1744 /* uxth */, MCK_RotImm, 8 /* 3 */ }, 12237 { Feature_IsThumb2, 1744 /* uxth */, MCK_RotImm, 16 /* 4 */ }, 12238 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12239 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12240 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12241 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ }, 12242 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12243 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ }, 12244 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12245 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12246 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12247 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12248 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ }, 12249 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12250 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ }, 12251 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12252 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12253 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12254 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12255 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12256 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12257 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12258 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12259 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ }, 12260 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12261 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ }, 12262 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12263 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12264 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12265 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12266 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12267 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12268 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12269 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ }, 12270 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ }, 12271 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12272 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12273 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ }, 12274 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ }, 12275 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12276 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12277 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12278 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12279 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12280 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12281 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12282 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12283 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ }, 12284 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ }, 12285 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12286 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12287 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ }, 12288 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ }, 12289 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12290 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12291 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12292 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12293 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12294 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12295 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12296 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12297 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12298 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12299 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12300 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12301 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12302 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListDPair, 4 /* 2 */ }, 12303 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12304 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListFourD, 4 /* 2 */ }, 12305 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ }, 12306 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDAllLanes, 4 /* 2 */ }, 12307 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12308 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneD, 4 /* 2 */ }, 12309 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ }, 12310 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ }, 12311 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12312 { Feature_HasNEON, 2024 /* vld1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12313 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12314 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ }, 12315 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ }, 12316 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12317 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ }, 12318 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ }, 12319 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ }, 12320 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12321 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ }, 12322 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ }, 12323 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12324 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ }, 12325 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ }, 12326 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ }, 12327 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12328 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ }, 12329 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ }, 12330 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12331 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ }, 12332 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ }, 12333 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12334 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12335 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ }, 12336 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ }, 12337 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ }, 12338 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ }, 12339 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12340 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12341 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ }, 12342 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ }, 12343 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ }, 12344 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ }, 12345 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ }, 12346 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ }, 12347 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12348 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12349 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ }, 12350 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ }, 12351 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ }, 12352 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ }, 12353 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12354 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12355 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ }, 12356 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ }, 12357 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ }, 12358 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ }, 12359 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ }, 12360 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ }, 12361 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12362 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairAllLanes, 4 /* 2 */ }, 12363 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ }, 12364 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPair, 4 /* 2 */ }, 12365 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ }, 12366 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpacedAllLanes, 4 /* 2 */ }, 12367 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12368 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12369 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ }, 12370 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListFourD, 4 /* 2 */ }, 12371 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ }, 12372 { Feature_HasNEON, 2029 /* vld2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ }, 12373 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ }, 12374 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12375 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ }, 12376 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ }, 12377 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12378 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ }, 12379 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ }, 12380 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12381 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ }, 12382 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ }, 12383 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12384 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ }, 12385 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ }, 12386 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12387 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ }, 12388 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ }, 12389 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12390 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ }, 12391 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ }, 12392 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12393 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12394 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ }, 12395 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ }, 12396 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ }, 12397 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ }, 12398 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12399 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12400 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ }, 12401 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ }, 12402 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ }, 12403 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ }, 12404 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12405 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12406 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ }, 12407 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ }, 12408 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ }, 12409 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ }, 12410 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12411 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12412 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ }, 12413 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ }, 12414 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ }, 12415 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDAllLanes, 4 /* 2 */ }, 12416 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12417 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12418 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ }, 12419 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ }, 12420 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ }, 12421 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQAllLanes, 4 /* 2 */ }, 12422 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12423 { Feature_HasNEON, 2034 /* vld3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12424 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ }, 12425 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ }, 12426 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ }, 12427 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ }, 12428 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12429 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ }, 12430 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ }, 12431 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ }, 12432 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ }, 12433 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ }, 12434 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12435 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ }, 12436 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ }, 12437 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ }, 12438 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ }, 12439 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ }, 12440 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12441 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ }, 12442 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ }, 12443 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ }, 12444 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ }, 12445 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ }, 12446 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ }, 12447 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ }, 12448 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ }, 12449 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12450 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12451 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ }, 12452 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ }, 12453 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ }, 12454 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ }, 12455 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ }, 12456 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ }, 12457 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ }, 12458 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ }, 12459 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ }, 12460 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ }, 12461 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12462 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12463 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ }, 12464 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ }, 12465 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ }, 12466 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDAllLanes, 4 /* 2 */ }, 12467 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ }, 12468 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourD, 4 /* 2 */ }, 12469 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ }, 12470 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ }, 12471 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ }, 12472 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQAllLanes, 4 /* 2 */ }, 12473 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12474 { Feature_HasNEON, 2039 /* vld4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12475 { Feature_HasNEON, 2121 /* vmov */, MCK_FPImm, 8 /* 3 */ }, 12476 { Feature_HasNEON, 2121 /* vmov */, MCK_FPImm, 8 /* 3 */ }, 12477 { Feature_HasVFP3, 2121 /* vmov */, MCK_FPImm, 8 /* 3 */ }, 12478 { Feature_HasVFP3|Feature_HasDPVFP, 2121 /* vmov */, MCK_FPImm, 8 /* 3 */ }, 12479 { Feature_HasFullFP16, 2121 /* vmov */, MCK_FPImm, 8 /* 3 */ }, 12480 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12481 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12482 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12483 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ }, 12484 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12485 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12486 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12487 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12488 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ }, 12489 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12490 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12491 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12492 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12493 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12494 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12495 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12496 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12497 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ }, 12498 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12499 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12500 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12501 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12502 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12503 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12504 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12505 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ }, 12506 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneDHWordIndexed, 4 /* 2 */ }, 12507 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12508 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12509 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12510 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12511 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12512 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12513 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12514 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12515 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ }, 12516 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneDWordIndexed, 4 /* 2 */ }, 12517 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12518 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12519 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12520 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12521 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12522 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12523 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12524 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12525 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12526 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12527 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12528 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListDPair, 4 /* 2 */ }, 12529 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12530 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListFourD, 4 /* 2 */ }, 12531 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12532 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneD, 4 /* 2 */ }, 12533 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ }, 12534 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListOneDByteIndexed, 4 /* 2 */ }, 12535 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12536 { Feature_HasNEON, 2621 /* vst1 */, MCK_VecListThreeD, 4 /* 2 */ }, 12537 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ }, 12538 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12539 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ }, 12540 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ }, 12541 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ }, 12542 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ }, 12543 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12544 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ }, 12545 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ }, 12546 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ }, 12547 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ }, 12548 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12549 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ }, 12550 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ }, 12551 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ }, 12552 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ }, 12553 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12554 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12555 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ }, 12556 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ }, 12557 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ }, 12558 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoDHWordIndexed, 4 /* 2 */ }, 12559 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ }, 12560 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoQHWordIndexed, 4 /* 2 */ }, 12561 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ }, 12562 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ }, 12563 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12564 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12565 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ }, 12566 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ }, 12567 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ }, 12568 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoDWordIndexed, 4 /* 2 */ }, 12569 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ }, 12570 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoQWordIndexed, 4 /* 2 */ }, 12571 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ }, 12572 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPair, 4 /* 2 */ }, 12573 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12574 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListDPairSpaced, 4 /* 2 */ }, 12575 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ }, 12576 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListFourD, 4 /* 2 */ }, 12577 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ }, 12578 { Feature_HasNEON, 2626 /* vst2 */, MCK_VecListTwoDByteIndexed, 4 /* 2 */ }, 12579 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12580 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ }, 12581 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12582 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ }, 12583 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12584 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ }, 12585 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12586 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ }, 12587 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12588 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ }, 12589 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12590 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12591 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12592 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ }, 12593 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeDHWordIndexed, 4 /* 2 */ }, 12594 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12595 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12596 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ }, 12597 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQHWordIndexed, 4 /* 2 */ }, 12598 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12599 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12600 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ }, 12601 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeDWordIndexed, 4 /* 2 */ }, 12602 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12603 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12604 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ }, 12605 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQWordIndexed, 4 /* 2 */ }, 12606 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12607 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeD, 4 /* 2 */ }, 12608 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ }, 12609 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeDByteIndexed, 4 /* 2 */ }, 12610 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12611 { Feature_HasNEON, 2631 /* vst3 */, MCK_VecListThreeQ, 4 /* 2 */ }, 12612 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ }, 12613 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ }, 12614 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12615 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ }, 12616 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ }, 12617 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ }, 12618 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12619 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ }, 12620 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ }, 12621 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ }, 12622 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12623 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ }, 12624 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ }, 12625 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ }, 12626 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourDHWordIndexed, 4 /* 2 */ }, 12627 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12628 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12629 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ }, 12630 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQHWordIndexed, 4 /* 2 */ }, 12631 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ }, 12632 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ }, 12633 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ }, 12634 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourDWordIndexed, 4 /* 2 */ }, 12635 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12636 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12637 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ }, 12638 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQWordIndexed, 4 /* 2 */ }, 12639 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ }, 12640 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourD, 4 /* 2 */ }, 12641 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ }, 12642 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourDByteIndexed, 4 /* 2 */ }, 12643 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12644 { Feature_HasNEON, 2636 /* vst4 */, MCK_VecListFourQ, 4 /* 2 */ }, 12645 { Feature_HasNEON, 2689 /* vtbl */, MCK_VecListDPair, 8 /* 3 */ }, 12646 { Feature_HasNEON, 2689 /* vtbl */, MCK_VecListFourD, 8 /* 3 */ }, 12647 { Feature_HasNEON, 2689 /* vtbl */, MCK_VecListOneD, 8 /* 3 */ }, 12648 { Feature_HasNEON, 2689 /* vtbl */, MCK_VecListThreeD, 8 /* 3 */ }, 12649 { Feature_HasNEON, 2694 /* vtbx */, MCK_VecListDPair, 8 /* 3 */ }, 12650 { Feature_HasNEON, 2694 /* vtbx */, MCK_VecListFourD, 8 /* 3 */ }, 12651 { Feature_HasNEON, 2694 /* vtbx */, MCK_VecListOneD, 8 /* 3 */ }, 12652 { Feature_HasNEON, 2694 /* vtbx */, MCK_VecListThreeD, 8 /* 3 */ }, 12653}; 12654 12655OperandMatchResultTy ARMAsmParser:: 12656tryCustomParseOperand(OperandVector &Operands, 12657 unsigned MCK) { 12658 12659 switch(MCK) { 12660 case MCK_AM3Offset: 12661 return parseAM3Offset(Operands); 12662 case MCK_BankedReg: 12663 return parseBankedRegOperand(Operands); 12664 case MCK_Bitfield: 12665 return parseBitfield(Operands); 12666 case MCK_CoprocNum: 12667 return parseCoprocNumOperand(Operands); 12668 case MCK_CoprocOption: 12669 return parseCoprocOptionOperand(Operands); 12670 case MCK_CoprocReg: 12671 return parseCoprocRegOperand(Operands); 12672 case MCK_FPImm: 12673 return parseFPImm(Operands); 12674 case MCK_InstSyncBarrierOpt: 12675 return parseInstSyncBarrierOptOperand(Operands); 12676 case MCK_MSRMask: 12677 return parseMSRMaskOperand(Operands); 12678 case MCK_MemBarrierOpt: 12679 return parseMemBarrierOptOperand(Operands); 12680 case MCK_ModImm: 12681 return parseModImm(Operands); 12682 case MCK_PKHASRImm: 12683 return parsePKHASRImm(Operands); 12684 case MCK_PKHLSLImm: 12685 return parsePKHLSLImm(Operands); 12686 case MCK_PostIdxReg: 12687 return parsePostIdxReg(Operands); 12688 case MCK_PostIdxRegShifted: 12689 return parsePostIdxReg(Operands); 12690 case MCK_ProcIFlags: 12691 return parseProcIFlagsOperand(Operands); 12692 case MCK_RotImm: 12693 return parseRotImm(Operands); 12694 case MCK_SetEndImm: 12695 return parseSetEndImm(Operands); 12696 case MCK_ShifterImm: 12697 return parseShifterImm(Operands); 12698 case MCK_TraceSyncBarrierOpt: 12699 return parseTraceSyncBarrierOptOperand(Operands); 12700 case MCK_VecListDPairAllLanes: 12701 return parseVectorList(Operands); 12702 case MCK_VecListDPair: 12703 return parseVectorList(Operands); 12704 case MCK_VecListDPairSpacedAllLanes: 12705 return parseVectorList(Operands); 12706 case MCK_VecListDPairSpaced: 12707 return parseVectorList(Operands); 12708 case MCK_VecListFourDAllLanes: 12709 return parseVectorList(Operands); 12710 case MCK_VecListFourD: 12711 return parseVectorList(Operands); 12712 case MCK_VecListFourDByteIndexed: 12713 return parseVectorList(Operands); 12714 case MCK_VecListFourDHWordIndexed: 12715 return parseVectorList(Operands); 12716 case MCK_VecListFourDWordIndexed: 12717 return parseVectorList(Operands); 12718 case MCK_VecListFourQAllLanes: 12719 return parseVectorList(Operands); 12720 case MCK_VecListFourQ: 12721 return parseVectorList(Operands); 12722 case MCK_VecListFourQHWordIndexed: 12723 return parseVectorList(Operands); 12724 case MCK_VecListFourQWordIndexed: 12725 return parseVectorList(Operands); 12726 case MCK_VecListOneDAllLanes: 12727 return parseVectorList(Operands); 12728 case MCK_VecListOneD: 12729 return parseVectorList(Operands); 12730 case MCK_VecListOneDByteIndexed: 12731 return parseVectorList(Operands); 12732 case MCK_VecListOneDHWordIndexed: 12733 return parseVectorList(Operands); 12734 case MCK_VecListOneDWordIndexed: 12735 return parseVectorList(Operands); 12736 case MCK_VecListThreeDAllLanes: 12737 return parseVectorList(Operands); 12738 case MCK_VecListThreeD: 12739 return parseVectorList(Operands); 12740 case MCK_VecListThreeDByteIndexed: 12741 return parseVectorList(Operands); 12742 case MCK_VecListThreeDHWordIndexed: 12743 return parseVectorList(Operands); 12744 case MCK_VecListThreeDWordIndexed: 12745 return parseVectorList(Operands); 12746 case MCK_VecListThreeQAllLanes: 12747 return parseVectorList(Operands); 12748 case MCK_VecListThreeQ: 12749 return parseVectorList(Operands); 12750 case MCK_VecListThreeQHWordIndexed: 12751 return parseVectorList(Operands); 12752 case MCK_VecListThreeQWordIndexed: 12753 return parseVectorList(Operands); 12754 case MCK_VecListTwoDByteIndexed: 12755 return parseVectorList(Operands); 12756 case MCK_VecListTwoDHWordIndexed: 12757 return parseVectorList(Operands); 12758 case MCK_VecListTwoDWordIndexed: 12759 return parseVectorList(Operands); 12760 case MCK_VecListTwoQHWordIndexed: 12761 return parseVectorList(Operands); 12762 case MCK_VecListTwoQWordIndexed: 12763 return parseVectorList(Operands); 12764 case MCK_ITCondCode: 12765 return parseITCondCode(Operands); 12766 default: 12767 return MatchOperand_NoMatch; 12768 } 12769 return MatchOperand_NoMatch; 12770} 12771 12772OperandMatchResultTy ARMAsmParser:: 12773MatchOperandParserImpl(OperandVector &Operands, 12774 StringRef Mnemonic, 12775 bool ParseForAllFeatures) { 12776 // Get the current feature set. 12777 uint64_t AvailableFeatures = getAvailableFeatures(); 12778 12779 // Get the next operand index. 12780 unsigned NextOpNum = Operands.size() - 1; 12781 // Search the table. 12782 auto MnemonicRange = 12783 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), 12784 Mnemonic, LessOpcodeOperand()); 12785 12786 if (MnemonicRange.first == MnemonicRange.second) 12787 return MatchOperand_NoMatch; 12788 12789 for (const OperandMatchEntry *it = MnemonicRange.first, 12790 *ie = MnemonicRange.second; it != ie; ++it) { 12791 // equal_range guarantees that instruction mnemonic matches. 12792 assert(Mnemonic == it->getMnemonic()); 12793 12794 // check if the available features match 12795 if (!ParseForAllFeatures && (AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) 12796 continue; 12797 12798 // check if the operand in question has a custom parser. 12799 if (!(it->OperandMask & (1 << NextOpNum))) 12800 continue; 12801 12802 // call custom parse method to handle the operand 12803 OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class); 12804 if (Result != MatchOperand_NoMatch) 12805 return Result; 12806 } 12807 12808 // Okay, we had no match. 12809 return MatchOperand_NoMatch; 12810} 12811 12812#endif // GET_MATCHER_IMPLEMENTATION 12813 12814 12815#ifdef GET_MNEMONIC_SPELL_CHECKER 12816#undef GET_MNEMONIC_SPELL_CHECKER 12817 12818static std::string ARMMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) { 12819 const unsigned MaxEditDist = 2; 12820 std::vector<StringRef> Candidates; 12821 StringRef Prev = ""; 12822 12823 // Find the appropriate table for this asm variant. 12824 const MatchEntry *Start, *End; 12825 switch (VariantID) { 12826 default: llvm_unreachable("invalid variant!"); 12827 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 12828 } 12829 12830 for (auto I = Start; I < End; I++) { 12831 // Ignore unsupported instructions. 12832 if ((FBS & I->RequiredFeatures) != I->RequiredFeatures) 12833 continue; 12834 12835 StringRef T = I->getMnemonic(); 12836 // Avoid recomputing the edit distance for the same string. 12837 if (T.equals(Prev)) 12838 continue; 12839 12840 Prev = T; 12841 unsigned Dist = S.edit_distance(T, false, MaxEditDist); 12842 if (Dist <= MaxEditDist) 12843 Candidates.push_back(T); 12844 } 12845 12846 if (Candidates.empty()) 12847 return ""; 12848 12849 std::string Res = ", did you mean: "; 12850 unsigned i = 0; 12851 for( ; i < Candidates.size() - 1; i++) 12852 Res += Candidates[i].str() + ", "; 12853 return Res + Candidates[i].str() + "?"; 12854} 12855 12856#endif // GET_MNEMONIC_SPELL_CHECKER 12857 12858