1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Global Instruction Selector for the ARM target                             *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 64;
11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15  mutable MatcherState State;
16  typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17  typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
18  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
19  static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20  static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
21  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24  const int64_t *getMatchTable() const override;
25  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
27
28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
29, State(0),
30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32
33#ifdef GET_GLOBALISEL_IMPL
34// Bits for subtarget features that participate in instruction matching.
35enum SubtargetFeatureBits : uint8_t {
36  Feature_NoHonorSignDependentRoundingBit = 57,
37  Feature_HasV4TBit = 6,
38  Feature_NoV4TBit = 7,
39  Feature_HasV5TBit = 8,
40  Feature_HasV5TEBit = 12,
41  Feature_HasV6Bit = 0,
42  Feature_NoV6Bit = 10,
43  Feature_HasV6MBit = 29,
44  Feature_HasV8MBaselineBit = 33,
45  Feature_HasV6T2Bit = 9,
46  Feature_HasV6KBit = 19,
47  Feature_HasV7Bit = 3,
48  Feature_HasV8Bit = 15,
49  Feature_PreV8Bit = 20,
50  Feature_HasV8_1aBit = 59,
51  Feature_NoVFPBit = 23,
52  Feature_HasVFP2Bit = 22,
53  Feature_HasVFP3Bit = 47,
54  Feature_HasVFP4Bit = 45,
55  Feature_HasDPVFPBit = 39,
56  Feature_HasFPARMv8Bit = 41,
57  Feature_HasNEONBit = 48,
58  Feature_HasCryptoBit = 49,
59  Feature_HasDotProdBit = 50,
60  Feature_HasCRCBit = 14,
61  Feature_HasFP16Bit = 54,
62  Feature_HasFullFP16Bit = 38,
63  Feature_HasDivideInThumbBit = 35,
64  Feature_HasDivideInARMBit = 13,
65  Feature_HasDSPBit = 34,
66  Feature_HasDBBit = 16,
67  Feature_HasV7ClrexBit = 18,
68  Feature_HasAcquireReleaseBit = 17,
69  Feature_HasMPBit = 2,
70  Feature_HasZCZBit = 51,
71  Feature_UseNEONForFPBit = 62,
72  Feature_DontUseNEONForFPBit = 40,
73  Feature_IsThumbBit = 27,
74  Feature_IsThumb1OnlyBit = 28,
75  Feature_IsThumb2Bit = 32,
76  Feature_IsNotMClassBit = 36,
77  Feature_IsARMBit = 1,
78  Feature_IsWindowsBit = 30,
79  Feature_IsNotWindowsBit = 31,
80  Feature_IsReadTPHardBit = 55,
81  Feature_IsReadTPSoftBit = 21,
82  Feature_UseNaClTrapBit = 4,
83  Feature_DontUseNaClTrapBit = 5,
84  Feature_UseMovtBit = 37,
85  Feature_DontUseMovtBit = 24,
86  Feature_UseMovtInPicBit = 25,
87  Feature_DontUseMovtInPicBit = 26,
88  Feature_UseFPVMLxBit = 44,
89  Feature_UseMulOpsBit = 11,
90  Feature_UseFusedMACBit = 46,
91  Feature_DontUseFusedMACBit = 43,
92  Feature_HasFastVGETLNi32Bit = 52,
93  Feature_HasSlowVGETLNi32Bit = 60,
94  Feature_HasFastVDUP32Bit = 53,
95  Feature_HasSlowVDUP32Bit = 61,
96  Feature_UseVMOVSRBit = 42,
97  Feature_DontUseVMOVSRBit = 63,
98  Feature_IsLEBit = 56,
99  Feature_IsBEBit = 58,
100};
101
102PredicateBitset ARMInstructionSelector::
103computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
104  PredicateBitset Features;
105  if (!TM.Options.HonorSignDependentRoundingFPMath())
106    Features[Feature_NoHonorSignDependentRoundingBit] = 1;
107  if (Subtarget->hasV4TOps())
108    Features[Feature_HasV4TBit] = 1;
109  if (!Subtarget->hasV4TOps())
110    Features[Feature_NoV4TBit] = 1;
111  if (Subtarget->hasV5TOps())
112    Features[Feature_HasV5TBit] = 1;
113  if (Subtarget->hasV5TEOps())
114    Features[Feature_HasV5TEBit] = 1;
115  if (Subtarget->hasV6Ops())
116    Features[Feature_HasV6Bit] = 1;
117  if (!Subtarget->hasV6Ops())
118    Features[Feature_NoV6Bit] = 1;
119  if (Subtarget->hasV6MOps())
120    Features[Feature_HasV6MBit] = 1;
121  if (Subtarget->hasV8MBaselineOps())
122    Features[Feature_HasV8MBaselineBit] = 1;
123  if (Subtarget->hasV6T2Ops())
124    Features[Feature_HasV6T2Bit] = 1;
125  if (Subtarget->hasV6KOps())
126    Features[Feature_HasV6KBit] = 1;
127  if (Subtarget->hasV7Ops())
128    Features[Feature_HasV7Bit] = 1;
129  if (Subtarget->hasV8Ops())
130    Features[Feature_HasV8Bit] = 1;
131  if (!Subtarget->hasV8Ops())
132    Features[Feature_PreV8Bit] = 1;
133  if (Subtarget->hasV8_1aOps())
134    Features[Feature_HasV8_1aBit] = 1;
135  if (!Subtarget->hasVFP2())
136    Features[Feature_NoVFPBit] = 1;
137  if (Subtarget->hasVFP2())
138    Features[Feature_HasVFP2Bit] = 1;
139  if (Subtarget->hasVFP3())
140    Features[Feature_HasVFP3Bit] = 1;
141  if (Subtarget->hasVFP4())
142    Features[Feature_HasVFP4Bit] = 1;
143  if (!Subtarget->isFPOnlySP())
144    Features[Feature_HasDPVFPBit] = 1;
145  if (Subtarget->hasFPARMv8())
146    Features[Feature_HasFPARMv8Bit] = 1;
147  if (Subtarget->hasNEON())
148    Features[Feature_HasNEONBit] = 1;
149  if (Subtarget->hasCrypto())
150    Features[Feature_HasCryptoBit] = 1;
151  if (Subtarget->hasDotProd())
152    Features[Feature_HasDotProdBit] = 1;
153  if (Subtarget->hasCRC())
154    Features[Feature_HasCRCBit] = 1;
155  if (Subtarget->hasFP16())
156    Features[Feature_HasFP16Bit] = 1;
157  if (Subtarget->hasFullFP16())
158    Features[Feature_HasFullFP16Bit] = 1;
159  if (Subtarget->hasDivideInThumbMode())
160    Features[Feature_HasDivideInThumbBit] = 1;
161  if (Subtarget->hasDivideInARMMode())
162    Features[Feature_HasDivideInARMBit] = 1;
163  if (Subtarget->hasDSP())
164    Features[Feature_HasDSPBit] = 1;
165  if (Subtarget->hasDataBarrier())
166    Features[Feature_HasDBBit] = 1;
167  if (Subtarget->hasV7Clrex())
168    Features[Feature_HasV7ClrexBit] = 1;
169  if (Subtarget->hasAcquireRelease())
170    Features[Feature_HasAcquireReleaseBit] = 1;
171  if (Subtarget->hasMPExtension())
172    Features[Feature_HasMPBit] = 1;
173  if (Subtarget->hasZeroCycleZeroing())
174    Features[Feature_HasZCZBit] = 1;
175  if (Subtarget->useNEONForSinglePrecisionFP())
176    Features[Feature_UseNEONForFPBit] = 1;
177  if (!Subtarget->useNEONForSinglePrecisionFP())
178    Features[Feature_DontUseNEONForFPBit] = 1;
179  if (Subtarget->isThumb())
180    Features[Feature_IsThumbBit] = 1;
181  if (Subtarget->isThumb1Only())
182    Features[Feature_IsThumb1OnlyBit] = 1;
183  if (Subtarget->isThumb2())
184    Features[Feature_IsThumb2Bit] = 1;
185  if (!Subtarget->isMClass())
186    Features[Feature_IsNotMClassBit] = 1;
187  if (!Subtarget->isThumb())
188    Features[Feature_IsARMBit] = 1;
189  if (Subtarget->isTargetWindows())
190    Features[Feature_IsWindowsBit] = 1;
191  if (!Subtarget->isTargetWindows())
192    Features[Feature_IsNotWindowsBit] = 1;
193  if (Subtarget->isReadTPHard())
194    Features[Feature_IsReadTPHardBit] = 1;
195  if (!Subtarget->isReadTPHard())
196    Features[Feature_IsReadTPSoftBit] = 1;
197  if (Subtarget->useNaClTrap())
198    Features[Feature_UseNaClTrapBit] = 1;
199  if (!Subtarget->useNaClTrap())
200    Features[Feature_DontUseNaClTrapBit] = 1;
201  if (Subtarget->useFPVMLx())
202    Features[Feature_UseFPVMLxBit] = 1;
203  if (Subtarget->useMulOps())
204    Features[Feature_UseMulOpsBit] = 1;
205  if ((TM.Options.AllowFPOpFusion == FPOpFusion::Fast &&  Subtarget->hasVFP4()) && !Subtarget->isTargetDarwin())
206    Features[Feature_UseFusedMACBit] = 1;
207  if (!(TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->hasVFP4()) || Subtarget->isTargetDarwin())
208    Features[Feature_DontUseFusedMACBit] = 1;
209  if (!Subtarget->hasSlowVGETLNi32())
210    Features[Feature_HasFastVGETLNi32Bit] = 1;
211  if (Subtarget->hasSlowVGETLNi32())
212    Features[Feature_HasSlowVGETLNi32Bit] = 1;
213  if (!Subtarget->hasSlowVDUP32())
214    Features[Feature_HasFastVDUP32Bit] = 1;
215  if (Subtarget->hasSlowVDUP32())
216    Features[Feature_HasSlowVDUP32Bit] = 1;
217  if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
218    Features[Feature_UseVMOVSRBit] = 1;
219  if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
220    Features[Feature_DontUseVMOVSRBit] = 1;
221  return Features;
222}
223
224PredicateBitset ARMInstructionSelector::
225computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
226  PredicateBitset Features;
227  if (Subtarget->useMovt(*MF))
228    Features[Feature_UseMovtBit] = 1;
229  if (!Subtarget->useMovt(*MF))
230    Features[Feature_DontUseMovtBit] = 1;
231  if (Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt())
232    Features[Feature_UseMovtInPicBit] = 1;
233  if (!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt())
234    Features[Feature_DontUseMovtInPicBit] = 1;
235  if (MF->getDataLayout().isLittleEndian())
236    Features[Feature_IsLEBit] = 1;
237  if (MF->getDataLayout().isBigEndian())
238    Features[Feature_IsBEBit] = 1;
239  return Features;
240}
241
242// LLT Objects.
243enum {
244  GILLT_s16,
245  GILLT_s32,
246  GILLT_s64,
247  GILLT_v2s32,
248  GILLT_v2s64,
249  GILLT_v4s16,
250  GILLT_v4s32,
251  GILLT_v8s8,
252  GILLT_v8s16,
253  GILLT_v16s8,
254};
255const static size_t NumTypeObjects = 10;
256const static LLT TypeObjects[] = {
257  LLT::scalar(16),
258  LLT::scalar(32),
259  LLT::scalar(64),
260  LLT::vector(2, 32),
261  LLT::vector(2, 64),
262  LLT::vector(4, 16),
263  LLT::vector(4, 32),
264  LLT::vector(8, 8),
265  LLT::vector(8, 16),
266  LLT::vector(16, 8),
267};
268
269// Feature bitsets.
270enum {
271  GIFBS_Invalid,
272  GIFBS_HasDotProd,
273  GIFBS_HasFPARMv8,
274  GIFBS_HasFullFP16,
275  GIFBS_HasNEON,
276  GIFBS_HasVFP2,
277  GIFBS_HasVFP4,
278  GIFBS_IsARM,
279  GIFBS_IsBE,
280  GIFBS_IsLE,
281  GIFBS_IsThumb,
282  GIFBS_IsThumb2,
283  GIFBS_NoHonorSignDependentRounding,
284  GIFBS_DontUseNEONForFP_HasVFP2,
285  GIFBS_HasCrypto_HasV8,
286  GIFBS_HasDB_IsARM,
287  GIFBS_HasDB_IsThumb,
288  GIFBS_HasDPVFP_HasFPARMv8,
289  GIFBS_HasDPVFP_HasVFP2,
290  GIFBS_HasDPVFP_HasVFP4,
291  GIFBS_HasDPVFP_NoHonorSignDependentRounding,
292  GIFBS_HasDSP_IsThumb2,
293  GIFBS_HasDivideInARM_IsARM,
294  GIFBS_HasFP16_HasNEON,
295  GIFBS_HasFullFP16_HasNEON,
296  GIFBS_HasNEON_HasV8,
297  GIFBS_HasNEON_HasV8_1a,
298  GIFBS_HasV5T_IsARM,
299  GIFBS_HasV5TE_IsARM,
300  GIFBS_HasV6_IsARM,
301  GIFBS_HasV6K_IsARM,
302  GIFBS_HasV6M_IsThumb,
303  GIFBS_HasV6T2_IsARM,
304  GIFBS_HasV6T2_IsThumb2,
305  GIFBS_HasV7_IsARM,
306  GIFBS_HasV7Clrex_IsThumb,
307  GIFBS_HasV8MBaseline_IsThumb,
308  GIFBS_HasVFP2_UseVMOVSR,
309  GIFBS_IsARM_NoV6,
310  GIFBS_IsARM_PreV8,
311  GIFBS_IsThumb_IsThumb1Only,
312  GIFBS_IsThumb_IsWindows,
313  GIFBS_IsThumb_UseMovt,
314  GIFBS_IsThumb2_PreV8,
315  GIFBS_IsThumb2_UseMulOps,
316  GIFBS_HasCRC_HasV8_IsARM,
317  GIFBS_HasCRC_HasV8_IsThumb2,
318  GIFBS_HasDSP_IsThumb2_UseMulOps,
319  GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
320  GIFBS_HasFullFP16_HasNEON_HasV8,
321  GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
322  GIFBS_HasV5TE_IsARM_UseMulOps,
323  GIFBS_HasV6_IsARM_UseMulOps,
324  GIFBS_HasV6_IsThumb_IsThumb1Only,
325  GIFBS_HasV6T2_IsARM_UseMulOps,
326  GIFBS_IsARM_NoV6_UseMulOps,
327  GIFBS_DontUseFusedMAC_HasFullFP16_HasNEON_UseFPVMLx,
328};
329const static PredicateBitset FeatureBitsets[] {
330  {}, // GIFBS_Invalid
331  {Feature_HasDotProdBit, },
332  {Feature_HasFPARMv8Bit, },
333  {Feature_HasFullFP16Bit, },
334  {Feature_HasNEONBit, },
335  {Feature_HasVFP2Bit, },
336  {Feature_HasVFP4Bit, },
337  {Feature_IsARMBit, },
338  {Feature_IsBEBit, },
339  {Feature_IsLEBit, },
340  {Feature_IsThumbBit, },
341  {Feature_IsThumb2Bit, },
342  {Feature_NoHonorSignDependentRoundingBit, },
343  {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
344  {Feature_HasCryptoBit, Feature_HasV8Bit, },
345  {Feature_HasDBBit, Feature_IsARMBit, },
346  {Feature_HasDBBit, Feature_IsThumbBit, },
347  {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
348  {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
349  {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
350  {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
351  {Feature_HasDSPBit, Feature_IsThumb2Bit, },
352  {Feature_HasDivideInARMBit, Feature_IsARMBit, },
353  {Feature_HasFP16Bit, Feature_HasNEONBit, },
354  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
355  {Feature_HasNEONBit, Feature_HasV8Bit, },
356  {Feature_HasNEONBit, Feature_HasV8_1aBit, },
357  {Feature_HasV5TBit, Feature_IsARMBit, },
358  {Feature_HasV5TEBit, Feature_IsARMBit, },
359  {Feature_HasV6Bit, Feature_IsARMBit, },
360  {Feature_HasV6KBit, Feature_IsARMBit, },
361  {Feature_HasV6MBit, Feature_IsThumbBit, },
362  {Feature_HasV6T2Bit, Feature_IsARMBit, },
363  {Feature_HasV6T2Bit, Feature_IsThumb2Bit, },
364  {Feature_HasV7Bit, Feature_IsARMBit, },
365  {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
366  {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
367  {Feature_HasVFP2Bit, Feature_UseVMOVSRBit, },
368  {Feature_IsARMBit, Feature_NoV6Bit, },
369  {Feature_IsARMBit, Feature_PreV8Bit, },
370  {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
371  {Feature_IsThumbBit, Feature_IsWindowsBit, },
372  {Feature_IsThumbBit, Feature_UseMovtBit, },
373  {Feature_IsThumb2Bit, Feature_PreV8Bit, },
374  {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
375  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsARMBit, },
376  {Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsThumb2Bit, },
377  {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
378  {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
379  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
380  {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
381  {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
382  {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
383  {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
384  {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
385  {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
386  {Feature_DontUseFusedMACBit, Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
387};
388
389// ComplexPattern predicates.
390enum {
391  GICP_Invalid,
392};
393// See constructor for table contents
394
395// PatFrag predicates.
396enum {
397  GIPFP_I64_Predicate_VectorIndex16 = GIPFP_I64_Invalid + 1,
398  GIPFP_I64_Predicate_VectorIndex32,
399  GIPFP_I64_Predicate_VectorIndex64,
400  GIPFP_I64_Predicate_VectorIndex8,
401  GIPFP_I64_Predicate_imm0_15,
402  GIPFP_I64_Predicate_imm0_239,
403  GIPFP_I64_Predicate_imm0_255,
404  GIPFP_I64_Predicate_imm0_31,
405  GIPFP_I64_Predicate_imm0_32,
406  GIPFP_I64_Predicate_imm0_4095,
407  GIPFP_I64_Predicate_imm0_63,
408  GIPFP_I64_Predicate_imm0_65535,
409  GIPFP_I64_Predicate_imm0_65535_neg,
410  GIPFP_I64_Predicate_imm0_7,
411  GIPFP_I64_Predicate_imm16,
412  GIPFP_I64_Predicate_imm16_31,
413  GIPFP_I64_Predicate_imm1_15,
414  GIPFP_I64_Predicate_imm1_16,
415  GIPFP_I64_Predicate_imm1_31,
416  GIPFP_I64_Predicate_imm1_7,
417  GIPFP_I64_Predicate_imm24b,
418  GIPFP_I64_Predicate_imm256_510,
419  GIPFP_I64_Predicate_imm32,
420  GIPFP_I64_Predicate_imm8,
421  GIPFP_I64_Predicate_imm8_255,
422  GIPFP_I64_Predicate_imm8_or_16,
423  GIPFP_I64_Predicate_mod_imm,
424  GIPFP_I64_Predicate_pkh_asr_amt,
425  GIPFP_I64_Predicate_pkh_lsl_amt,
426  GIPFP_I64_Predicate_shr_imm16,
427  GIPFP_I64_Predicate_shr_imm32,
428  GIPFP_I64_Predicate_shr_imm64,
429  GIPFP_I64_Predicate_shr_imm8,
430  GIPFP_I64_Predicate_t2_so_imm,
431  GIPFP_I64_Predicate_t2_so_imm_neg,
432};
433bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
434  switch (PredicateID) {
435  case GIPFP_I64_Predicate_VectorIndex16: {
436
437  return ((uint64_t)Imm) < 4;
438
439    llvm_unreachable("ImmediateCode should have returned");
440    return false;
441  }
442  case GIPFP_I64_Predicate_VectorIndex32: {
443
444  return ((uint64_t)Imm) < 2;
445
446    llvm_unreachable("ImmediateCode should have returned");
447    return false;
448  }
449  case GIPFP_I64_Predicate_VectorIndex64: {
450
451  return ((uint64_t)Imm) < 1;
452
453    llvm_unreachable("ImmediateCode should have returned");
454    return false;
455  }
456  case GIPFP_I64_Predicate_VectorIndex8: {
457
458  return ((uint64_t)Imm) < 8;
459
460    llvm_unreachable("ImmediateCode should have returned");
461    return false;
462  }
463  case GIPFP_I64_Predicate_imm0_15: {
464
465  return Imm >= 0 && Imm < 16;
466
467    llvm_unreachable("ImmediateCode should have returned");
468    return false;
469  }
470  case GIPFP_I64_Predicate_imm0_239: {
471     return Imm >= 0 && Imm < 240;
472    llvm_unreachable("ImmediateCode should have returned");
473    return false;
474  }
475  case GIPFP_I64_Predicate_imm0_255: {
476     return Imm >= 0 && Imm < 256;
477    llvm_unreachable("ImmediateCode should have returned");
478    return false;
479  }
480  case GIPFP_I64_Predicate_imm0_31: {
481
482  return Imm >= 0 && Imm < 32;
483
484    llvm_unreachable("ImmediateCode should have returned");
485    return false;
486  }
487  case GIPFP_I64_Predicate_imm0_32: {
488
489  return Imm >= 0 && Imm < 33;
490
491    llvm_unreachable("ImmediateCode should have returned");
492    return false;
493  }
494  case GIPFP_I64_Predicate_imm0_4095: {
495
496  return Imm >= 0 && Imm < 4096;
497
498    llvm_unreachable("ImmediateCode should have returned");
499    return false;
500  }
501  case GIPFP_I64_Predicate_imm0_63: {
502
503  return Imm >= 0 && Imm < 64;
504
505    llvm_unreachable("ImmediateCode should have returned");
506    return false;
507  }
508  case GIPFP_I64_Predicate_imm0_65535: {
509
510  return Imm >= 0 && Imm < 65536;
511
512    llvm_unreachable("ImmediateCode should have returned");
513    return false;
514  }
515  case GIPFP_I64_Predicate_imm0_65535_neg: {
516
517  return -Imm >= 0 && -Imm < 65536;
518
519    llvm_unreachable("ImmediateCode should have returned");
520    return false;
521  }
522  case GIPFP_I64_Predicate_imm0_7: {
523
524  return Imm >= 0 && Imm < 8;
525
526    llvm_unreachable("ImmediateCode should have returned");
527    return false;
528  }
529  case GIPFP_I64_Predicate_imm16: {
530     return Imm == 16;
531    llvm_unreachable("ImmediateCode should have returned");
532    return false;
533  }
534  case GIPFP_I64_Predicate_imm16_31: {
535
536  return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
537
538    llvm_unreachable("ImmediateCode should have returned");
539    return false;
540  }
541  case GIPFP_I64_Predicate_imm1_15: {
542     return Imm > 0 && Imm < 16;
543    llvm_unreachable("ImmediateCode should have returned");
544    return false;
545  }
546  case GIPFP_I64_Predicate_imm1_16: {
547
548    return Imm > 0 && Imm <= 16;
549
550    llvm_unreachable("ImmediateCode should have returned");
551    return false;
552  }
553  case GIPFP_I64_Predicate_imm1_31: {
554     return Imm > 0 && Imm < 32;
555    llvm_unreachable("ImmediateCode should have returned");
556    return false;
557  }
558  case GIPFP_I64_Predicate_imm1_7: {
559     return Imm > 0 && Imm < 8;
560    llvm_unreachable("ImmediateCode should have returned");
561    return false;
562  }
563  case GIPFP_I64_Predicate_imm24b: {
564
565  return Imm >= 0 && Imm <= 0xffffff;
566
567    llvm_unreachable("ImmediateCode should have returned");
568    return false;
569  }
570  case GIPFP_I64_Predicate_imm256_510: {
571
572  return Imm >= 256 && Imm < 511;
573
574    llvm_unreachable("ImmediateCode should have returned");
575    return false;
576  }
577  case GIPFP_I64_Predicate_imm32: {
578     return Imm == 32;
579    llvm_unreachable("ImmediateCode should have returned");
580    return false;
581  }
582  case GIPFP_I64_Predicate_imm8: {
583     return Imm == 8;
584    llvm_unreachable("ImmediateCode should have returned");
585    return false;
586  }
587  case GIPFP_I64_Predicate_imm8_255: {
588
589  return Imm >= 8 && Imm < 256;
590
591    llvm_unreachable("ImmediateCode should have returned");
592    return false;
593  }
594  case GIPFP_I64_Predicate_imm8_or_16: {
595     return Imm == 8 || Imm == 16;
596    llvm_unreachable("ImmediateCode should have returned");
597    return false;
598  }
599  case GIPFP_I64_Predicate_mod_imm: {
600
601    return ARM_AM::getSOImmVal(Imm) != -1;
602
603    llvm_unreachable("ImmediateCode should have returned");
604    return false;
605  }
606  case GIPFP_I64_Predicate_pkh_asr_amt: {
607     return Imm > 0 && Imm <= 32;
608    llvm_unreachable("ImmediateCode should have returned");
609    return false;
610  }
611  case GIPFP_I64_Predicate_pkh_lsl_amt: {
612     return Imm >= 0 && Imm < 32;
613    llvm_unreachable("ImmediateCode should have returned");
614    return false;
615  }
616  case GIPFP_I64_Predicate_shr_imm16: {
617     return Imm > 0 && Imm <= 16;
618    llvm_unreachable("ImmediateCode should have returned");
619    return false;
620  }
621  case GIPFP_I64_Predicate_shr_imm32: {
622     return Imm > 0 && Imm <= 32;
623    llvm_unreachable("ImmediateCode should have returned");
624    return false;
625  }
626  case GIPFP_I64_Predicate_shr_imm64: {
627     return Imm > 0 && Imm <= 64;
628    llvm_unreachable("ImmediateCode should have returned");
629    return false;
630  }
631  case GIPFP_I64_Predicate_shr_imm8: {
632     return Imm > 0 && Imm <= 8;
633    llvm_unreachable("ImmediateCode should have returned");
634    return false;
635  }
636  case GIPFP_I64_Predicate_t2_so_imm: {
637
638    return ARM_AM::getT2SOImmVal(Imm) != -1;
639
640    llvm_unreachable("ImmediateCode should have returned");
641    return false;
642  }
643  case GIPFP_I64_Predicate_t2_so_imm_neg: {
644
645  return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
646
647    llvm_unreachable("ImmediateCode should have returned");
648    return false;
649  }
650  }
651  llvm_unreachable("Unknown predicate");
652  return false;
653}
654bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
655  llvm_unreachable("Unknown predicate");
656  return false;
657}
658bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
659  llvm_unreachable("Unknown predicate");
660  return false;
661}
662// PatFrag predicates.
663enum {
664  GIPFP_MI_Predicate_bf_inv_mask_imm = GIPFP_MI_Invalid + 1,
665};
666bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
667  const MachineFunction &MF = *MI.getParent()->getParent();
668  const MachineRegisterInfo &MRI = MF.getRegInfo();
669  (void)MRI;
670  switch (PredicateID) {
671  case GIPFP_MI_Predicate_bf_inv_mask_imm: {
672
673    // There's better methods of implementing this check. IntImmLeaf<> would be
674    // equivalent and have less boilerplate but we need a test for C++
675    // predicates and this one causes new rules to be imported into GlobalISel
676    // without requiring additional features first.
677    const auto &MO = MI.getOperand(1);
678    if (!MO.isCImm())
679      return false;
680    return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
681
682    llvm_unreachable("GISelPredicateCode should have returned");
683    return false;
684  }
685  }
686  llvm_unreachable("Unknown predicate");
687  return false;
688}
689
690ARMInstructionSelector::ComplexMatcherMemFn
691ARMInstructionSelector::ComplexPredicateFns[] = {
692  nullptr, // GICP_Invalid
693};
694
695// Custom renderers.
696enum {
697  GICR_Invalid,
698};
699ARMInstructionSelector::CustomRendererFn
700ARMInstructionSelector::CustomRenderers[] = {
701  nullptr, // GICP_Invalid
702};
703
704bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
705  MachineFunction &MF = *I.getParent()->getParent();
706  MachineRegisterInfo &MRI = MF.getRegInfo();
707  // FIXME: This should be computed on a per-function basis rather than per-insn.
708  AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
709  const PredicateBitset AvailableFeatures = getAvailableFeatures();
710  NewMIVector OutMIs;
711  State.MIs.clear();
712  State.MIs.push_back(&I);
713
714  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
715    return true;
716  }
717
718  return false;
719}
720
721const int64_t *ARMInstructionSelector::getMatchTable() const {
722  constexpr static int64_t MatchTable0[] = {
723    GIM_SwitchOpcode, /*MI*/0, /*[*/34, 124, /*)*//*default:*//*Label 33*/ 61035,
724    /*TargetOpcode::G_ADD*//*Label 0*/ 95,
725    /*TargetOpcode::G_SUB*//*Label 1*/ 6646,
726    /*TargetOpcode::G_MUL*//*Label 2*/ 8636,
727    /*TargetOpcode::G_SDIV*//*Label 3*/ 9270,
728    /*TargetOpcode::G_UDIV*//*Label 4*/ 9370, 0, 0,
729    /*TargetOpcode::G_AND*//*Label 5*/ 9470,
730    /*TargetOpcode::G_OR*//*Label 6*/ 11183,
731    /*TargetOpcode::G_XOR*//*Label 7*/ 15366, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
732    /*TargetOpcode::G_BITCAST*//*Label 8*/ 15865, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
733    /*TargetOpcode::G_INTRINSIC*//*Label 9*/ 20253,
734    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 10*/ 49624,
735    /*TargetOpcode::G_ANYEXT*//*Label 11*/ 53953,
736    /*TargetOpcode::G_TRUNC*//*Label 12*/ 54076,
737    /*TargetOpcode::G_CONSTANT*//*Label 13*/ 54205, 0, 0, 0,
738    /*TargetOpcode::G_SEXT*//*Label 14*/ 54370,
739    /*TargetOpcode::G_ZEXT*//*Label 15*/ 54499,
740    /*TargetOpcode::G_SHL*//*Label 16*/ 55009,
741    /*TargetOpcode::G_LSHR*//*Label 17*/ 55114,
742    /*TargetOpcode::G_ASHR*//*Label 18*/ 55172, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
743    /*TargetOpcode::G_FADD*//*Label 19*/ 55385,
744    /*TargetOpcode::G_FSUB*//*Label 20*/ 56016,
745    /*TargetOpcode::G_FMUL*//*Label 21*/ 56631,
746    /*TargetOpcode::G_FMA*//*Label 22*/ 57214,
747    /*TargetOpcode::G_FDIV*//*Label 23*/ 58107, 0, 0, 0, 0, 0, 0,
748    /*TargetOpcode::G_FNEG*//*Label 24*/ 58270,
749    /*TargetOpcode::G_FPEXT*//*Label 25*/ 59187,
750    /*TargetOpcode::G_FPTRUNC*//*Label 26*/ 59344,
751    /*TargetOpcode::G_FPTOSI*//*Label 27*/ 59505,
752    /*TargetOpcode::G_FPTOUI*//*Label 28*/ 59845,
753    /*TargetOpcode::G_SITOFP*//*Label 29*/ 60185,
754    /*TargetOpcode::G_UITOFP*//*Label 30*/ 60522, 0, 0, 0,
755    /*TargetOpcode::G_BR*//*Label 31*/ 60859, 0, 0, 0,
756    /*TargetOpcode::G_BSWAP*//*Label 32*/ 60921,
757    // Label 0: @95
758    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 43*/ 6645,
759    /*GILLT_s32*//*Label 34*/ 110,
760    /*GILLT_s64*//*Label 35*/ 1788,
761    /*GILLT_v2s32*//*Label 36*/ 1839,
762    /*GILLT_v2s64*//*Label 37*/ 2299,
763    /*GILLT_v4s16*//*Label 38*/ 3017,
764    /*GILLT_v4s32*//*Label 39*/ 3477,
765    /*GILLT_v8s8*//*Label 40*/ 4601,
766    /*GILLT_v8s16*//*Label 41*/ 5061,
767    /*GILLT_v16s8*//*Label 42*/ 6185,
768    // Label 34: @110
769    GIM_Try, /*On fail goto*//*Label 44*/ 1787,
770      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
771      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
772      GIM_Try, /*On fail goto*//*Label 45*/ 186, // Rule ID 2738 //
773        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
774        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
775        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
776        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
777        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
778        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
779        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
780        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
781        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
782        GIM_CheckIsSafeToFold, /*InsnID*/1,
783        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
784        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
787        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
788        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
789        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
790        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
791        GIR_EraseFromParent, /*InsnID*/0,
792        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
793        // GIR_Coverage, 2738,
794        GIR_Done,
795      // Label 45: @186
796      GIM_Try, /*On fail goto*//*Label 46*/ 252, // Rule ID 2739 //
797        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
799        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
800        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
801        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
802        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
803        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
804        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
806        GIM_CheckIsSafeToFold, /*InsnID*/1,
807        // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
808        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
812        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
813        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
814        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
815        GIR_EraseFromParent, /*InsnID*/0,
816        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
817        // GIR_Coverage, 2739,
818        GIR_Done,
819      // Label 46: @252
820      GIM_Try, /*On fail goto*//*Label 47*/ 318, // Rule ID 2768 //
821        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
823        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
824        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
825        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
826        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
827        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
828        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
830        GIM_CheckIsSafeToFold, /*InsnID*/1,
831        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
832        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
836        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
837        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
838        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
839        GIR_EraseFromParent, /*InsnID*/0,
840        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
841        // GIR_Coverage, 2768,
842        GIR_Done,
843      // Label 47: @318
844      GIM_Try, /*On fail goto*//*Label 48*/ 384, // Rule ID 2769 //
845        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
846        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
847        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
848        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
849        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
850        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
851        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
852        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
854        GIM_CheckIsSafeToFold, /*InsnID*/1,
855        // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
856        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
860        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
861        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
862        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
863        GIR_EraseFromParent, /*InsnID*/0,
864        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
865        // GIR_Coverage, 2769,
866        GIR_Done,
867      // Label 48: @384
868      GIM_Try, /*On fail goto*//*Label 49*/ 450, // Rule ID 1813 //
869        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
872        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
873        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
874        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
875        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
876        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
877        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
878        GIM_CheckIsSafeToFold, /*InsnID*/1,
879        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
880        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
884        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
885        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
886        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
887        GIR_EraseFromParent, /*InsnID*/0,
888        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
889        // GIR_Coverage, 1813,
890        GIR_Done,
891      // Label 49: @450
892      GIM_Try, /*On fail goto*//*Label 50*/ 516, // Rule ID 1814 //
893        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
896        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
897        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
898        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
899        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
900        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
901        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
902        GIM_CheckIsSafeToFold, /*InsnID*/1,
903        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
904        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
907        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
908        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
909        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
910        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
911        GIR_EraseFromParent, /*InsnID*/0,
912        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
913        // GIR_Coverage, 1814,
914        GIR_Done,
915      // Label 50: @516
916      GIM_Try, /*On fail goto*//*Label 51*/ 582, // Rule ID 1999 //
917        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
920        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
921        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
922        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
923        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
924        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
925        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
926        GIM_CheckIsSafeToFold, /*InsnID*/1,
927        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }))  =>  (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
928        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
932        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
933        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
934        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
935        GIR_EraseFromParent, /*InsnID*/0,
936        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
937        // GIR_Coverage, 1999,
938        GIR_Done,
939      // Label 51: @582
940      GIM_Try, /*On fail goto*//*Label 52*/ 648, // Rule ID 2000 //
941        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
942        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
943        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
944        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
945        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
946        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
947        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
948        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
949        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
950        GIM_CheckIsSafeToFold, /*InsnID*/1,
951        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }))  =>  (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
952        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
956        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
957        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
958        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
959        GIR_EraseFromParent, /*InsnID*/0,
960        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
961        // GIR_Coverage, 2000,
962        GIR_Done,
963      // Label 52: @648
964      GIM_Try, /*On fail goto*//*Label 53*/ 757, // Rule ID 2523 //
965        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
967        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
968        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
969        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
970        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
971        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
972        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
973        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
974        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
975        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
976        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
977        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
978        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
979        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
980        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
981        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
982        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
983        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
984        GIM_CheckIsSafeToFold, /*InsnID*/1,
985        GIM_CheckIsSafeToFold, /*InsnID*/2,
986        GIM_CheckIsSafeToFold, /*InsnID*/3,
987        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra)  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
988        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
989        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
990        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
993        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
994        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
995        GIR_EraseFromParent, /*InsnID*/0,
996        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
997        // GIR_Coverage, 2523,
998        GIR_Done,
999      // Label 53: @757
1000      GIM_Try, /*On fail goto*//*Label 54*/ 866, // Rule ID 2560 //
1001        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1002        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1003        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1004        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1005        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1006        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1007        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1008        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1009        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1010        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1011        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1012        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1013        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1014        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1015        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1016        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1017        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1018        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1020        GIM_CheckIsSafeToFold, /*InsnID*/1,
1021        GIM_CheckIsSafeToFold, /*InsnID*/2,
1022        GIM_CheckIsSafeToFold, /*InsnID*/3,
1023        // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1024        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1029        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1030        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1031        GIR_EraseFromParent, /*InsnID*/0,
1032        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1033        // GIR_Coverage, 2560,
1034        GIR_Done,
1035      // Label 54: @866
1036      GIM_Try, /*On fail goto*//*Label 55*/ 975, // Rule ID 194 //
1037        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
1038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1040        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1041        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1042        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1043        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1044        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1045        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1046        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1047        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1048        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1049        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1050        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1051        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1052        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1053        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1054        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1055        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1056        GIM_CheckIsSafeToFold, /*InsnID*/1,
1057        GIM_CheckIsSafeToFold, /*InsnID*/2,
1058        GIM_CheckIsSafeToFold, /*InsnID*/3,
1059        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1060        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
1061        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1065        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1066        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1067        GIR_EraseFromParent, /*InsnID*/0,
1068        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1069        // GIR_Coverage, 194,
1070        GIR_Done,
1071      // Label 55: @975
1072      GIM_Try, /*On fail goto*//*Label 56*/ 1084, // Rule ID 525 //
1073        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
1074        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1076        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1077        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1078        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1079        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1080        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1081        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1082        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1083        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1084        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1085        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
1086        GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1087        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1088        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1089        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1090        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1091        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
1092        GIM_CheckIsSafeToFold, /*InsnID*/1,
1093        GIM_CheckIsSafeToFold, /*InsnID*/2,
1094        GIM_CheckIsSafeToFold, /*InsnID*/3,
1095        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })))  =>  (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1096        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
1097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1101        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1102        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1103        GIR_EraseFromParent, /*InsnID*/0,
1104        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1105        // GIR_Coverage, 525,
1106        GIR_Done,
1107      // Label 56: @1084
1108      GIM_Try, /*On fail goto*//*Label 57*/ 1136, // Rule ID 74 //
1109        GIM_CheckFeatures, GIFBS_IsARM,
1110        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1111        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1112        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1113        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1114        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
1115        // MIs[1] Operand 1
1116        // No operand predicates
1117        GIM_CheckIsSafeToFold, /*InsnID*/1,
1118        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri,
1120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1122        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1123        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1124        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1125        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1126        GIR_EraseFromParent, /*InsnID*/0,
1127        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1128        // GIR_Coverage, 74,
1129        GIR_Done,
1130      // Label 57: @1136
1131      GIM_Try, /*On fail goto*//*Label 58*/ 1188, // Rule ID 411 //
1132        GIM_CheckFeatures, GIFBS_IsThumb2,
1133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1134        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1135        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1136        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1137        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
1138        // MIs[1] Operand 1
1139        // No operand predicates
1140        GIM_CheckIsSafeToFold, /*InsnID*/1,
1141        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1142        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
1143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1145        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1146        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1147        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1148        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1149        GIR_EraseFromParent, /*InsnID*/0,
1150        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1151        // GIR_Coverage, 411,
1152        GIR_Done,
1153      // Label 58: @1188
1154      GIM_Try, /*On fail goto*//*Label 59*/ 1237, // Rule ID 412 //
1155        GIM_CheckFeatures, GIFBS_IsThumb2,
1156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1158        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1159        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
1160        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
1161        // MIs[1] Operand 1
1162        // No operand predicates
1163        GIM_CheckIsSafeToFold, /*InsnID*/1,
1164        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
1165        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12,
1166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1168        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
1169        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1170        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1171        GIR_EraseFromParent, /*InsnID*/0,
1172        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1173        // GIR_Coverage, 412,
1174        GIR_Done,
1175      // Label 59: @1237
1176      GIM_Try, /*On fail goto*//*Label 60*/ 1307, // Rule ID 173 //
1177        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1179        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1180        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1181        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1182        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1183        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1184        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1186        GIM_CheckIsSafeToFold, /*InsnID*/1,
1187        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1188        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1193        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1194        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1195        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1196        GIR_EraseFromParent, /*InsnID*/0,
1197        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1198        // GIR_Coverage, 173,
1199        GIR_Done,
1200      // Label 60: @1307
1201      GIM_Try, /*On fail goto*//*Label 61*/ 1377, // Rule ID 174 //
1202        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1204        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1205        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1206        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1207        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1208        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1209        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1211        GIM_CheckIsSafeToFold, /*InsnID*/1,
1212        // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra)  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1213        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1218        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1219        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1220        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1221        GIR_EraseFromParent, /*InsnID*/0,
1222        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1223        // GIR_Coverage, 174,
1224        GIR_Done,
1225      // Label 61: @1377
1226      GIM_Try, /*On fail goto*//*Label 62*/ 1444, // Rule ID 507 //
1227        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1229        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1230        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1231        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1232        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1233        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1234        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1236        GIM_CheckIsSafeToFold, /*InsnID*/1,
1237        // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra)  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1238        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1241        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
1243        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1244        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1245        GIR_EraseFromParent, /*InsnID*/0,
1246        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1247        // GIR_Coverage, 507,
1248        GIR_Done,
1249      // Label 62: @1444
1250      GIM_Try, /*On fail goto*//*Label 63*/ 1514, // Rule ID 2517 //
1251        GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
1252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1254        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1255        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1256        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1257        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1258        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1259        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1260        GIM_CheckIsSafeToFold, /*InsnID*/1,
1261        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1262        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
1263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1264        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1267        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1268        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1269        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1270        GIR_EraseFromParent, /*InsnID*/0,
1271        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1272        // GIR_Coverage, 2517,
1273        GIR_Done,
1274      // Label 63: @1514
1275      GIM_Try, /*On fail goto*//*Label 64*/ 1584, // Rule ID 2518 //
1276        GIM_CheckFeatures, GIFBS_IsARM_NoV6,
1277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1278        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1279        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1280        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1281        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1282        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1283        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1284        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1285        GIM_CheckIsSafeToFold, /*InsnID*/1,
1286        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm))  =>  (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
1287        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
1288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1292        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1293        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1294        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1295        GIR_EraseFromParent, /*InsnID*/0,
1296        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1297        // GIR_Coverage, 2518,
1298        GIR_Done,
1299      // Label 64: @1584
1300      GIM_Try, /*On fail goto*//*Label 65*/ 1651, // Rule ID 2555 //
1301        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
1302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
1303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1304        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1305        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1306        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1307        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1308        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1309        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1310        GIM_CheckIsSafeToFold, /*InsnID*/1,
1311        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1312        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
1313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
1315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
1316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
1317        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1318        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1319        GIR_EraseFromParent, /*InsnID*/0,
1320        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1321        // GIR_Coverage, 2555,
1322        GIR_Done,
1323      // Label 65: @1651
1324      GIM_Try, /*On fail goto*//*Label 66*/ 1696, // Rule ID 75 //
1325        GIM_CheckFeatures, GIFBS_IsARM,
1326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
1327        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
1328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
1329        // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
1330        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr,
1331        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1332        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1334        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1335        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1336        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1337        GIR_EraseFromParent, /*InsnID*/0,
1338        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1339        // GIR_Coverage, 75,
1340        GIR_Done,
1341      // Label 66: @1696
1342      GIM_Try, /*On fail goto*//*Label 67*/ 1741, // Rule ID 413 //
1343        GIM_CheckFeatures, GIFBS_IsThumb2,
1344        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1345        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
1346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
1347        // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1348        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
1352        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1353        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1354        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1355        GIR_EraseFromParent, /*InsnID*/0,
1356        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1357        // GIR_Coverage, 413,
1358        GIR_Done,
1359      // Label 67: @1741
1360      GIM_Try, /*On fail goto*//*Label 68*/ 1786, // Rule ID 2537 //
1361        GIM_CheckFeatures, GIFBS_IsThumb2,
1362        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
1363        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
1364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
1365        // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
1366        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
1367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
1370        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1371        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1372        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1373        GIR_EraseFromParent, /*InsnID*/0,
1374        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1375        // GIR_Coverage, 2537,
1376        GIR_Done,
1377      // Label 68: @1786
1378      GIM_Reject,
1379    // Label 44: @1787
1380    GIM_Reject,
1381    // Label 35: @1788
1382    GIM_Try, /*On fail goto*//*Label 69*/ 1838, // Rule ID 760 //
1383      GIM_CheckFeatures, GIFBS_HasNEON,
1384      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
1385      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
1386      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1387      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1388      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1389      // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1390      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64,
1391      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1392      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1393      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1394      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1395      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1396      GIR_EraseFromParent, /*InsnID*/0,
1397      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1398      // GIR_Coverage, 760,
1399      GIR_Done,
1400    // Label 69: @1838
1401    GIM_Reject,
1402    // Label 36: @1839
1403    GIM_Try, /*On fail goto*//*Label 70*/ 2298,
1404      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
1405      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
1406      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1407      GIM_Try, /*On fail goto*//*Label 71*/ 1923, // Rule ID 2675 //
1408        GIM_CheckFeatures, GIFBS_HasNEON,
1409        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1410        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1411        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1412        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1413        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1414        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1415        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1416        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1418        GIM_CheckIsSafeToFold, /*InsnID*/1,
1419        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1016:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1420        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1423        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1425        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1426        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1427        GIR_EraseFromParent, /*InsnID*/0,
1428        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1429        // GIR_Coverage, 2675,
1430        GIR_Done,
1431      // Label 71: @1923
1432      GIM_Try, /*On fail goto*//*Label 72*/ 1993, // Rule ID 2681 //
1433        GIM_CheckFeatures, GIFBS_HasNEON,
1434        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1435        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1436        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1437        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1438        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1439        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1440        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1441        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1443        GIM_CheckIsSafeToFold, /*InsnID*/1,
1444        // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1017:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1445        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1450        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1451        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1452        GIR_EraseFromParent, /*InsnID*/0,
1453        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1454        // GIR_Coverage, 2681,
1455        GIR_Done,
1456      // Label 72: @1993
1457      GIM_Try, /*On fail goto*//*Label 73*/ 2063, // Rule ID 1152 //
1458        GIM_CheckFeatures, GIFBS_HasNEON,
1459        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1460        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1461        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1462        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1463        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1464        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1465        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1466        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1467        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1468        GIM_CheckIsSafeToFold, /*InsnID*/1,
1469        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1016:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1470        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
1471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1475        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1476        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1477        GIR_EraseFromParent, /*InsnID*/0,
1478        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1479        // GIR_Coverage, 1152,
1480        GIR_Done,
1481      // Label 73: @2063
1482      GIM_Try, /*On fail goto*//*Label 74*/ 2133, // Rule ID 1158 //
1483        GIM_CheckFeatures, GIFBS_HasNEON,
1484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1485        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1486        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1487        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1488        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1489        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1490        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
1491        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1492        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1493        GIM_CheckIsSafeToFold, /*InsnID*/1,
1494        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1017:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1495        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
1496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1500        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1501        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1502        GIR_EraseFromParent, /*InsnID*/0,
1503        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1504        // GIR_Coverage, 1158,
1505        GIR_Done,
1506      // Label 74: @2133
1507      GIM_Try, /*On fail goto*//*Label 75*/ 2196, // Rule ID 2605 //
1508        GIM_CheckFeatures, GIFBS_HasNEON,
1509        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1510        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1511        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1512        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1513        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1514        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1515        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1516        GIM_CheckIsSafeToFold, /*InsnID*/1,
1517        // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1518        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1519        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1520        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1523        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1524        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1525        GIR_EraseFromParent, /*InsnID*/0,
1526        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1527        // GIR_Coverage, 2605,
1528        GIR_Done,
1529      // Label 75: @2196
1530      GIM_Try, /*On fail goto*//*Label 76*/ 2259, // Rule ID 875 //
1531        GIM_CheckFeatures, GIFBS_HasNEON,
1532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1533        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1534        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1535        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1536        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
1537        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1538        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1539        GIM_CheckIsSafeToFold, /*InsnID*/1,
1540        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1541        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
1542        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1546        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1547        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1548        GIR_EraseFromParent, /*InsnID*/0,
1549        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1550        // GIR_Coverage, 875,
1551        GIR_Done,
1552      // Label 76: @2259
1553      GIM_Try, /*On fail goto*//*Label 77*/ 2297, // Rule ID 756 //
1554        GIM_CheckFeatures, GIFBS_HasNEON,
1555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1557        // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32,
1559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1562        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1563        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1564        GIR_EraseFromParent, /*InsnID*/0,
1565        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1566        // GIR_Coverage, 756,
1567        GIR_Done,
1568      // Label 77: @2297
1569      GIM_Reject,
1570    // Label 70: @2298
1571    GIM_Reject,
1572    // Label 37: @2299
1573    GIM_Try, /*On fail goto*//*Label 78*/ 3016,
1574      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
1575      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
1576      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
1577      GIM_Try, /*On fail goto*//*Label 79*/ 2396, // Rule ID 2687 //
1578        GIM_CheckFeatures, GIFBS_HasNEON,
1579        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1580        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1581        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1582        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1583        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1584        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1585        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1586        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1587        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1588        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1589        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1591        GIM_CheckIsSafeToFold, /*InsnID*/1,
1592        GIM_CheckIsSafeToFold, /*InsnID*/2,
1593        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1016:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1594        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1599        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1600        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1601        GIR_EraseFromParent, /*InsnID*/0,
1602        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1603        // GIR_Coverage, 2687,
1604        GIR_Done,
1605      // Label 79: @2396
1606      GIM_Try, /*On fail goto*//*Label 80*/ 2479, // Rule ID 2690 //
1607        GIM_CheckFeatures, GIFBS_HasNEON,
1608        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1609        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1610        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1611        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1612        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1613        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1614        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1615        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1616        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1617        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1618        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1620        GIM_CheckIsSafeToFold, /*InsnID*/1,
1621        GIM_CheckIsSafeToFold, /*InsnID*/2,
1622        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1017:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1)  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1623        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1628        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1629        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1630        GIR_EraseFromParent, /*InsnID*/0,
1631        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1632        // GIR_Coverage, 2690,
1633        GIR_Done,
1634      // Label 80: @2479
1635      GIM_Try, /*On fail goto*//*Label 81*/ 2562, // Rule ID 1164 //
1636        GIM_CheckFeatures, GIFBS_HasNEON,
1637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1638        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1639        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1640        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1641        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1642        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1643        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1644        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
1645        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1646        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1647        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1648        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1649        GIM_CheckIsSafeToFold, /*InsnID*/1,
1650        GIM_CheckIsSafeToFold, /*InsnID*/2,
1651        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1016:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1652        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
1653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1654        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1655        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1657        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1658        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1659        GIR_EraseFromParent, /*InsnID*/0,
1660        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1661        // GIR_Coverage, 1164,
1662        GIR_Done,
1663      // Label 81: @2562
1664      GIM_Try, /*On fail goto*//*Label 82*/ 2645, // Rule ID 1167 //
1665        GIM_CheckFeatures, GIFBS_HasNEON,
1666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1667        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1668        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1669        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1670        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1671        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
1672        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
1673        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
1674        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
1675        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
1676        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1677        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1678        GIM_CheckIsSafeToFold, /*InsnID*/1,
1679        GIM_CheckIsSafeToFold, /*InsnID*/2,
1680        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1017:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)))  =>  (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1681        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
1682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
1685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
1686        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1687        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1688        GIR_EraseFromParent, /*InsnID*/0,
1689        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1690        // GIR_Coverage, 1167,
1691        GIR_Done,
1692      // Label 82: @2645
1693      GIM_Try, /*On fail goto*//*Label 83*/ 2709, // Rule ID 768 //
1694        GIM_CheckFeatures, GIFBS_HasNEON,
1695        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1696        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1697        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1698        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1699        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1700        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
1701        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1702        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1703        GIM_CheckIsSafeToFold, /*InsnID*/1,
1704        GIM_CheckIsSafeToFold, /*InsnID*/2,
1705        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1706        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64,
1707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1709        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1710        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1711        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1712        GIR_EraseFromParent, /*InsnID*/0,
1713        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1714        // GIR_Coverage, 768,
1715        GIR_Done,
1716      // Label 83: @2709
1717      GIM_Try, /*On fail goto*//*Label 84*/ 2773, // Rule ID 771 //
1718        GIM_CheckFeatures, GIFBS_HasNEON,
1719        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1720        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1721        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1722        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1723        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1724        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
1725        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
1726        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1727        GIM_CheckIsSafeToFold, /*InsnID*/1,
1728        GIM_CheckIsSafeToFold, /*InsnID*/2,
1729        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1730        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
1731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
1734        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1735        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1736        GIR_EraseFromParent, /*InsnID*/0,
1737        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1738        // GIR_Coverage, 771,
1739        GIR_Done,
1740      // Label 84: @2773
1741      GIM_Try, /*On fail goto*//*Label 85*/ 2824, // Rule ID 2581 //
1742        GIM_CheckFeatures, GIFBS_HasNEON,
1743        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1744        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1745        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1746        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1748        GIM_CheckIsSafeToFold, /*InsnID*/1,
1749        // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1750        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
1753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1754        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1755        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1756        GIR_EraseFromParent, /*InsnID*/0,
1757        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1758        // GIR_Coverage, 2581,
1759        GIR_Done,
1760      // Label 85: @2824
1761      GIM_Try, /*On fail goto*//*Label 86*/ 2875, // Rule ID 2584 //
1762        GIM_CheckFeatures, GIFBS_HasNEON,
1763        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1764        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1765        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1766        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1768        GIM_CheckIsSafeToFold, /*InsnID*/1,
1769        // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn)  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1770        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
1771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
1773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1774        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1775        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1776        GIR_EraseFromParent, /*InsnID*/0,
1777        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1778        // GIR_Coverage, 2584,
1779        GIR_Done,
1780      // Label 86: @2875
1781      GIM_Try, /*On fail goto*//*Label 87*/ 2926, // Rule ID 774 //
1782        GIM_CheckFeatures, GIFBS_HasNEON,
1783        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1784        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1785        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
1786        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1787        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1788        GIM_CheckIsSafeToFold, /*InsnID*/1,
1789        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1790        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
1791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1794        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1795        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1796        GIR_EraseFromParent, /*InsnID*/0,
1797        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1798        // GIR_Coverage, 774,
1799        GIR_Done,
1800      // Label 87: @2926
1801      GIM_Try, /*On fail goto*//*Label 88*/ 2977, // Rule ID 777 //
1802        GIM_CheckFeatures, GIFBS_HasNEON,
1803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1804        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1805        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
1806        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
1807        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1808        GIM_CheckIsSafeToFold, /*InsnID*/1,
1809        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1810        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
1811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
1814        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1815        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1816        GIR_EraseFromParent, /*InsnID*/0,
1817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1818        // GIR_Coverage, 777,
1819        GIR_Done,
1820      // Label 88: @2977
1821      GIM_Try, /*On fail goto*//*Label 89*/ 3015, // Rule ID 761 //
1822        GIM_CheckFeatures, GIFBS_HasNEON,
1823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
1824        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
1825        // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
1826        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64,
1827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1830        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1831        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1832        GIR_EraseFromParent, /*InsnID*/0,
1833        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1834        // GIR_Coverage, 761,
1835        GIR_Done,
1836      // Label 89: @3015
1837      GIM_Reject,
1838    // Label 78: @3016
1839    GIM_Reject,
1840    // Label 38: @3017
1841    GIM_Try, /*On fail goto*//*Label 90*/ 3476,
1842      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
1843      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
1844      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
1845      GIM_Try, /*On fail goto*//*Label 91*/ 3101, // Rule ID 2674 //
1846        GIM_CheckFeatures, GIFBS_HasNEON,
1847        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1848        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1849        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1850        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1851        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1852        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1853        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1854        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1855        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1856        GIM_CheckIsSafeToFold, /*InsnID*/1,
1857        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1016:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1858        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
1859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1863        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1864        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1865        GIR_EraseFromParent, /*InsnID*/0,
1866        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1867        // GIR_Coverage, 2674,
1868        GIR_Done,
1869      // Label 91: @3101
1870      GIM_Try, /*On fail goto*//*Label 92*/ 3171, // Rule ID 2680 //
1871        GIM_CheckFeatures, GIFBS_HasNEON,
1872        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1873        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1874        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1875        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1876        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1877        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1878        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1879        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1881        GIM_CheckIsSafeToFold, /*InsnID*/1,
1882        // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 1017:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1883        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
1884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1888        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1889        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1890        GIR_EraseFromParent, /*InsnID*/0,
1891        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1892        // GIR_Coverage, 2680,
1893        GIR_Done,
1894      // Label 92: @3171
1895      GIM_Try, /*On fail goto*//*Label 93*/ 3241, // Rule ID 1151 //
1896        GIM_CheckFeatures, GIFBS_HasNEON,
1897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1898        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1899        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1900        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1901        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
1902        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1903        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1904        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1905        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1906        GIM_CheckIsSafeToFold, /*InsnID*/1,
1907        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1016:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1908        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i16,
1909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1911        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1912        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1913        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1914        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1915        GIR_EraseFromParent, /*InsnID*/0,
1916        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1917        // GIR_Coverage, 1151,
1918        GIR_Done,
1919      // Label 93: @3241
1920      GIM_Try, /*On fail goto*//*Label 94*/ 3311, // Rule ID 1157 //
1921        GIM_CheckFeatures, GIFBS_HasNEON,
1922        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1923        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1924        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
1925        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
1926        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
1927        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1928        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
1929        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1930        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
1931        GIM_CheckIsSafeToFold, /*InsnID*/1,
1932        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1017:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1933        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i16,
1934        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
1937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1938        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1939        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1940        GIR_EraseFromParent, /*InsnID*/0,
1941        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1942        // GIR_Coverage, 1157,
1943        GIR_Done,
1944      // Label 94: @3311
1945      GIM_Try, /*On fail goto*//*Label 95*/ 3374, // Rule ID 2604 //
1946        GIM_CheckFeatures, GIFBS_HasNEON,
1947        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1948        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1949        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
1950        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1951        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1952        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1954        GIM_CheckIsSafeToFold, /*InsnID*/1,
1955        // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1956        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
1957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
1959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1961        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1962        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1963        GIR_EraseFromParent, /*InsnID*/0,
1964        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1965        // GIR_Coverage, 2604,
1966        GIR_Done,
1967      // Label 95: @3374
1968      GIM_Try, /*On fail goto*//*Label 96*/ 3437, // Rule ID 874 //
1969        GIM_CheckFeatures, GIFBS_HasNEON,
1970        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1971        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1972        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
1973        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
1974        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
1975        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1976        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1977        GIM_CheckIsSafeToFold, /*InsnID*/1,
1978        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1979        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i16,
1980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
1983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
1984        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
1985        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
1986        GIR_EraseFromParent, /*InsnID*/0,
1987        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1988        // GIR_Coverage, 874,
1989        GIR_Done,
1990      // Label 96: @3437
1991      GIM_Try, /*On fail goto*//*Label 97*/ 3475, // Rule ID 755 //
1992        GIM_CheckFeatures, GIFBS_HasNEON,
1993        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
1994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
1995        // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
1996        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i16,
1997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
1998        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
1999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2000        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2001        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2002        GIR_EraseFromParent, /*InsnID*/0,
2003        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2004        // GIR_Coverage, 755,
2005        GIR_Done,
2006      // Label 97: @3475
2007      GIM_Reject,
2008    // Label 90: @3476
2009    GIM_Reject,
2010    // Label 39: @3477
2011    GIM_Try, /*On fail goto*//*Label 98*/ 4600,
2012      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
2013      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
2014      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2015      GIM_Try, /*On fail goto*//*Label 99*/ 3574, // Rule ID 2686 //
2016        GIM_CheckFeatures, GIFBS_HasNEON,
2017        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2018        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2019        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2020        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2021        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2022        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2023        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2024        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2025        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2026        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2027        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2028        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2029        GIM_CheckIsSafeToFold, /*InsnID*/1,
2030        GIM_CheckIsSafeToFold, /*InsnID*/2,
2031        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1016:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2032        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2033        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2034        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2037        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2038        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2039        GIR_EraseFromParent, /*InsnID*/0,
2040        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2041        // GIR_Coverage, 2686,
2042        GIR_Done,
2043      // Label 99: @3574
2044      GIM_Try, /*On fail goto*//*Label 100*/ 3657, // Rule ID 2689 //
2045        GIM_CheckFeatures, GIFBS_HasNEON,
2046        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2047        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2048        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2049        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2050        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2051        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2052        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2053        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2054        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2055        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2056        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2058        GIM_CheckIsSafeToFold, /*InsnID*/1,
2059        GIM_CheckIsSafeToFold, /*InsnID*/2,
2060        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1017:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1)  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2061        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2066        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2067        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2068        GIR_EraseFromParent, /*InsnID*/0,
2069        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2070        // GIR_Coverage, 2689,
2071        GIR_Done,
2072      // Label 100: @3657
2073      GIM_Try, /*On fail goto*//*Label 101*/ 3740, // Rule ID 1163 //
2074        GIM_CheckFeatures, GIFBS_HasNEON,
2075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2076        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2077        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2078        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2079        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2080        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2081        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2082        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2083        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2084        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2085        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2086        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2087        GIM_CheckIsSafeToFold, /*InsnID*/1,
2088        GIM_CheckIsSafeToFold, /*InsnID*/2,
2089        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1016:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2090        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv4i32,
2091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2095        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2096        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2097        GIR_EraseFromParent, /*InsnID*/0,
2098        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2099        // GIR_Coverage, 1163,
2100        GIR_Done,
2101      // Label 101: @3740
2102      GIM_Try, /*On fail goto*//*Label 102*/ 3823, // Rule ID 1166 //
2103        GIM_CheckFeatures, GIFBS_HasNEON,
2104        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2105        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2106        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2107        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2108        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2109        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2110        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2111        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2112        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
2113        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
2114        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2115        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2116        GIM_CheckIsSafeToFold, /*InsnID*/1,
2117        GIM_CheckIsSafeToFold, /*InsnID*/2,
2118        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1017:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)))  =>  (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2119        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv4i32,
2120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2123        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2124        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2125        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2126        GIR_EraseFromParent, /*InsnID*/0,
2127        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2128        // GIR_Coverage, 1166,
2129        GIR_Done,
2130      // Label 102: @3823
2131      GIM_Try, /*On fail goto*//*Label 103*/ 3893, // Rule ID 2678 //
2132        GIM_CheckFeatures, GIFBS_HasNEON,
2133        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2134        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2135        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2136        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2137        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2138        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2139        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2140        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2142        GIM_CheckIsSafeToFold, /*InsnID*/1,
2143        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1016:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2144        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2145        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2146        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2149        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2150        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2151        GIR_EraseFromParent, /*InsnID*/0,
2152        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2153        // GIR_Coverage, 2678,
2154        GIR_Done,
2155      // Label 103: @3893
2156      GIM_Try, /*On fail goto*//*Label 104*/ 3963, // Rule ID 2684 //
2157        GIM_CheckFeatures, GIFBS_HasNEON,
2158        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2159        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2160        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2161        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2162        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2163        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2164        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2165        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2167        GIM_CheckIsSafeToFold, /*InsnID*/1,
2168        // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 1017:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2169        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2174        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2175        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2176        GIR_EraseFromParent, /*InsnID*/0,
2177        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2178        // GIR_Coverage, 2684,
2179        GIR_Done,
2180      // Label 104: @3963
2181      GIM_Try, /*On fail goto*//*Label 105*/ 4033, // Rule ID 1155 //
2182        GIM_CheckFeatures, GIFBS_HasNEON,
2183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2184        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2185        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2186        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2187        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2188        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2189        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2190        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2191        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2192        GIM_CheckIsSafeToFold, /*InsnID*/1,
2193        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1016:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2194        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv4i32,
2195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2199        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2200        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2201        GIR_EraseFromParent, /*InsnID*/0,
2202        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2203        // GIR_Coverage, 1155,
2204        GIR_Done,
2205      // Label 105: @4033
2206      GIM_Try, /*On fail goto*//*Label 106*/ 4103, // Rule ID 1161 //
2207        GIM_CheckFeatures, GIFBS_HasNEON,
2208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2209        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2210        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2211        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2212        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2213        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2214        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
2215        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2216        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2217        GIM_CheckIsSafeToFold, /*InsnID*/1,
2218        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1017:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2219        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv4i32,
2220        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2224        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2225        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2226        GIR_EraseFromParent, /*InsnID*/0,
2227        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2228        // GIR_Coverage, 1161,
2229        GIR_Done,
2230      // Label 106: @4103
2231      GIM_Try, /*On fail goto*//*Label 107*/ 4167, // Rule ID 767 //
2232        GIM_CheckFeatures, GIFBS_HasNEON,
2233        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2234        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2235        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2236        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2237        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2238        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2239        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2240        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2241        GIM_CheckIsSafeToFold, /*InsnID*/1,
2242        GIM_CheckIsSafeToFold, /*InsnID*/2,
2243        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2244        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv4i32,
2245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2248        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2249        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2250        GIR_EraseFromParent, /*InsnID*/0,
2251        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2252        // GIR_Coverage, 767,
2253        GIR_Done,
2254      // Label 107: @4167
2255      GIM_Try, /*On fail goto*//*Label 108*/ 4231, // Rule ID 770 //
2256        GIM_CheckFeatures, GIFBS_HasNEON,
2257        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2258        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2259        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2260        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2261        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2262        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2263        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
2264        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2265        GIM_CheckIsSafeToFold, /*InsnID*/1,
2266        GIM_CheckIsSafeToFold, /*InsnID*/2,
2267        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2268        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv4i32,
2269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2272        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2273        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2274        GIR_EraseFromParent, /*InsnID*/0,
2275        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2276        // GIR_Coverage, 770,
2277        GIR_Done,
2278      // Label 108: @4231
2279      GIM_Try, /*On fail goto*//*Label 109*/ 4294, // Rule ID 2608 //
2280        GIM_CheckFeatures, GIFBS_HasNEON,
2281        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2282        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2283        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2284        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2285        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2286        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2288        GIM_CheckIsSafeToFold, /*InsnID*/1,
2289        // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2290        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2295        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2296        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2297        GIR_EraseFromParent, /*InsnID*/0,
2298        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2299        // GIR_Coverage, 2608,
2300        GIR_Done,
2301      // Label 109: @4294
2302      GIM_Try, /*On fail goto*//*Label 110*/ 4345, // Rule ID 2580 //
2303        GIM_CheckFeatures, GIFBS_HasNEON,
2304        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2305        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2306        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2307        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2309        GIM_CheckIsSafeToFold, /*InsnID*/1,
2310        // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2311        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2315        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2316        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2317        GIR_EraseFromParent, /*InsnID*/0,
2318        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2319        // GIR_Coverage, 2580,
2320        GIR_Done,
2321      // Label 110: @4345
2322      GIM_Try, /*On fail goto*//*Label 111*/ 4396, // Rule ID 2583 //
2323        GIM_CheckFeatures, GIFBS_HasNEON,
2324        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2325        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2326        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2327        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2328        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2329        GIM_CheckIsSafeToFold, /*InsnID*/1,
2330        // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn)  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2331        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2332        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2333        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2334        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2335        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2336        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2337        GIR_EraseFromParent, /*InsnID*/0,
2338        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2339        // GIR_Coverage, 2583,
2340        GIR_Done,
2341      // Label 111: @4396
2342      GIM_Try, /*On fail goto*//*Label 112*/ 4459, // Rule ID 878 //
2343        GIM_CheckFeatures, GIFBS_HasNEON,
2344        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2345        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2346        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2347        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2348        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
2349        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2350        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2351        GIM_CheckIsSafeToFold, /*InsnID*/1,
2352        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2353        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv4i32,
2354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2358        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2359        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2360        GIR_EraseFromParent, /*InsnID*/0,
2361        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2362        // GIR_Coverage, 878,
2363        GIR_Done,
2364      // Label 112: @4459
2365      GIM_Try, /*On fail goto*//*Label 113*/ 4510, // Rule ID 773 //
2366        GIM_CheckFeatures, GIFBS_HasNEON,
2367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2368        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2369        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2370        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2371        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2372        GIM_CheckIsSafeToFold, /*InsnID*/1,
2373        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2374        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv4i32,
2375        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2376        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2378        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2379        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2380        GIR_EraseFromParent, /*InsnID*/0,
2381        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2382        // GIR_Coverage, 773,
2383        GIR_Done,
2384      // Label 113: @4510
2385      GIM_Try, /*On fail goto*//*Label 114*/ 4561, // Rule ID 776 //
2386        GIM_CheckFeatures, GIFBS_HasNEON,
2387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2388        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2389        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2390        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
2391        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2392        GIM_CheckIsSafeToFold, /*InsnID*/1,
2393        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
2394        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv4i32,
2395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2398        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2399        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2400        GIR_EraseFromParent, /*InsnID*/0,
2401        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2402        // GIR_Coverage, 776,
2403        GIR_Done,
2404      // Label 114: @4561
2405      GIM_Try, /*On fail goto*//*Label 115*/ 4599, // Rule ID 759 //
2406        GIM_CheckFeatures, GIFBS_HasNEON,
2407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2409        // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2410        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv4i32,
2411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2414        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2415        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2416        GIR_EraseFromParent, /*InsnID*/0,
2417        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2418        // GIR_Coverage, 759,
2419        GIR_Done,
2420      // Label 115: @4599
2421      GIM_Reject,
2422    // Label 98: @4600
2423    GIM_Reject,
2424    // Label 40: @4601
2425    GIM_Try, /*On fail goto*//*Label 116*/ 5060,
2426      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
2427      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
2428      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
2429      GIM_Try, /*On fail goto*//*Label 117*/ 4685, // Rule ID 2673 //
2430        GIM_CheckFeatures, GIFBS_HasNEON,
2431        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2432        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2433        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2434        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2435        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2436        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2437        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2438        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2440        GIM_CheckIsSafeToFold, /*InsnID*/1,
2441        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1016:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2442        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2443        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2444        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2445        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2447        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2448        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2449        GIR_EraseFromParent, /*InsnID*/0,
2450        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2451        // GIR_Coverage, 2673,
2452        GIR_Done,
2453      // Label 117: @4685
2454      GIM_Try, /*On fail goto*//*Label 118*/ 4755, // Rule ID 2679 //
2455        GIM_CheckFeatures, GIFBS_HasNEON,
2456        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2457        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2458        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2459        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2460        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2461        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2462        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2463        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2465        GIM_CheckIsSafeToFold, /*InsnID*/1,
2466        // (add:{ *:[v8i8] } (intrinsic_wo_chain:{ *:[v8i8] } 1017:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2467        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2472        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2473        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2474        GIR_EraseFromParent, /*InsnID*/0,
2475        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2476        // GIR_Coverage, 2679,
2477        GIR_Done,
2478      // Label 118: @4755
2479      GIM_Try, /*On fail goto*//*Label 119*/ 4825, // Rule ID 1150 //
2480        GIM_CheckFeatures, GIFBS_HasNEON,
2481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2482        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2483        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2484        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2485        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2486        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2487        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2488        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2489        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2490        GIM_CheckIsSafeToFold, /*InsnID*/1,
2491        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1016:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2492        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i8,
2493        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2494        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2495        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2497        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2498        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2499        GIR_EraseFromParent, /*InsnID*/0,
2500        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2501        // GIR_Coverage, 1150,
2502        GIR_Done,
2503      // Label 119: @4825
2504      GIM_Try, /*On fail goto*//*Label 120*/ 4895, // Rule ID 1156 //
2505        GIM_CheckFeatures, GIFBS_HasNEON,
2506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2507        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2508        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2509        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2510        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2511        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2512        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
2513        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2514        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2515        GIM_CheckIsSafeToFold, /*InsnID*/1,
2516        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (intrinsic_wo_chain:{ *:[v8i8] } 1017:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2517        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i8,
2518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2519        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2520        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2521        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2522        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2523        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2524        GIR_EraseFromParent, /*InsnID*/0,
2525        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2526        // GIR_Coverage, 1156,
2527        GIR_Done,
2528      // Label 120: @4895
2529      GIM_Try, /*On fail goto*//*Label 121*/ 4958, // Rule ID 2603 //
2530        GIM_CheckFeatures, GIFBS_HasNEON,
2531        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2532        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2533        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2534        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2535        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2536        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2537        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2538        GIM_CheckIsSafeToFold, /*InsnID*/1,
2539        // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1)  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2540        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2542        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2545        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2546        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2547        GIR_EraseFromParent, /*InsnID*/0,
2548        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2549        // GIR_Coverage, 2603,
2550        GIR_Done,
2551      // Label 121: @4958
2552      GIM_Try, /*On fail goto*//*Label 122*/ 5021, // Rule ID 873 //
2553        GIM_CheckFeatures, GIFBS_HasNEON,
2554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2555        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2556        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2557        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2558        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2559        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2560        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2561        GIM_CheckIsSafeToFold, /*InsnID*/1,
2562        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2563        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i8,
2564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2565        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2568        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2569        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2570        GIR_EraseFromParent, /*InsnID*/0,
2571        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2572        // GIR_Coverage, 873,
2573        GIR_Done,
2574      // Label 122: @5021
2575      GIM_Try, /*On fail goto*//*Label 123*/ 5059, // Rule ID 754 //
2576        GIM_CheckFeatures, GIFBS_HasNEON,
2577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2578        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2579        // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2580        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i8,
2581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2584        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2585        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2586        GIR_EraseFromParent, /*InsnID*/0,
2587        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2588        // GIR_Coverage, 754,
2589        GIR_Done,
2590      // Label 123: @5059
2591      GIM_Reject,
2592    // Label 116: @5060
2593    GIM_Reject,
2594    // Label 41: @5061
2595    GIM_Try, /*On fail goto*//*Label 124*/ 6184,
2596      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
2597      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
2598      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
2599      GIM_Try, /*On fail goto*//*Label 125*/ 5158, // Rule ID 2685 //
2600        GIM_CheckFeatures, GIFBS_HasNEON,
2601        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2602        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2603        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2604        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2605        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2606        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2607        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2608        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2609        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2610        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2611        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2613        GIM_CheckIsSafeToFold, /*InsnID*/1,
2614        GIM_CheckIsSafeToFold, /*InsnID*/2,
2615        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1016:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2616        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2617        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2621        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2622        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2623        GIR_EraseFromParent, /*InsnID*/0,
2624        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2625        // GIR_Coverage, 2685,
2626        GIR_Done,
2627      // Label 125: @5158
2628      GIM_Try, /*On fail goto*//*Label 126*/ 5241, // Rule ID 2688 //
2629        GIM_CheckFeatures, GIFBS_HasNEON,
2630        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2631        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2632        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2633        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2634        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2635        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2636        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2637        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2638        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2639        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2640        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2641        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2642        GIM_CheckIsSafeToFold, /*InsnID*/1,
2643        GIM_CheckIsSafeToFold, /*InsnID*/2,
2644        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1017:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1)  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2645        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2646        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2647        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2648        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2649        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2650        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2651        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2652        GIR_EraseFromParent, /*InsnID*/0,
2653        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2654        // GIR_Coverage, 2688,
2655        GIR_Done,
2656      // Label 126: @5241
2657      GIM_Try, /*On fail goto*//*Label 127*/ 5324, // Rule ID 1162 //
2658        GIM_CheckFeatures, GIFBS_HasNEON,
2659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2660        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2661        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2662        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2663        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2664        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2665        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2666        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
2667        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2668        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2669        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2670        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2671        GIM_CheckIsSafeToFold, /*InsnID*/1,
2672        GIM_CheckIsSafeToFold, /*InsnID*/2,
2673        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1016:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2674        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv8i16,
2675        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2676        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2679        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2680        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2681        GIR_EraseFromParent, /*InsnID*/0,
2682        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2683        // GIR_Coverage, 1162,
2684        GIR_Done,
2685      // Label 127: @5324
2686      GIM_Try, /*On fail goto*//*Label 128*/ 5407, // Rule ID 1165 //
2687        GIM_CheckFeatures, GIFBS_HasNEON,
2688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2689        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2690        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2691        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2692        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2693        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
2694        GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
2695        GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
2696        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
2697        GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v8s8,
2698        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
2699        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
2700        GIM_CheckIsSafeToFold, /*InsnID*/1,
2701        GIM_CheckIsSafeToFold, /*InsnID*/2,
2702        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1017:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)))  =>  (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2703        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv8i16,
2704        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
2707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
2708        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2709        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2710        GIR_EraseFromParent, /*InsnID*/0,
2711        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2712        // GIR_Coverage, 1165,
2713        GIR_Done,
2714      // Label 128: @5407
2715      GIM_Try, /*On fail goto*//*Label 129*/ 5477, // Rule ID 2677 //
2716        GIM_CheckFeatures, GIFBS_HasNEON,
2717        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2718        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2719        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2720        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2721        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2722        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2723        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2724        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2726        GIM_CheckIsSafeToFold, /*InsnID*/1,
2727        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1016:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2728        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
2729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2733        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2734        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2735        GIR_EraseFromParent, /*InsnID*/0,
2736        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2737        // GIR_Coverage, 2677,
2738        GIR_Done,
2739      // Label 129: @5477
2740      GIM_Try, /*On fail goto*//*Label 130*/ 5547, // Rule ID 2683 //
2741        GIM_CheckFeatures, GIFBS_HasNEON,
2742        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2743        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2744        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2745        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2746        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2747        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2748        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2749        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2751        GIM_CheckIsSafeToFold, /*InsnID*/1,
2752        // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 1017:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2753        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
2754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2757        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2758        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2759        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2760        GIR_EraseFromParent, /*InsnID*/0,
2761        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2762        // GIR_Coverage, 2683,
2763        GIR_Done,
2764      // Label 130: @5547
2765      GIM_Try, /*On fail goto*//*Label 131*/ 5617, // Rule ID 1154 //
2766        GIM_CheckFeatures, GIFBS_HasNEON,
2767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2768        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2769        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2770        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2771        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
2772        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2773        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2774        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2775        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2776        GIM_CheckIsSafeToFold, /*InsnID*/1,
2777        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1016:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2778        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv8i16,
2779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2783        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2784        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2785        GIR_EraseFromParent, /*InsnID*/0,
2786        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2787        // GIR_Coverage, 1154,
2788        GIR_Done,
2789      // Label 131: @5617
2790      GIM_Try, /*On fail goto*//*Label 132*/ 5687, // Rule ID 1160 //
2791        GIM_CheckFeatures, GIFBS_HasNEON,
2792        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2793        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2794        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
2795        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
2796        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
2797        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2798        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
2799        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2800        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
2801        GIM_CheckIsSafeToFold, /*InsnID*/1,
2802        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1017:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2803        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv8i16,
2804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
2807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
2808        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2809        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2810        GIR_EraseFromParent, /*InsnID*/0,
2811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2812        // GIR_Coverage, 1160,
2813        GIR_Done,
2814      // Label 132: @5687
2815      GIM_Try, /*On fail goto*//*Label 133*/ 5751, // Rule ID 766 //
2816        GIM_CheckFeatures, GIFBS_HasNEON,
2817        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2818        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2819        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2820        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2821        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2822        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
2823        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
2824        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2825        GIM_CheckIsSafeToFold, /*InsnID*/1,
2826        GIM_CheckIsSafeToFold, /*InsnID*/2,
2827        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2828        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv8i16,
2829        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2832        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2833        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2834        GIR_EraseFromParent, /*InsnID*/0,
2835        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2836        // GIR_Coverage, 766,
2837        GIR_Done,
2838      // Label 133: @5751
2839      GIM_Try, /*On fail goto*//*Label 134*/ 5815, // Rule ID 769 //
2840        GIM_CheckFeatures, GIFBS_HasNEON,
2841        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2842        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2843        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2844        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2845        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
2846        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
2847        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
2848        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2849        GIM_CheckIsSafeToFold, /*InsnID*/1,
2850        GIM_CheckIsSafeToFold, /*InsnID*/2,
2851        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2852        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv8i16,
2853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
2856        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2857        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2858        GIR_EraseFromParent, /*InsnID*/0,
2859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2860        // GIR_Coverage, 769,
2861        GIR_Done,
2862      // Label 134: @5815
2863      GIM_Try, /*On fail goto*//*Label 135*/ 5878, // Rule ID 2607 //
2864        GIM_CheckFeatures, GIFBS_HasNEON,
2865        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2866        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2867        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2868        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2869        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2870        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2872        GIM_CheckIsSafeToFold, /*InsnID*/1,
2873        // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2874        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
2875        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
2877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2879        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2880        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2881        GIR_EraseFromParent, /*InsnID*/0,
2882        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2883        // GIR_Coverage, 2607,
2884        GIR_Done,
2885      // Label 135: @5878
2886      GIM_Try, /*On fail goto*//*Label 136*/ 5929, // Rule ID 2579 //
2887        GIM_CheckFeatures, GIFBS_HasNEON,
2888        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2889        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2890        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2891        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2893        GIM_CheckIsSafeToFold, /*InsnID*/1,
2894        // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2895        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
2896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2899        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2900        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2901        GIR_EraseFromParent, /*InsnID*/0,
2902        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2903        // GIR_Coverage, 2579,
2904        GIR_Done,
2905      // Label 136: @5929
2906      GIM_Try, /*On fail goto*//*Label 137*/ 5980, // Rule ID 2582 //
2907        GIM_CheckFeatures, GIFBS_HasNEON,
2908        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2909        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2910        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2911        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2913        GIM_CheckIsSafeToFold, /*InsnID*/1,
2914        // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn)  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2915        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
2916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
2918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2919        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2920        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2921        GIR_EraseFromParent, /*InsnID*/0,
2922        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2923        // GIR_Coverage, 2582,
2924        GIR_Done,
2925      // Label 137: @5980
2926      GIM_Try, /*On fail goto*//*Label 138*/ 6043, // Rule ID 877 //
2927        GIM_CheckFeatures, GIFBS_HasNEON,
2928        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2929        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2930        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
2931        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2932        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
2933        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2934        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2935        GIM_CheckIsSafeToFold, /*InsnID*/1,
2936        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2937        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv8i16,
2938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
2940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2942        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2943        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2944        GIR_EraseFromParent, /*InsnID*/0,
2945        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2946        // GIR_Coverage, 877,
2947        GIR_Done,
2948      // Label 138: @6043
2949      GIM_Try, /*On fail goto*//*Label 139*/ 6094, // Rule ID 772 //
2950        GIM_CheckFeatures, GIFBS_HasNEON,
2951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2952        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2953        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
2954        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2955        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2956        GIM_CheckIsSafeToFold, /*InsnID*/1,
2957        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv8i16,
2959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2962        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2963        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2964        GIR_EraseFromParent, /*InsnID*/0,
2965        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2966        // GIR_Coverage, 772,
2967        GIR_Done,
2968      // Label 139: @6094
2969      GIM_Try, /*On fail goto*//*Label 140*/ 6145, // Rule ID 775 //
2970        GIM_CheckFeatures, GIFBS_HasNEON,
2971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2972        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2973        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
2974        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2975        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
2976        GIM_CheckIsSafeToFold, /*InsnID*/1,
2977        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2978        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv8i16,
2979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
2982        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2983        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
2984        GIR_EraseFromParent, /*InsnID*/0,
2985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
2986        // GIR_Coverage, 775,
2987        GIR_Done,
2988      // Label 140: @6145
2989      GIM_Try, /*On fail goto*//*Label 141*/ 6183, // Rule ID 758 //
2990        GIM_CheckFeatures, GIFBS_HasNEON,
2991        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
2992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
2993        // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
2994        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv8i16,
2995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
2996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
2997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
2998        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
2999        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3000        GIR_EraseFromParent, /*InsnID*/0,
3001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3002        // GIR_Coverage, 758,
3003        GIR_Done,
3004      // Label 141: @6183
3005      GIM_Reject,
3006    // Label 124: @6184
3007    GIM_Reject,
3008    // Label 42: @6185
3009    GIM_Try, /*On fail goto*//*Label 142*/ 6644,
3010      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3011      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3012      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3013      GIM_Try, /*On fail goto*//*Label 143*/ 6269, // Rule ID 2676 //
3014        GIM_CheckFeatures, GIFBS_HasNEON,
3015        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3016        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3017        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3018        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3019        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3020        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3021        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3022        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3024        GIM_CheckIsSafeToFold, /*InsnID*/1,
3025        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1016:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3026        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3031        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3032        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3033        GIR_EraseFromParent, /*InsnID*/0,
3034        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3035        // GIR_Coverage, 2676,
3036        GIR_Done,
3037      // Label 143: @6269
3038      GIM_Try, /*On fail goto*//*Label 144*/ 6339, // Rule ID 2682 //
3039        GIM_CheckFeatures, GIFBS_HasNEON,
3040        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3041        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3042        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3043        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3044        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3045        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3046        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3047        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3048        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3049        GIM_CheckIsSafeToFold, /*InsnID*/1,
3050        // (add:{ *:[v16i8] } (intrinsic_wo_chain:{ *:[v16i8] } 1017:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3051        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3052        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3053        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3056        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3057        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3058        GIR_EraseFromParent, /*InsnID*/0,
3059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3060        // GIR_Coverage, 2682,
3061        GIR_Done,
3062      // Label 144: @6339
3063      GIM_Try, /*On fail goto*//*Label 145*/ 6409, // Rule ID 1153 //
3064        GIM_CheckFeatures, GIFBS_HasNEON,
3065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3066        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3067        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3068        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3069        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
3070        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3071        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3072        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3073        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3074        GIM_CheckIsSafeToFold, /*InsnID*/1,
3075        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1016:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3076        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv16i8,
3077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3081        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3082        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3083        GIR_EraseFromParent, /*InsnID*/0,
3084        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3085        // GIR_Coverage, 1153,
3086        GIR_Done,
3087      // Label 145: @6409
3088      GIM_Try, /*On fail goto*//*Label 146*/ 6479, // Rule ID 1159 //
3089        GIM_CheckFeatures, GIFBS_HasNEON,
3090        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3091        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3092        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
3093        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
3094        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
3095        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3096        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
3097        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3098        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
3099        GIM_CheckIsSafeToFold, /*InsnID*/1,
3100        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (intrinsic_wo_chain:{ *:[v16i8] } 1017:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3101        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv16i8,
3102        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
3105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
3106        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3107        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3108        GIR_EraseFromParent, /*InsnID*/0,
3109        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3110        // GIR_Coverage, 1159,
3111        GIR_Done,
3112      // Label 146: @6479
3113      GIM_Try, /*On fail goto*//*Label 147*/ 6542, // Rule ID 2606 //
3114        GIM_CheckFeatures, GIFBS_HasNEON,
3115        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3116        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3117        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3118        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3119        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3120        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3122        GIM_CheckIsSafeToFold, /*InsnID*/1,
3123        // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1)  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3124        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
3127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3129        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3130        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3131        GIR_EraseFromParent, /*InsnID*/0,
3132        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3133        // GIR_Coverage, 2606,
3134        GIR_Done,
3135      // Label 147: @6542
3136      GIM_Try, /*On fail goto*//*Label 148*/ 6605, // Rule ID 876 //
3137        GIM_CheckFeatures, GIFBS_HasNEON,
3138        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3139        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3140        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3141        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3142        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3143        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3144        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3145        GIM_CheckIsSafeToFold, /*InsnID*/1,
3146        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3147        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv16i8,
3148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3152        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3153        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3154        GIR_EraseFromParent, /*InsnID*/0,
3155        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3156        // GIR_Coverage, 876,
3157        GIR_Done,
3158      // Label 148: @6605
3159      GIM_Try, /*On fail goto*//*Label 149*/ 6643, // Rule ID 757 //
3160        GIM_CheckFeatures, GIFBS_HasNEON,
3161        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3163        // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3164        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv16i8,
3165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3168        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3169        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3170        GIR_EraseFromParent, /*InsnID*/0,
3171        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3172        // GIR_Coverage, 757,
3173        GIR_Done,
3174      // Label 149: @6643
3175      GIM_Reject,
3176    // Label 142: @6644
3177    GIM_Reject,
3178    // Label 43: @6645
3179    GIM_Reject,
3180    // Label 1: @6646
3181    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 159*/ 8635,
3182    /*GILLT_s32*//*Label 150*/ 6661,
3183    /*GILLT_s64*//*Label 151*/ 7154,
3184    /*GILLT_v2s32*//*Label 152*/ 7205,
3185    /*GILLT_v2s64*//*Label 153*/ 7318,
3186    /*GILLT_v4s16*//*Label 154*/ 7602,
3187    /*GILLT_v4s32*//*Label 155*/ 7715,
3188    /*GILLT_v8s8*//*Label 156*/ 8062,
3189    /*GILLT_v8s16*//*Label 157*/ 8175,
3190    /*GILLT_v16s8*//*Label 158*/ 8522,
3191    // Label 150: @6661
3192    GIM_Try, /*On fail goto*//*Label 160*/ 7153,
3193      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3194      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3195      GIM_Try, /*On fail goto*//*Label 161*/ 6723, // Rule ID 98 //
3196        GIM_CheckFeatures, GIFBS_IsARM,
3197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3198        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3199        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3200        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3201        // MIs[1] Operand 1
3202        // No operand predicates
3203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3204        GIM_CheckIsSafeToFold, /*InsnID*/1,
3205        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn)  =>  (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3206        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::RSBri,
3207        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3209        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3210        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3211        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3212        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3213        GIR_EraseFromParent, /*InsnID*/0,
3214        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3215        // GIR_Coverage, 98,
3216        GIR_Done,
3217      // Label 161: @6723
3218      GIM_Try, /*On fail goto*//*Label 162*/ 6775, // Rule ID 431 //
3219        GIM_CheckFeatures, GIFBS_IsThumb2,
3220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3221        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3222        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3223        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3224        // MIs[1] Operand 1
3225        // No operand predicates
3226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3227        GIM_CheckIsSafeToFold, /*InsnID*/1,
3228        // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn)  =>  (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2RSBri,
3230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
3232        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3233        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3234        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3235        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3236        GIR_EraseFromParent, /*InsnID*/0,
3237        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3238        // GIR_Coverage, 431,
3239        GIR_Done,
3240      // Label 162: @6775
3241      GIM_Try, /*On fail goto*//*Label 163*/ 6827, // Rule ID 78 //
3242        GIM_CheckFeatures, GIFBS_IsARM,
3243        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3244        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3245        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3246        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3247        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
3248        // MIs[1] Operand 1
3249        // No operand predicates
3250        GIM_CheckIsSafeToFold, /*InsnID*/1,
3251        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3252        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBri,
3253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3254        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3255        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3256        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3257        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3258        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3259        GIR_EraseFromParent, /*InsnID*/0,
3260        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3261        // GIR_Coverage, 78,
3262        GIR_Done,
3263      // Label 163: @6827
3264      GIM_Try, /*On fail goto*//*Label 164*/ 6879, // Rule ID 415 //
3265        GIM_CheckFeatures, GIFBS_IsThumb2,
3266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3268        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3269        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3270        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
3271        // MIs[1] Operand 1
3272        // No operand predicates
3273        GIM_CheckIsSafeToFold, /*InsnID*/1,
3274        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3275        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri,
3276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3278        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3279        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3280        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3281        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3282        GIR_EraseFromParent, /*InsnID*/0,
3283        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3284        // GIR_Coverage, 415,
3285        GIR_Done,
3286      // Label 164: @6879
3287      GIM_Try, /*On fail goto*//*Label 165*/ 6928, // Rule ID 416 //
3288        GIM_CheckFeatures, GIFBS_IsThumb2,
3289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3291        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3292        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
3293        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
3294        // MIs[1] Operand 1
3295        // No operand predicates
3296        GIM_CheckIsSafeToFold, /*InsnID*/1,
3297        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm)  =>  (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
3298        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12,
3299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3301        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
3302        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3303        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3304        GIR_EraseFromParent, /*InsnID*/0,
3305        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3306        // GIR_Coverage, 416,
3307        GIR_Done,
3308      // Label 165: @6928
3309      GIM_Try, /*On fail goto*//*Label 166*/ 6995, // Rule ID 175 //
3310        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM_UseMulOps,
3311        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3312        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3313        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3314        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3315        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3316        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3317        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3318        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3319        GIM_CheckIsSafeToFold, /*InsnID*/1,
3320        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm))  =>  (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
3321        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLS,
3322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3326        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3327        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3328        GIR_EraseFromParent, /*InsnID*/0,
3329        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3330        // GIR_Coverage, 175,
3331        GIR_Done,
3332      // Label 166: @6995
3333      GIM_Try, /*On fail goto*//*Label 167*/ 7062, // Rule ID 508 //
3334        GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
3335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
3336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3337        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3338        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3339        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
3340        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
3341        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
3342        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3343        GIM_CheckIsSafeToFold, /*InsnID*/1,
3344        // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm))  =>  (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
3345        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLS,
3346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
3348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
3349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
3350        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3351        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3352        GIR_EraseFromParent, /*InsnID*/0,
3353        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3354        // GIR_Coverage, 508,
3355        GIR_Done,
3356      // Label 167: @7062
3357      GIM_Try, /*On fail goto*//*Label 168*/ 7107, // Rule ID 79 //
3358        GIM_CheckFeatures, GIFBS_IsARM,
3359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
3360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
3361        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
3362        // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
3363        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SUBrr,
3364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3367        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3368        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3369        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3370        GIR_EraseFromParent, /*InsnID*/0,
3371        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3372        // GIR_Coverage, 79,
3373        GIR_Done,
3374      // Label 168: @7107
3375      GIM_Try, /*On fail goto*//*Label 169*/ 7152, // Rule ID 417 //
3376        GIM_CheckFeatures, GIFBS_IsThumb2,
3377        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
3378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
3379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
3380        // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
3381        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBrr,
3382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
3383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
3384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
3385        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3386        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3387        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3388        GIR_EraseFromParent, /*InsnID*/0,
3389        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3390        // GIR_Coverage, 417,
3391        GIR_Done,
3392      // Label 169: @7152
3393      GIM_Reject,
3394    // Label 160: @7153
3395    GIM_Reject,
3396    // Label 151: @7154
3397    GIM_Try, /*On fail goto*//*Label 170*/ 7204, // Rule ID 947 //
3398      GIM_CheckFeatures, GIFBS_HasNEON,
3399      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
3400      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
3401      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3402      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3403      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3404      // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
3405      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv1i64,
3406      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3407      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3408      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3409      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3410      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3411      GIR_EraseFromParent, /*InsnID*/0,
3412      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3413      // GIR_Coverage, 947,
3414      GIR_Done,
3415    // Label 170: @7204
3416    GIM_Reject,
3417    // Label 152: @7205
3418    GIM_Try, /*On fail goto*//*Label 171*/ 7317,
3419      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
3420      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
3421      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3422      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3423      GIM_Try, /*On fail goto*//*Label 172*/ 7282, // Rule ID 903 //
3424        GIM_CheckFeatures, GIFBS_HasNEON,
3425        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3426        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3427        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3428        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3429        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3430        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3431        GIM_CheckIsSafeToFold, /*InsnID*/1,
3432        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3433        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv2i32,
3434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3438        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3439        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3440        GIR_EraseFromParent, /*InsnID*/0,
3441        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3442        // GIR_Coverage, 903,
3443        GIR_Done,
3444      // Label 172: @7282
3445      GIM_Try, /*On fail goto*//*Label 173*/ 7316, // Rule ID 943 //
3446        GIM_CheckFeatures, GIFBS_HasNEON,
3447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3448        // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3449        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i32,
3450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3453        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3454        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3455        GIR_EraseFromParent, /*InsnID*/0,
3456        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3457        // GIR_Coverage, 943,
3458        GIR_Done,
3459      // Label 173: @7316
3460      GIM_Reject,
3461    // Label 171: @7317
3462    GIM_Reject,
3463    // Label 153: @7318
3464    GIM_Try, /*On fail goto*//*Label 174*/ 7601,
3465      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
3466      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
3467      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3468      GIM_Try, /*On fail goto*//*Label 175*/ 7396, // Rule ID 955 //
3469        GIM_CheckFeatures, GIFBS_HasNEON,
3470        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3471        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3472        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3473        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3474        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3475        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3476        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3477        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3478        GIM_CheckIsSafeToFold, /*InsnID*/1,
3479        GIM_CheckIsSafeToFold, /*InsnID*/2,
3480        // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3481        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv2i64,
3482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3485        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3486        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3487        GIR_EraseFromParent, /*InsnID*/0,
3488        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3489        // GIR_Coverage, 955,
3490        GIR_Done,
3491      // Label 175: @7396
3492      GIM_Try, /*On fail goto*//*Label 176*/ 7460, // Rule ID 958 //
3493        GIM_CheckFeatures, GIFBS_HasNEON,
3494        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3495        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3496        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3497        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3498        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3499        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3500        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3501        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3502        GIM_CheckIsSafeToFold, /*InsnID*/1,
3503        GIM_CheckIsSafeToFold, /*InsnID*/2,
3504        // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3505        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv2i64,
3506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3508        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3509        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3510        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3511        GIR_EraseFromParent, /*InsnID*/0,
3512        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3513        // GIR_Coverage, 958,
3514        GIR_Done,
3515      // Label 176: @7460
3516      GIM_Try, /*On fail goto*//*Label 177*/ 7511, // Rule ID 961 //
3517        GIM_CheckFeatures, GIFBS_HasNEON,
3518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3519        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3520        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3521        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3522        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3523        GIM_CheckIsSafeToFold, /*InsnID*/1,
3524        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3525        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv2i64,
3526        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3529        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3530        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3531        GIR_EraseFromParent, /*InsnID*/0,
3532        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3533        // GIR_Coverage, 961,
3534        GIR_Done,
3535      // Label 177: @7511
3536      GIM_Try, /*On fail goto*//*Label 178*/ 7562, // Rule ID 964 //
3537        GIM_CheckFeatures, GIFBS_HasNEON,
3538        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3539        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3540        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3541        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3542        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3543        GIM_CheckIsSafeToFold, /*InsnID*/1,
3544        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm))  =>  (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3545        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv2i64,
3546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3549        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3550        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3551        GIR_EraseFromParent, /*InsnID*/0,
3552        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3553        // GIR_Coverage, 964,
3554        GIR_Done,
3555      // Label 178: @7562
3556      GIM_Try, /*On fail goto*//*Label 179*/ 7600, // Rule ID 948 //
3557        GIM_CheckFeatures, GIFBS_HasNEON,
3558        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3560        // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
3561        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv2i64,
3562        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3565        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3566        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3567        GIR_EraseFromParent, /*InsnID*/0,
3568        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3569        // GIR_Coverage, 948,
3570        GIR_Done,
3571      // Label 179: @7600
3572      GIM_Reject,
3573    // Label 174: @7601
3574    GIM_Reject,
3575    // Label 154: @7602
3576    GIM_Try, /*On fail goto*//*Label 180*/ 7714,
3577      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
3578      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
3579      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3580      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3581      GIM_Try, /*On fail goto*//*Label 181*/ 7679, // Rule ID 902 //
3582        GIM_CheckFeatures, GIFBS_HasNEON,
3583        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3584        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3585        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3586        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3587        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3588        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3589        GIM_CheckIsSafeToFold, /*InsnID*/1,
3590        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3591        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i16,
3592        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3596        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3597        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3598        GIR_EraseFromParent, /*InsnID*/0,
3599        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3600        // GIR_Coverage, 902,
3601        GIR_Done,
3602      // Label 181: @7679
3603      GIM_Try, /*On fail goto*//*Label 182*/ 7713, // Rule ID 942 //
3604        GIM_CheckFeatures, GIFBS_HasNEON,
3605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3606        // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3607        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i16,
3608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3611        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3612        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3613        GIR_EraseFromParent, /*InsnID*/0,
3614        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3615        // GIR_Coverage, 942,
3616        GIR_Done,
3617      // Label 182: @7713
3618      GIM_Reject,
3619    // Label 180: @7714
3620    GIM_Reject,
3621    // Label 155: @7715
3622    GIM_Try, /*On fail goto*//*Label 183*/ 8061,
3623      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
3624      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
3625      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3626      GIM_Try, /*On fail goto*//*Label 184*/ 7793, // Rule ID 954 //
3627        GIM_CheckFeatures, GIFBS_HasNEON,
3628        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3629        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3630        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3631        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3632        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3633        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3634        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3635        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3636        GIM_CheckIsSafeToFold, /*InsnID*/1,
3637        GIM_CheckIsSafeToFold, /*InsnID*/2,
3638        // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3639        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv4i32,
3640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3643        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3644        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3645        GIR_EraseFromParent, /*InsnID*/0,
3646        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3647        // GIR_Coverage, 954,
3648        GIR_Done,
3649      // Label 184: @7793
3650      GIM_Try, /*On fail goto*//*Label 185*/ 7857, // Rule ID 957 //
3651        GIM_CheckFeatures, GIFBS_HasNEON,
3652        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3653        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3654        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3655        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3656        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3657        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3658        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3659        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3660        GIM_CheckIsSafeToFold, /*InsnID*/1,
3661        GIM_CheckIsSafeToFold, /*InsnID*/2,
3662        // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv4i32,
3664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3667        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3668        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3669        GIR_EraseFromParent, /*InsnID*/0,
3670        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3671        // GIR_Coverage, 957,
3672        GIR_Done,
3673      // Label 185: @7857
3674      GIM_Try, /*On fail goto*//*Label 186*/ 7920, // Rule ID 906 //
3675        GIM_CheckFeatures, GIFBS_HasNEON,
3676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3677        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3678        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3679        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3680        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3681        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3682        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3683        GIM_CheckIsSafeToFold, /*InsnID*/1,
3684        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3685        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv4i32,
3686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3690        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3691        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3692        GIR_EraseFromParent, /*InsnID*/0,
3693        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3694        // GIR_Coverage, 906,
3695        GIR_Done,
3696      // Label 186: @7920
3697      GIM_Try, /*On fail goto*//*Label 187*/ 7971, // Rule ID 960 //
3698        GIM_CheckFeatures, GIFBS_HasNEON,
3699        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3700        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3701        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3702        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3703        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3704        GIM_CheckIsSafeToFold, /*InsnID*/1,
3705        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3706        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv4i32,
3707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3709        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3710        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3711        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3712        GIR_EraseFromParent, /*InsnID*/0,
3713        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3714        // GIR_Coverage, 960,
3715        GIR_Done,
3716      // Label 187: @7971
3717      GIM_Try, /*On fail goto*//*Label 188*/ 8022, // Rule ID 963 //
3718        GIM_CheckFeatures, GIFBS_HasNEON,
3719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3720        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3721        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3722        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3723        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3724        GIM_CheckIsSafeToFold, /*InsnID*/1,
3725        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm))  =>  (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3726        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv4i32,
3727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3730        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3731        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3732        GIR_EraseFromParent, /*InsnID*/0,
3733        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3734        // GIR_Coverage, 963,
3735        GIR_Done,
3736      // Label 188: @8022
3737      GIM_Try, /*On fail goto*//*Label 189*/ 8060, // Rule ID 946 //
3738        GIM_CheckFeatures, GIFBS_HasNEON,
3739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3741        // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3742        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv4i32,
3743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3745        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3746        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3747        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3748        GIR_EraseFromParent, /*InsnID*/0,
3749        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3750        // GIR_Coverage, 946,
3751        GIR_Done,
3752      // Label 189: @8060
3753      GIM_Reject,
3754    // Label 183: @8061
3755    GIM_Reject,
3756    // Label 156: @8062
3757    GIM_Try, /*On fail goto*//*Label 190*/ 8174,
3758      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
3759      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
3760      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
3761      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3762      GIM_Try, /*On fail goto*//*Label 191*/ 8139, // Rule ID 901 //
3763        GIM_CheckFeatures, GIFBS_HasNEON,
3764        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3765        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3766        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3767        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3768        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3769        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3770        GIM_CheckIsSafeToFold, /*InsnID*/1,
3771        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3772        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i8,
3773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3777        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3778        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3779        GIR_EraseFromParent, /*InsnID*/0,
3780        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3781        // GIR_Coverage, 901,
3782        GIR_Done,
3783      // Label 191: @8139
3784      GIM_Try, /*On fail goto*//*Label 192*/ 8173, // Rule ID 941 //
3785        GIM_CheckFeatures, GIFBS_HasNEON,
3786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
3787        // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3788        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i8,
3789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3792        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3793        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3794        GIR_EraseFromParent, /*InsnID*/0,
3795        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3796        // GIR_Coverage, 941,
3797        GIR_Done,
3798      // Label 192: @8173
3799      GIM_Reject,
3800    // Label 190: @8174
3801    GIM_Reject,
3802    // Label 157: @8175
3803    GIM_Try, /*On fail goto*//*Label 193*/ 8521,
3804      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
3805      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
3806      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3807      GIM_Try, /*On fail goto*//*Label 194*/ 8253, // Rule ID 953 //
3808        GIM_CheckFeatures, GIFBS_HasNEON,
3809        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3810        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3811        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3812        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3813        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3814        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
3815        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3816        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3817        GIM_CheckIsSafeToFold, /*InsnID*/1,
3818        GIM_CheckIsSafeToFold, /*InsnID*/2,
3819        // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3820        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLsv8i16,
3821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3822        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3824        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3825        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3826        GIR_EraseFromParent, /*InsnID*/0,
3827        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3828        // GIR_Coverage, 953,
3829        GIR_Done,
3830      // Label 194: @8253
3831      GIM_Try, /*On fail goto*//*Label 195*/ 8317, // Rule ID 956 //
3832        GIM_CheckFeatures, GIFBS_HasNEON,
3833        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3834        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3835        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3836        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3837        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3838        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
3839        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3840        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3841        GIM_CheckIsSafeToFold, /*InsnID*/1,
3842        GIM_CheckIsSafeToFold, /*InsnID*/2,
3843        // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3844        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBLuv8i16,
3845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3848        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3849        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3850        GIR_EraseFromParent, /*InsnID*/0,
3851        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3852        // GIR_Coverage, 956,
3853        GIR_Done,
3854      // Label 195: @8317
3855      GIM_Try, /*On fail goto*//*Label 196*/ 8380, // Rule ID 905 //
3856        GIM_CheckFeatures, GIFBS_HasNEON,
3857        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3858        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3859        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3860        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3861        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3862        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3863        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3864        GIM_CheckIsSafeToFold, /*InsnID*/1,
3865        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3866        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv8i16,
3867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3871        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3872        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3873        GIR_EraseFromParent, /*InsnID*/0,
3874        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3875        // GIR_Coverage, 905,
3876        GIR_Done,
3877      // Label 196: @8380
3878      GIM_Try, /*On fail goto*//*Label 197*/ 8431, // Rule ID 959 //
3879        GIM_CheckFeatures, GIFBS_HasNEON,
3880        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3881        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3882        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
3883        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3884        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3885        GIM_CheckIsSafeToFold, /*InsnID*/1,
3886        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3887        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWsv8i16,
3888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3891        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3892        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3893        GIR_EraseFromParent, /*InsnID*/0,
3894        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3895        // GIR_Coverage, 959,
3896        GIR_Done,
3897      // Label 197: @8431
3898      GIM_Try, /*On fail goto*//*Label 198*/ 8482, // Rule ID 962 //
3899        GIM_CheckFeatures, GIFBS_HasNEON,
3900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3901        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3902        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
3903        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3904        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
3905        GIM_CheckIsSafeToFold, /*InsnID*/1,
3906        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm))  =>  (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3907        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBWuv8i16,
3908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3911        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3912        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3913        GIR_EraseFromParent, /*InsnID*/0,
3914        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3915        // GIR_Coverage, 962,
3916        GIR_Done,
3917      // Label 198: @8482
3918      GIM_Try, /*On fail goto*//*Label 199*/ 8520, // Rule ID 945 //
3919        GIM_CheckFeatures, GIFBS_HasNEON,
3920        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3921        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3922        // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3923        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv8i16,
3924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3927        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3928        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3929        GIR_EraseFromParent, /*InsnID*/0,
3930        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3931        // GIR_Coverage, 945,
3932        GIR_Done,
3933      // Label 199: @8520
3934      GIM_Reject,
3935    // Label 193: @8521
3936    GIM_Reject,
3937    // Label 158: @8522
3938    GIM_Try, /*On fail goto*//*Label 200*/ 8634,
3939      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
3940      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
3941      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
3942      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3943      GIM_Try, /*On fail goto*//*Label 201*/ 8599, // Rule ID 904 //
3944        GIM_CheckFeatures, GIFBS_HasNEON,
3945        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3946        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
3947        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3948        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3949        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
3950        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3951        GIM_CheckIsSafeToFold, /*InsnID*/1,
3952        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm))  =>  (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3953        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLSv16i8,
3954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
3956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3958        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3959        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3960        GIR_EraseFromParent, /*InsnID*/0,
3961        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3962        // GIR_Coverage, 904,
3963        GIR_Done,
3964      // Label 201: @8599
3965      GIM_Try, /*On fail goto*//*Label 202*/ 8633, // Rule ID 944 //
3966        GIM_CheckFeatures, GIFBS_HasNEON,
3967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
3968        // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3969        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBv16i8,
3970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
3971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
3972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
3973        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
3974        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
3975        GIR_EraseFromParent, /*InsnID*/0,
3976        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
3977        // GIR_Coverage, 944,
3978        GIR_Done,
3979      // Label 202: @8633
3980      GIM_Reject,
3981    // Label 200: @8634
3982    GIM_Reject,
3983    // Label 159: @8635
3984    GIM_Reject,
3985    // Label 2: @8636
3986    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 210*/ 9269,
3987    /*GILLT_s32*//*Label 203*/ 8651, 0,
3988    /*GILLT_v2s32*//*Label 204*/ 8963, 0,
3989    /*GILLT_v4s16*//*Label 205*/ 9014,
3990    /*GILLT_v4s32*//*Label 206*/ 9065,
3991    /*GILLT_v8s8*//*Label 207*/ 9116,
3992    /*GILLT_v8s16*//*Label 208*/ 9167,
3993    /*GILLT_v16s8*//*Label 209*/ 9218,
3994    // Label 203: @8651
3995    GIM_Try, /*On fail goto*//*Label 211*/ 8962,
3996      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
3997      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
3998      GIM_Try, /*On fail goto*//*Label 212*/ 8745, // Rule ID 188 //
3999        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
4000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4001        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4002        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4003        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4004        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4005        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4006        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4007        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4008        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4009        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4010        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4011        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4012        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4013        GIM_CheckIsSafeToFold, /*InsnID*/1,
4014        GIM_CheckIsSafeToFold, /*InsnID*/2,
4015        // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4016        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
4017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4020        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4021        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4022        GIR_EraseFromParent, /*InsnID*/0,
4023        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4024        // GIR_Coverage, 188,
4025        GIR_Done,
4026      // Label 212: @8745
4027      GIM_Try, /*On fail goto*//*Label 213*/ 8829, // Rule ID 519 //
4028        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4029        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4030        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4031        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4032        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4033        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4034        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4035        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
4036        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4037        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4038        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
4039        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
4040        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4041        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
4042        GIM_CheckIsSafeToFold, /*InsnID*/1,
4043        GIM_CheckIsSafeToFold, /*InsnID*/2,
4044        // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4045        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
4046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
4049        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4050        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4051        GIR_EraseFromParent, /*InsnID*/0,
4052        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4053        // GIR_Coverage, 519,
4054        GIR_Done,
4055      // Label 213: @8829
4056      GIM_Try, /*On fail goto*//*Label 214*/ 8874, // Rule ID 171 //
4057        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4061        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4062        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MUL,
4063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4066        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4067        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4068        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4069        GIR_EraseFromParent, /*InsnID*/0,
4070        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4071        // GIR_Coverage, 171,
4072        GIR_Done,
4073      // Label 214: @8874
4074      GIM_Try, /*On fail goto*//*Label 215*/ 8919, // Rule ID 172 //
4075        GIM_CheckFeatures, GIFBS_IsARM_NoV6_UseMulOps,
4076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
4078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
4079        // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
4080        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MULv5,
4081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4082        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4084        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4085        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4086        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4087        GIR_EraseFromParent, /*InsnID*/0,
4088        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4089        // GIR_Coverage, 172,
4090        GIR_Done,
4091      // Label 215: @8919
4092      GIM_Try, /*On fail goto*//*Label 216*/ 8961, // Rule ID 506 //
4093        GIM_CheckFeatures, GIFBS_IsThumb2,
4094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4095        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4096        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4097        // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4098        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MUL,
4099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4102        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4103        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4104        GIR_EraseFromParent, /*InsnID*/0,
4105        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4106        // GIR_Coverage, 506,
4107        GIR_Done,
4108      // Label 216: @8961
4109      GIM_Reject,
4110    // Label 211: @8962
4111    GIM_Reject,
4112    // Label 204: @8963
4113    GIM_Try, /*On fail goto*//*Label 217*/ 9013, // Rule ID 823 //
4114      GIM_CheckFeatures, GIFBS_HasNEON,
4115      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4116      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4117      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4118      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4119      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4120      // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4121      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv2i32,
4122      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4123      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4124      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4125      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4126      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4127      GIR_EraseFromParent, /*InsnID*/0,
4128      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4129      // GIR_Coverage, 823,
4130      GIR_Done,
4131    // Label 217: @9013
4132    GIM_Reject,
4133    // Label 205: @9014
4134    GIM_Try, /*On fail goto*//*Label 218*/ 9064, // Rule ID 822 //
4135      GIM_CheckFeatures, GIFBS_HasNEON,
4136      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
4137      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
4138      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4139      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4140      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4141      // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4142      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i16,
4143      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4144      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4145      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4146      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4147      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4148      GIR_EraseFromParent, /*InsnID*/0,
4149      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4150      // GIR_Coverage, 822,
4151      GIR_Done,
4152    // Label 218: @9064
4153    GIM_Reject,
4154    // Label 206: @9065
4155    GIM_Try, /*On fail goto*//*Label 219*/ 9115, // Rule ID 826 //
4156      GIM_CheckFeatures, GIFBS_HasNEON,
4157      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4158      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4159      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4160      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4161      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4162      // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4163      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv4i32,
4164      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4165      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4166      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4167      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4168      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4169      GIR_EraseFromParent, /*InsnID*/0,
4170      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4171      // GIR_Coverage, 826,
4172      GIR_Done,
4173    // Label 219: @9115
4174    GIM_Reject,
4175    // Label 207: @9116
4176    GIM_Try, /*On fail goto*//*Label 220*/ 9166, // Rule ID 821 //
4177      GIM_CheckFeatures, GIFBS_HasNEON,
4178      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
4179      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
4180      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4181      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4182      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4183      // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4184      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i8,
4185      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4186      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4187      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4188      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4189      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4190      GIR_EraseFromParent, /*InsnID*/0,
4191      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4192      // GIR_Coverage, 821,
4193      GIR_Done,
4194    // Label 220: @9166
4195    GIM_Reject,
4196    // Label 208: @9167
4197    GIM_Try, /*On fail goto*//*Label 221*/ 9217, // Rule ID 825 //
4198      GIM_CheckFeatures, GIFBS_HasNEON,
4199      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
4200      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
4201      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4202      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4203      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4204      // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4205      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv8i16,
4206      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4207      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4208      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4209      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4210      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4211      GIR_EraseFromParent, /*InsnID*/0,
4212      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4213      // GIR_Coverage, 825,
4214      GIR_Done,
4215    // Label 221: @9217
4216    GIM_Reject,
4217    // Label 209: @9218
4218    GIM_Try, /*On fail goto*//*Label 222*/ 9268, // Rule ID 824 //
4219      GIM_CheckFeatures, GIFBS_HasNEON,
4220      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
4221      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
4222      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4223      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4224      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4225      // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4226      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULv16i8,
4227      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4228      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4229      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4230      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4231      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4232      GIR_EraseFromParent, /*InsnID*/0,
4233      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4234      // GIR_Coverage, 824,
4235      GIR_Done,
4236    // Label 222: @9268
4237    GIM_Reject,
4238    // Label 210: @9269
4239    GIM_Reject,
4240    // Label 3: @9270
4241    GIM_Try, /*On fail goto*//*Label 223*/ 9369,
4242      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4243      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4244      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4245      GIM_Try, /*On fail goto*//*Label 224*/ 9326, // Rule ID 197 //
4246        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4249        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4250        // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4251        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SDIV,
4252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4254        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4255        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4256        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4257        GIR_EraseFromParent, /*InsnID*/0,
4258        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4259        // GIR_Coverage, 197,
4260        GIR_Done,
4261      // Label 224: @9326
4262      GIM_Try, /*On fail goto*//*Label 225*/ 9368, // Rule ID 536 //
4263        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4264        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4267        // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4268        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SDIV,
4269        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4272        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4273        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4274        GIR_EraseFromParent, /*InsnID*/0,
4275        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4276        // GIR_Coverage, 536,
4277        GIR_Done,
4278      // Label 225: @9368
4279      GIM_Reject,
4280    // Label 223: @9369
4281    GIM_Reject,
4282    // Label 4: @9370
4283    GIM_Try, /*On fail goto*//*Label 226*/ 9469,
4284      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
4285      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4286      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4287      GIM_Try, /*On fail goto*//*Label 227*/ 9426, // Rule ID 198 //
4288        GIM_CheckFeatures, GIFBS_HasDivideInARM_IsARM,
4289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4292        // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4293        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDIV,
4294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4297        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4298        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4299        GIR_EraseFromParent, /*InsnID*/0,
4300        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4301        // GIR_Coverage, 198,
4302        GIR_Done,
4303      // Label 227: @9426
4304      GIM_Try, /*On fail goto*//*Label 228*/ 9468, // Rule ID 537 //
4305        GIM_CheckFeatures, GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
4306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4309        // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4310        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDIV,
4311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4314        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4315        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4316        GIR_EraseFromParent, /*InsnID*/0,
4317        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4318        // GIR_Coverage, 537,
4319        GIR_Done,
4320      // Label 228: @9468
4321      GIM_Reject,
4322    // Label 226: @9469
4323    GIM_Reject,
4324    // Label 5: @9470
4325    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 232*/ 11182,
4326    /*GILLT_s32*//*Label 229*/ 9482, 0,
4327    /*GILLT_v2s32*//*Label 230*/ 11080, 0, 0,
4328    /*GILLT_v4s32*//*Label 231*/ 11131,
4329    // Label 229: @9482
4330    GIM_Try, /*On fail goto*//*Label 233*/ 11079,
4331      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
4332      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
4333      GIM_Try, /*On fail goto*//*Label 234*/ 9554, // Rule ID 1707 //
4334        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4336        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4337        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4338        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4339        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4340        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4341        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4342        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4343        GIM_CheckIsSafeToFold, /*InsnID*/1,
4344        // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4345        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4347        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4348        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4349        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4350        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4351        GIR_EraseFromParent, /*InsnID*/0,
4352        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4353        // GIR_Coverage, 1707,
4354        GIR_Done,
4355      // Label 234: @9554
4356      GIM_Try, /*On fail goto*//*Label 235*/ 9616, // Rule ID 1909 //
4357        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4359        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4360        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
4361        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4362        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4363        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4364        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 8,
4365        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4366        GIM_CheckIsSafeToFold, /*InsnID*/1,
4367        // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
4368        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
4371        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
4372        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4373        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4374        GIR_EraseFromParent, /*InsnID*/0,
4375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4376        // GIR_Coverage, 1909,
4377        GIR_Done,
4378      // Label 235: @9616
4379      GIM_Try, /*On fail goto*//*Label 236*/ 9657, // Rule ID 1810 //
4380        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4383        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4384        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] })  =>  (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4385        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB,
4386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4388        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4389        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4390        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4391        GIR_EraseFromParent, /*InsnID*/0,
4392        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4393        // GIR_Coverage, 1810,
4394        GIR_Done,
4395      // Label 236: @9657
4396      GIM_Try, /*On fail goto*//*Label 237*/ 9698, // Rule ID 1811 //
4397        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4400        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4401        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] })  =>  (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4402        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTH,
4403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4405        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4406        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4407        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4408        GIR_EraseFromParent, /*InsnID*/0,
4409        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4410        // GIR_Coverage, 1811,
4411        GIR_Done,
4412      // Label 237: @9698
4413      GIM_Try, /*On fail goto*//*Label 238*/ 9739, // Rule ID 1812 //
4414        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
4415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
4416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4417        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4418        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] })  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
4419        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
4420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Src
4422        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4423        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4424        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4425        GIR_EraseFromParent, /*InsnID*/0,
4426        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4427        // GIR_Coverage, 1812,
4428        GIR_Done,
4429      // Label 238: @9739
4430      GIM_Try, /*On fail goto*//*Label 239*/ 9780, // Rule ID 1996 //
4431        GIM_CheckFeatures, GIFBS_IsThumb2,
4432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4433        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4434        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4435        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4436        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB,
4437        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4438        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4439        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4440        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4441        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4442        GIR_EraseFromParent, /*InsnID*/0,
4443        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4444        // GIR_Coverage, 1996,
4445        GIR_Done,
4446      // Label 239: @9780
4447      GIM_Try, /*On fail goto*//*Label 240*/ 9821, // Rule ID 1997 //
4448        GIM_CheckFeatures, GIFBS_IsThumb2,
4449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4451        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4452        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4453        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTH,
4454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4456        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4457        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4458        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4459        GIR_EraseFromParent, /*InsnID*/0,
4460        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4461        // GIR_Coverage, 1997,
4462        GIR_Done,
4463      // Label 240: @9821
4464      GIM_Try, /*On fail goto*//*Label 241*/ 9862, // Rule ID 1998 //
4465        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
4466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4467        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4468        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16711935,
4469        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] })  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
4470        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
4471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4473        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
4474        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4475        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4476        GIR_EraseFromParent, /*InsnID*/0,
4477        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4478        // GIR_Coverage, 1998,
4479        GIR_Done,
4480      // Label 241: @9862
4481      GIM_Try, /*On fail goto*//*Label 242*/ 9935, // Rule ID 2513 //
4482        GIM_CheckFeatures, GIFBS_IsARM,
4483        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4484        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4485        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4486        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4487        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4488        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4489        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4490        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4491        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4492        // MIs[2] Operand 1
4493        // No operand predicates
4494        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4495        GIM_CheckIsSafeToFold, /*InsnID*/1,
4496        GIM_CheckIsSafeToFold, /*InsnID*/2,
4497        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4498        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4501        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4502        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4503        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4504        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4505        GIR_EraseFromParent, /*InsnID*/0,
4506        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4507        // GIR_Coverage, 2513,
4508        GIR_Done,
4509      // Label 242: @9935
4510      GIM_Try, /*On fail goto*//*Label 243*/ 10008, // Rule ID 2546 //
4511        GIM_CheckFeatures, GIFBS_IsThumb2,
4512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4513        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4514        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4515        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4516        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4517        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4518        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4519        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4520        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4521        // MIs[2] Operand 1
4522        // No operand predicates
4523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4524        GIM_CheckIsSafeToFold, /*InsnID*/1,
4525        GIM_CheckIsSafeToFold, /*InsnID*/2,
4526        // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4527        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4530        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4531        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4532        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4533        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4534        GIR_EraseFromParent, /*InsnID*/0,
4535        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4536        // GIR_Coverage, 2546,
4537        GIR_Done,
4538      // Label 243: @10008
4539      GIM_Try, /*On fail goto*//*Label 244*/ 10081, // Rule ID 2512 //
4540        GIM_CheckFeatures, GIFBS_IsARM,
4541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4542        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4543        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4544        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4545        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4546        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4547        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4548        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4549        // MIs[2] Operand 1
4550        // No operand predicates
4551        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4552        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4553        GIM_CheckIsSafeToFold, /*InsnID*/1,
4554        GIM_CheckIsSafeToFold, /*InsnID*/2,
4555        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4556        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4557        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4559        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4560        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4561        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4562        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4563        GIR_EraseFromParent, /*InsnID*/0,
4564        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4565        // GIR_Coverage, 2512,
4566        GIR_Done,
4567      // Label 244: @10081
4568      GIM_Try, /*On fail goto*//*Label 245*/ 10154, // Rule ID 2545 //
4569        GIM_CheckFeatures, GIFBS_IsThumb2,
4570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4571        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4572        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4573        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4574        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4575        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4576        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4577        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4578        // MIs[2] Operand 1
4579        // No operand predicates
4580        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4582        GIM_CheckIsSafeToFold, /*InsnID*/1,
4583        GIM_CheckIsSafeToFold, /*InsnID*/2,
4584        // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4585        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4588        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4589        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4590        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4591        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4592        GIR_EraseFromParent, /*InsnID*/0,
4593        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4594        // GIR_Coverage, 2545,
4595        GIR_Done,
4596      // Label 245: @10154
4597      GIM_Try, /*On fail goto*//*Label 246*/ 10227, // Rule ID 2511 //
4598        GIM_CheckFeatures, GIFBS_IsARM,
4599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4601        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4602        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4603        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4604        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4605        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4606        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4607        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4608        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4609        // MIs[2] Operand 1
4610        // No operand predicates
4611        GIM_CheckIsSafeToFold, /*InsnID*/1,
4612        GIM_CheckIsSafeToFold, /*InsnID*/2,
4613        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4614        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4617        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4618        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4619        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4620        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4621        GIR_EraseFromParent, /*InsnID*/0,
4622        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4623        // GIR_Coverage, 2511,
4624        GIR_Done,
4625      // Label 246: @10227
4626      GIM_Try, /*On fail goto*//*Label 247*/ 10300, // Rule ID 2544 //
4627        GIM_CheckFeatures, GIFBS_IsThumb2,
4628        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4629        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4630        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4631        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4632        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4633        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4634        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
4635        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4636        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4637        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4638        // MIs[2] Operand 1
4639        // No operand predicates
4640        GIM_CheckIsSafeToFold, /*InsnID*/1,
4641        GIM_CheckIsSafeToFold, /*InsnID*/2,
4642        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4643        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4646        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4647        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4648        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4649        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4650        GIR_EraseFromParent, /*InsnID*/0,
4651        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4652        // GIR_Coverage, 2544,
4653        GIR_Done,
4654      // Label 247: @10300
4655      GIM_Try, /*On fail goto*//*Label 248*/ 10373, // Rule ID 161 //
4656        GIM_CheckFeatures, GIFBS_IsARM,
4657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4659        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4660        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4661        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4662        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4663        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4664        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4665        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4666        // MIs[2] Operand 1
4667        // No operand predicates
4668        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4669        GIM_CheckIsSafeToFold, /*InsnID*/1,
4670        GIM_CheckIsSafeToFold, /*InsnID*/2,
4671        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }))  =>  (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4672        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICri,
4673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4675        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4676        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4677        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4678        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4679        GIR_EraseFromParent, /*InsnID*/0,
4680        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4681        // GIR_Coverage, 161,
4682        GIR_Done,
4683      // Label 248: @10373
4684      GIM_Try, /*On fail goto*//*Label 249*/ 10446, // Rule ID 494 //
4685        GIM_CheckFeatures, GIFBS_IsThumb2,
4686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4688        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4689        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4690        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4691        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4692        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4693        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
4694        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4695        // MIs[2] Operand 1
4696        // No operand predicates
4697        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4698        GIM_CheckIsSafeToFold, /*InsnID*/1,
4699        GIM_CheckIsSafeToFold, /*InsnID*/2,
4700        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4701        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICri,
4702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4704        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
4705        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4706        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4707        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4708        GIR_EraseFromParent, /*InsnID*/0,
4709        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4710        // GIR_Coverage, 494,
4711        GIR_Done,
4712      // Label 249: @10446
4713      GIM_Try, /*On fail goto*//*Label 250*/ 10512, // Rule ID 2514 //
4714        GIM_CheckFeatures, GIFBS_IsARM,
4715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4716        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4717        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4718        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4719        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4720        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4721        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4723        GIM_CheckIsSafeToFold, /*InsnID*/1,
4724        // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn)  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4725        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
4726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4729        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4730        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4731        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4732        GIR_EraseFromParent, /*InsnID*/0,
4733        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4734        // GIR_Coverage, 2514,
4735        GIR_Done,
4736      // Label 250: @10512
4737      GIM_Try, /*On fail goto*//*Label 251*/ 10578, // Rule ID 2547 //
4738        GIM_CheckFeatures, GIFBS_IsThumb2,
4739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4740        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4741        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4742        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4743        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4744        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4745        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4747        GIM_CheckIsSafeToFold, /*InsnID*/1,
4748        // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4749        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
4750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
4752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4753        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4754        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4755        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4756        GIR_EraseFromParent, /*InsnID*/0,
4757        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4758        // GIR_Coverage, 2547,
4759        GIR_Done,
4760      // Label 251: @10578
4761      GIM_Try, /*On fail goto*//*Label 252*/ 10644, // Rule ID 162 //
4762        GIM_CheckFeatures, GIFBS_IsARM,
4763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4765        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4766        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4767        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4768        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4769        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4770        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4771        GIM_CheckIsSafeToFold, /*InsnID*/1,
4772        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4773        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BICrr,
4774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4777        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4778        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4779        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4780        GIR_EraseFromParent, /*InsnID*/0,
4781        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4782        // GIR_Coverage, 162,
4783        GIR_Done,
4784      // Label 252: @10644
4785      GIM_Try, /*On fail goto*//*Label 253*/ 10710, // Rule ID 495 //
4786        GIM_CheckFeatures, GIFBS_IsThumb2,
4787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4789        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4790        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
4791        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4792        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4793        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4794        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
4795        GIM_CheckIsSafeToFold, /*InsnID*/1,
4796        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4797        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BICrr,
4798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4799        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
4801        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4802        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4803        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4804        GIR_EraseFromParent, /*InsnID*/0,
4805        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4806        // GIR_Coverage, 495,
4807        GIR_Done,
4808      // Label 253: @10710
4809      GIM_Try, /*On fail goto*//*Label 254*/ 10748, // Rule ID 351 //
4810        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
4811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
4812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
4813        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
4814        // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })  =>  (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
4815        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTB,
4816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4818        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4819        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4820        GIR_EraseFromParent, /*InsnID*/0,
4821        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4822        // GIR_Coverage, 351,
4823        GIR_Done,
4824      // Label 254: @10748
4825      GIM_Try, /*On fail goto*//*Label 255*/ 10786, // Rule ID 352 //
4826        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
4827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
4828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
4829        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
4830        // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })  =>  (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
4831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUXTH,
4832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
4834        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4835        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4836        GIR_EraseFromParent, /*InsnID*/0,
4837        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4838        // GIR_Coverage, 352,
4839        GIR_Done,
4840      // Label 255: @10786
4841      GIM_Try, /*On fail goto*//*Label 256*/ 10838, // Rule ID 149 //
4842        GIM_CheckFeatures, GIFBS_IsARM,
4843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4845        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4846        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4847        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
4848        // MIs[1] Operand 1
4849        // No operand predicates
4850        GIM_CheckIsSafeToFold, /*InsnID*/1,
4851        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4852        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDri,
4853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4855        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4856        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4857        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4858        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4859        GIR_EraseFromParent, /*InsnID*/0,
4860        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4861        // GIR_Coverage, 149,
4862        GIR_Done,
4863      // Label 256: @10838
4864      GIM_Try, /*On fail goto*//*Label 257*/ 10890, // Rule ID 485 //
4865        GIM_CheckFeatures, GIFBS_IsThumb2,
4866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4868        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4869        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4870        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
4871        // MIs[1] Operand 1
4872        // No operand predicates
4873        GIM_CheckIsSafeToFold, /*InsnID*/1,
4874        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4875        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDri,
4876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4878        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4879        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4880        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4881        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4882        GIR_EraseFromParent, /*InsnID*/0,
4883        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4884        // GIR_Coverage, 485,
4885        GIR_Done,
4886      // Label 257: @10890
4887      GIM_Try, /*On fail goto*//*Label 258*/ 10939, // Rule ID 165 //
4888        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
4889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4891        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4892        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4893        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm,
4894        // MIs[1] Operand 1
4895        // No operand predicates
4896        GIM_CheckIsSafeToFold, /*InsnID*/1,
4897        // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm)  =>  (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
4898        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::BFC,
4899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4901        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4902        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4903        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4904        GIR_EraseFromParent, /*InsnID*/0,
4905        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4906        // GIR_Coverage, 165,
4907        GIR_Done,
4908      // Label 258: @10939
4909      GIM_Try, /*On fail goto*//*Label 259*/ 10988, // Rule ID 497 //
4910        GIM_CheckFeatures, GIFBS_IsThumb2,
4911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4913        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4914        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
4915        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_bf_inv_mask_imm,
4916        // MIs[1] Operand 1
4917        // No operand predicates
4918        GIM_CheckIsSafeToFold, /*InsnID*/1,
4919        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm)  =>  (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
4920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2BFC,
4921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
4923        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4924        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4925        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4926        GIR_EraseFromParent, /*InsnID*/0,
4927        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4928        // GIR_Coverage, 497,
4929        GIR_Done,
4930      // Label 259: @10988
4931      GIM_Try, /*On fail goto*//*Label 260*/ 11033, // Rule ID 150 //
4932        GIM_CheckFeatures, GIFBS_IsARM,
4933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
4934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
4935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
4936        // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4937        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDrr,
4938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4941        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4942        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4943        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4944        GIR_EraseFromParent, /*InsnID*/0,
4945        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4946        // GIR_Coverage, 150,
4947        GIR_Done,
4948      // Label 260: @11033
4949      GIM_Try, /*On fail goto*//*Label 261*/ 11078, // Rule ID 486 //
4950        GIM_CheckFeatures, GIFBS_IsThumb2,
4951        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
4952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
4953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
4954        // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4955        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ANDrr,
4956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
4957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
4958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
4959        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4960        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4961        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4962        GIR_EraseFromParent, /*InsnID*/0,
4963        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4964        // GIR_Coverage, 486,
4965        GIR_Done,
4966      // Label 261: @11078
4967      GIM_Reject,
4968    // Label 233: @11079
4969    GIM_Reject,
4970    // Label 230: @11080
4971    GIM_Try, /*On fail goto*//*Label 262*/ 11130, // Rule ID 1102 //
4972      GIM_CheckFeatures, GIFBS_HasNEON,
4973      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
4974      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
4975      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
4976      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
4977      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
4978      // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4979      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDd,
4980      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
4981      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
4982      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
4983      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
4984      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
4985      GIR_EraseFromParent, /*InsnID*/0,
4986      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
4987      // GIR_Coverage, 1102,
4988      GIR_Done,
4989    // Label 262: @11130
4990    GIM_Reject,
4991    // Label 231: @11131
4992    GIM_Try, /*On fail goto*//*Label 263*/ 11181, // Rule ID 1103 //
4993      GIM_CheckFeatures, GIFBS_HasNEON,
4994      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
4995      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
4996      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
4997      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
4998      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
4999      // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5000      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VANDq,
5001      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
5002      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
5003      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
5004      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5005      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5006      GIR_EraseFromParent, /*InsnID*/0,
5007      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5008      // GIR_Coverage, 1103,
5009      GIR_Done,
5010    // Label 263: @11181
5011    GIM_Reject,
5012    // Label 232: @11182
5013    GIM_Reject,
5014    // Label 6: @11183
5015    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 267*/ 15365,
5016    /*GILLT_s32*//*Label 264*/ 11195, 0,
5017    /*GILLT_v2s32*//*Label 265*/ 15263, 0, 0,
5018    /*GILLT_v4s32*//*Label 266*/ 15314,
5019    // Label 264: @11195
5020    GIM_Try, /*On fail goto*//*Label 268*/ 15262,
5021      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
5022      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
5023      GIM_Try, /*On fail goto*//*Label 269*/ 11324, // Rule ID 2727 //
5024        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5026        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5027        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5028        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5029        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5030        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5031        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
5032        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5033        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5034        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5035        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8,
5036        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
5037        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5038        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
5039        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5040        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5041        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5042        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
5043        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5044        // MIs[4] Rm
5045        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5046        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24,
5047        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
5048        GIM_CheckIsSafeToFold, /*InsnID*/1,
5049        GIM_CheckIsSafeToFold, /*InsnID*/2,
5050        GIM_CheckIsSafeToFold, /*InsnID*/3,
5051        GIM_CheckIsSafeToFold, /*InsnID*/4,
5052        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }))  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
5053        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
5054        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5056        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5057        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5058        GIR_EraseFromParent, /*InsnID*/0,
5059        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5060        // GIR_Coverage, 2727,
5061        GIR_Done,
5062      // Label 269: @11324
5063      GIM_Try, /*On fail goto*//*Label 270*/ 11443, // Rule ID 2760 //
5064        GIM_CheckFeatures, GIFBS_IsThumb2,
5065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5066        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5067        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5068        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5069        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5070        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5071        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
5072        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5073        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5074        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5075        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 8,
5076        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
5077        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5078        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
5079        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5080        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5081        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5082        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_SHL,
5083        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5084        // MIs[4] Rm
5085        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5086        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 24,
5087        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
5088        GIM_CheckIsSafeToFold, /*InsnID*/1,
5089        GIM_CheckIsSafeToFold, /*InsnID*/2,
5090        GIM_CheckIsSafeToFold, /*InsnID*/3,
5091        GIM_CheckIsSafeToFold, /*InsnID*/4,
5092        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }))  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
5093        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
5094        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5096        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5097        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5098        GIR_EraseFromParent, /*InsnID*/0,
5099        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5100        // GIR_Coverage, 2760,
5101        GIR_Done,
5102      // Label 270: @11443
5103      GIM_Try, /*On fail goto*//*Label 271*/ 11562, // Rule ID 1743 //
5104        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5105        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
5106        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5107        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5108        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5109        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5110        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5111        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
5112        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5113        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5114        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRRegClassID,
5115        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24,
5116        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
5117        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5118        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
5119        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5120        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5121        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5122        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR,
5123        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5124        // MIs[4] Rm
5125        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5126        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8,
5127        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255,
5128        GIM_CheckIsSafeToFold, /*InsnID*/1,
5129        GIM_CheckIsSafeToFold, /*InsnID*/2,
5130        GIM_CheckIsSafeToFold, /*InsnID*/3,
5131        GIM_CheckIsSafeToFold, /*InsnID*/4,
5132        // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }))  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
5133        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
5134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5136        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5137        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5138        GIR_EraseFromParent, /*InsnID*/0,
5139        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5140        // GIR_Coverage, 1743,
5141        GIR_Done,
5142      // Label 271: @11562
5143      GIM_Try, /*On fail goto*//*Label 272*/ 11681, // Rule ID 1969 //
5144        GIM_CheckFeatures, GIFBS_IsThumb2,
5145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5146        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5147        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5148        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5149        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5150        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5151        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
5152        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5153        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5154        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5155        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 24,
5156        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 16,
5157        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
5158        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
5159        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5160        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5161        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
5162        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_LSHR,
5163        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5164        // MIs[4] Rm
5165        GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
5166        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 8,
5167        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 255,
5168        GIM_CheckIsSafeToFold, /*InsnID*/1,
5169        GIM_CheckIsSafeToFold, /*InsnID*/2,
5170        GIM_CheckIsSafeToFold, /*InsnID*/3,
5171        GIM_CheckIsSafeToFold, /*InsnID*/4,
5172        // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }))  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
5173        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
5174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5176        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5177        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5178        GIR_EraseFromParent, /*InsnID*/0,
5179        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5180        // GIR_Coverage, 1969,
5181        GIR_Done,
5182      // Label 272: @11681
5183      GIM_Try, /*On fail goto*//*Label 273*/ 11797, // Rule ID 2527 //
5184        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5186        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5187        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5188        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5189        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5190        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5191        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5192        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5193        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5194        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5195        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5196        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5197        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
5198        // MIs[3] Operand 1
5199        // No operand predicates
5200        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5201        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
5202        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
5203        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
5204        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5205        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5206        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
5207        GIM_CheckIsSafeToFold, /*InsnID*/1,
5208        GIM_CheckIsSafeToFold, /*InsnID*/2,
5209        GIM_CheckIsSafeToFold, /*InsnID*/3,
5210        GIM_CheckIsSafeToFold, /*InsnID*/4,
5211        // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5212        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
5213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
5215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5216        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5217        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5218        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5219        GIR_EraseFromParent, /*InsnID*/0,
5220        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5221        // GIR_Coverage, 2527,
5222        GIR_Done,
5223      // Label 273: @11797
5224      GIM_Try, /*On fail goto*//*Label 274*/ 11913, // Rule ID 2564 //
5225        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5227        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5228        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5229        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5230        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5231        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5232        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5233        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5234        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5235        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5236        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5237        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5238        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
5239        // MIs[3] Operand 1
5240        // No operand predicates
5241        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5242        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
5243        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
5244        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
5245        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5246        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5247        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
5248        GIM_CheckIsSafeToFold, /*InsnID*/1,
5249        GIM_CheckIsSafeToFold, /*InsnID*/2,
5250        GIM_CheckIsSafeToFold, /*InsnID*/3,
5251        GIM_CheckIsSafeToFold, /*InsnID*/4,
5252        // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5253        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
5254        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5255        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
5256        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5257        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5258        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5259        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5260        GIR_EraseFromParent, /*InsnID*/0,
5261        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5262        // GIR_Coverage, 2564,
5263        GIR_Done,
5264      // Label 274: @11913
5265      GIM_Try, /*On fail goto*//*Label 275*/ 12029, // Rule ID 2732 //
5266        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5268        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5269        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5270        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5271        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5272        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5273        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
5274        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5275        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5276        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5277        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5278        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5279        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
5280        // MIs[3] Operand 1
5281        // No operand predicates
5282        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5283        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
5284        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
5285        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
5286        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5287        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5288        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
5289        GIM_CheckIsSafeToFold, /*InsnID*/1,
5290        GIM_CheckIsSafeToFold, /*InsnID*/2,
5291        GIM_CheckIsSafeToFold, /*InsnID*/3,
5292        GIM_CheckIsSafeToFold, /*InsnID*/4,
5293        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
5294        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
5295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
5297        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
5298        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5299        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5300        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5301        GIR_EraseFromParent, /*InsnID*/0,
5302        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5303        // GIR_Coverage, 2732,
5304        GIR_Done,
5305      // Label 275: @12029
5306      GIM_Try, /*On fail goto*//*Label 276*/ 12145, // Rule ID 2765 //
5307        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5309        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5310        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5311        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5312        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5313        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5314        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
5315        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5316        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5317        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5318        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5319        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5320        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
5321        // MIs[3] Operand 1
5322        // No operand predicates
5323        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5324        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
5325        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
5326        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
5327        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5328        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5329        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 4294901760,
5330        GIM_CheckIsSafeToFold, /*InsnID*/1,
5331        GIM_CheckIsSafeToFold, /*InsnID*/2,
5332        GIM_CheckIsSafeToFold, /*InsnID*/3,
5333        GIM_CheckIsSafeToFold, /*InsnID*/4,
5334        // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
5335        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
5336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
5338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
5339        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5340        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5341        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5342        GIR_EraseFromParent, /*InsnID*/0,
5343        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5344        // GIR_Coverage, 2765,
5345        GIR_Done,
5346      // Label 276: @12145
5347      GIM_Try, /*On fail goto*//*Label 277*/ 12261, // Rule ID 2526 //
5348        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5349        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5350        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5351        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5352        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5353        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5354        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5355        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
5356        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5357        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5358        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5359        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5360        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5361        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
5362        // MIs[3] Operand 1
5363        // No operand predicates
5364        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5365        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
5366        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
5367        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
5368        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5369        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5370        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535,
5371        GIM_CheckIsSafeToFold, /*InsnID*/1,
5372        GIM_CheckIsSafeToFold, /*InsnID*/2,
5373        GIM_CheckIsSafeToFold, /*InsnID*/3,
5374        GIM_CheckIsSafeToFold, /*InsnID*/4,
5375        // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5376        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
5377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
5379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5380        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5381        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5382        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5383        GIR_EraseFromParent, /*InsnID*/0,
5384        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5385        // GIR_Coverage, 2526,
5386        GIR_Done,
5387      // Label 277: @12261
5388      GIM_Try, /*On fail goto*//*Label 278*/ 12377, // Rule ID 2563 //
5389        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5390        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5391        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5392        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5393        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5394        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5395        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
5396        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
5397        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5398        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5399        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5400        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5401        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5402        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
5403        // MIs[3] Operand 1
5404        // No operand predicates
5405        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5406        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
5407        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_AND,
5408        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
5409        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
5410        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5411        GIM_CheckConstantInt, /*MI*/4, /*Op*/2, 65535,
5412        GIM_CheckIsSafeToFold, /*InsnID*/1,
5413        GIM_CheckIsSafeToFold, /*InsnID*/2,
5414        GIM_CheckIsSafeToFold, /*InsnID*/3,
5415        GIM_CheckIsSafeToFold, /*InsnID*/4,
5416        // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5417        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
5418        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
5420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5421        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5422        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5423        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5424        GIR_EraseFromParent, /*InsnID*/0,
5425        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5426        // GIR_Coverage, 2563,
5427        GIR_Done,
5428      // Label 278: @12377
5429      GIM_Try, /*On fail goto*//*Label 279*/ 12493, // Rule ID 205 //
5430        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5432        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5433        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5434        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5435        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5436        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5437        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5438        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5439        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5440        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5441        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5442        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5443        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
5444        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5445        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5446        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5447        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5448        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
5449        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
5450        // MIs[4] Operand 1
5451        // No operand predicates
5452        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
5453        GIM_CheckIsSafeToFold, /*InsnID*/1,
5454        GIM_CheckIsSafeToFold, /*InsnID*/2,
5455        GIM_CheckIsSafeToFold, /*InsnID*/3,
5456        GIM_CheckIsSafeToFold, /*InsnID*/4,
5457        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5458        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
5459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5460        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
5462        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
5463        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5464        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5465        GIR_EraseFromParent, /*InsnID*/0,
5466        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5467        // GIR_Coverage, 205,
5468        GIR_Done,
5469      // Label 279: @12493
5470      GIM_Try, /*On fail goto*//*Label 280*/ 12609, // Rule ID 544 //
5471        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5473        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5474        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5475        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5476        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5477        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5478        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5479        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5480        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5481        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5482        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5483        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5484        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
5485        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5486        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5487        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5488        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5489        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
5490        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_asr_amt,
5491        // MIs[4] Operand 1
5492        // No operand predicates
5493        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
5494        GIM_CheckIsSafeToFold, /*InsnID*/1,
5495        GIM_CheckIsSafeToFold, /*InsnID*/2,
5496        GIM_CheckIsSafeToFold, /*InsnID*/3,
5497        GIM_CheckIsSafeToFold, /*InsnID*/4,
5498        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5499        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
5500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
5503        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
5504        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5505        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5506        GIR_EraseFromParent, /*InsnID*/0,
5507        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5508        // GIR_Coverage, 544,
5509        GIR_Done,
5510      // Label 280: @12609
5511      GIM_Try, /*On fail goto*//*Label 281*/ 12725, // Rule ID 1748 //
5512        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5514        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5515        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5516        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5517        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5518        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5519        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5520        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5521        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5522        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5523        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5524        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5525        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR,
5526        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5527        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5528        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5529        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5530        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
5531        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
5532        // MIs[4] Operand 1
5533        // No operand predicates
5534        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
5535        GIM_CheckIsSafeToFold, /*InsnID*/1,
5536        GIM_CheckIsSafeToFold, /*InsnID*/2,
5537        GIM_CheckIsSafeToFold, /*InsnID*/3,
5538        GIM_CheckIsSafeToFold, /*InsnID*/4,
5539        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
5540        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
5541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5542        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
5543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
5544        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
5545        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5546        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5547        GIR_EraseFromParent, /*InsnID*/0,
5548        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5549        // GIR_Coverage, 1748,
5550        GIR_Done,
5551      // Label 281: @12725
5552      GIM_Try, /*On fail goto*//*Label 282*/ 12841, // Rule ID 1974 //
5553        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5555        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5556        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5557        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5558        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5559        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5560        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5561        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5562        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5563        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5564        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5565        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5566        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_LSHR,
5567        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5568        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5569        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5570        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5571        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
5572        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_imm1_15,
5573        // MIs[4] Operand 1
5574        // No operand predicates
5575        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
5576        GIM_CheckIsSafeToFold, /*InsnID*/1,
5577        GIM_CheckIsSafeToFold, /*InsnID*/2,
5578        GIM_CheckIsSafeToFold, /*InsnID*/3,
5579        GIM_CheckIsSafeToFold, /*InsnID*/4,
5580        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
5581        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
5582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5583        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
5584        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
5585        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
5586        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5587        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5588        GIR_EraseFromParent, /*InsnID*/0,
5589        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5590        // GIR_Coverage, 1974,
5591        GIR_Done,
5592      // Label 282: @12841
5593      GIM_Try, /*On fail goto*//*Label 283*/ 12957, // Rule ID 204 //
5594        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5596        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5597        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5598        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5599        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5600        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5601        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5602        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5603        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5604        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5605        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5606        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5607        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
5608        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5609        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5610        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5611        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5612        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
5613        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
5614        // MIs[4] Operand 1
5615        // No operand predicates
5616        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
5617        GIM_CheckIsSafeToFold, /*InsnID*/1,
5618        GIM_CheckIsSafeToFold, /*InsnID*/2,
5619        GIM_CheckIsSafeToFold, /*InsnID*/3,
5620        GIM_CheckIsSafeToFold, /*InsnID*/4,
5621        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5622        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
5623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
5626        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
5627        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5628        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5629        GIR_EraseFromParent, /*InsnID*/0,
5630        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5631        // GIR_Coverage, 204,
5632        GIR_Done,
5633      // Label 283: @12957
5634      GIM_Try, /*On fail goto*//*Label 284*/ 13073, // Rule ID 543 //
5635        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5637        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5638        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5639        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5640        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5641        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5642        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5643        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5644        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5645        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5646        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5647        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5648        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_SHL,
5649        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
5650        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
5651        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5652        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5653        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
5654        GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIPFP_I64_Predicate_pkh_lsl_amt,
5655        // MIs[4] Operand 1
5656        // No operand predicates
5657        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
5658        GIM_CheckIsSafeToFold, /*InsnID*/1,
5659        GIM_CheckIsSafeToFold, /*InsnID*/2,
5660        GIM_CheckIsSafeToFold, /*InsnID*/3,
5661        GIM_CheckIsSafeToFold, /*InsnID*/4,
5662        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
5663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
5664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
5667        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
5668        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5669        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5670        GIR_EraseFromParent, /*InsnID*/0,
5671        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5672        // GIR_Coverage, 543,
5673        GIR_Done,
5674      // Label 284: @13073
5675      GIM_Try, /*On fail goto*//*Label 285*/ 13160, // Rule ID 1744 //
5676        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5678        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5679        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5680        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5681        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5682        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5683        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5684        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5685        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5686        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5687        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5688        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5689        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
5690        GIM_CheckIsSafeToFold, /*InsnID*/1,
5691        GIM_CheckIsSafeToFold, /*InsnID*/2,
5692        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5693        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
5694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5697        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5698        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5699        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5700        GIR_EraseFromParent, /*InsnID*/0,
5701        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5702        // GIR_Coverage, 1744,
5703        GIR_Done,
5704      // Label 285: @13160
5705      GIM_Try, /*On fail goto*//*Label 286*/ 13247, // Rule ID 1970 //
5706        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5708        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5709        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5710        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5711        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5712        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5713        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5714        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5715        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5716        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5717        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5718        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5719        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294901760,
5720        GIM_CheckIsSafeToFold, /*InsnID*/1,
5721        GIM_CheckIsSafeToFold, /*InsnID*/2,
5722        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
5723        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
5724        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
5726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
5727        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5728        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5729        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5730        GIR_EraseFromParent, /*InsnID*/0,
5731        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5732        // GIR_Coverage, 1970,
5733        GIR_Done,
5734      // Label 286: @13247
5735      GIM_Try, /*On fail goto*//*Label 287*/ 13334, // Rule ID 2728 //
5736        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5738        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5739        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5740        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5741        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5742        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5743        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5744        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5745        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5746        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5747        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5748        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5749        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
5750        GIM_CheckIsSafeToFold, /*InsnID*/1,
5751        GIM_CheckIsSafeToFold, /*InsnID*/2,
5752        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
5753        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
5754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
5756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
5757        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5758        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5759        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5760        GIR_EraseFromParent, /*InsnID*/0,
5761        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5762        // GIR_Coverage, 2728,
5763        GIR_Done,
5764      // Label 287: @13334
5765      GIM_Try, /*On fail goto*//*Label 288*/ 13421, // Rule ID 2761 //
5766        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5768        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5769        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5770        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5771        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5772        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5773        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5774        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5775        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
5776        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5777        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5778        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5779        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 65535,
5780        GIM_CheckIsSafeToFold, /*InsnID*/1,
5781        GIM_CheckIsSafeToFold, /*InsnID*/2,
5782        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
5783        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
5784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5785        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
5786        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
5787        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
5788        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5789        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5790        GIR_EraseFromParent, /*InsnID*/0,
5791        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5792        // GIR_Coverage, 2761,
5793        GIR_Done,
5794      // Label 288: @13421
5795      GIM_Try, /*On fail goto*//*Label 289*/ 13516, // Rule ID 1747 //
5796        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5798        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5799        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5800        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5801        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5802        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5803        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5804        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5805        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5806        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5807        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5808        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5809        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5810        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5811        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
5812        // MIs[3] Operand 1
5813        // No operand predicates
5814        GIM_CheckIsSafeToFold, /*InsnID*/1,
5815        GIM_CheckIsSafeToFold, /*InsnID*/2,
5816        GIM_CheckIsSafeToFold, /*InsnID*/3,
5817        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
5818        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
5819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
5821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
5822        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5823        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5824        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5825        GIR_EraseFromParent, /*InsnID*/0,
5826        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5827        // GIR_Coverage, 1747,
5828        GIR_Done,
5829      // Label 289: @13516
5830      GIM_Try, /*On fail goto*//*Label 290*/ 13611, // Rule ID 1973 //
5831        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5833        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5834        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5835        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5836        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5837        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5838        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5839        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5840        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5841        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5842        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5843        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5844        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5845        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5846        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
5847        // MIs[3] Operand 1
5848        // No operand predicates
5849        GIM_CheckIsSafeToFold, /*InsnID*/1,
5850        GIM_CheckIsSafeToFold, /*InsnID*/2,
5851        GIM_CheckIsSafeToFold, /*InsnID*/3,
5852        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
5853        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
5854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
5856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
5857        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5858        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5859        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5860        GIR_EraseFromParent, /*InsnID*/0,
5861        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5862        // GIR_Coverage, 1973,
5863        GIR_Done,
5864      // Label 290: @13611
5865      GIM_Try, /*On fail goto*//*Label 291*/ 13706, // Rule ID 1746 //
5866        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5868        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5869        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5870        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5871        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5872        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5873        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5874        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5875        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
5876        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5877        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5878        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5879        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5880        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5881        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16,
5882        // MIs[3] Operand 1
5883        // No operand predicates
5884        GIM_CheckIsSafeToFold, /*InsnID*/1,
5885        GIM_CheckIsSafeToFold, /*InsnID*/2,
5886        GIM_CheckIsSafeToFold, /*InsnID*/3,
5887        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
5888        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
5889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5890        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
5891        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
5892        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5893        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5894        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5895        GIR_EraseFromParent, /*InsnID*/0,
5896        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5897        // GIR_Coverage, 1746,
5898        GIR_Done,
5899      // Label 291: @13706
5900      GIM_Try, /*On fail goto*//*Label 292*/ 13801, // Rule ID 1972 //
5901        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5903        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5904        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5905        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5906        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5907        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5908        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294901760,
5909        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5910        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_LSHR,
5911        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5912        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5913        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5914        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5915        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5916        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16,
5917        // MIs[3] Operand 1
5918        // No operand predicates
5919        GIM_CheckIsSafeToFold, /*InsnID*/1,
5920        GIM_CheckIsSafeToFold, /*InsnID*/2,
5921        GIM_CheckIsSafeToFold, /*InsnID*/3,
5922        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
5923        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
5924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
5926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
5927        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5928        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5929        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5930        GIR_EraseFromParent, /*InsnID*/0,
5931        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5932        // GIR_Coverage, 1972,
5933        GIR_Done,
5934      // Label 292: @13801
5935      GIM_Try, /*On fail goto*//*Label 293*/ 13896, // Rule ID 1745 //
5936        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
5937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
5938        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5939        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5940        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5941        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5942        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5943        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5944        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5945        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
5946        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5947        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5948        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
5949        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5950        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5951        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
5952        // MIs[3] Operand 1
5953        // No operand predicates
5954        GIM_CheckIsSafeToFold, /*InsnID*/1,
5955        GIM_CheckIsSafeToFold, /*InsnID*/2,
5956        GIM_CheckIsSafeToFold, /*InsnID*/3,
5957        // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
5958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
5959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5962        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5963        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5964        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
5965        GIR_EraseFromParent, /*InsnID*/0,
5966        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
5967        // GIR_Coverage, 1745,
5968        GIR_Done,
5969      // Label 293: @13896
5970      GIM_Try, /*On fail goto*//*Label 294*/ 13991, // Rule ID 1971 //
5971        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
5972        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
5973        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5974        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
5975        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5976        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5977        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5978        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
5979        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5980        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SHL,
5981        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5982        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5983        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
5984        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5985        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
5986        GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
5987        // MIs[3] Operand 1
5988        // No operand predicates
5989        GIM_CheckIsSafeToFold, /*InsnID*/1,
5990        GIM_CheckIsSafeToFold, /*InsnID*/2,
5991        GIM_CheckIsSafeToFold, /*InsnID*/3,
5992        // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
5993        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
5994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
5995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
5996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
5997        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
5998        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
5999        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6000        GIR_EraseFromParent, /*InsnID*/0,
6001        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6002        // GIR_Coverage, 1971,
6003        GIR_Done,
6004      // Label 294: @13991
6005      GIM_Try, /*On fail goto*//*Label 295*/ 14086, // Rule ID 2731 //
6006        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6007        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6008        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6009        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
6010        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6011        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6012        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6013        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6014        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6015        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6016        // MIs[2] Operand 1
6017        // No operand predicates
6018        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6019        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6020        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6021        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6022        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6023        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
6024        GIM_CheckIsSafeToFold, /*InsnID*/1,
6025        GIM_CheckIsSafeToFold, /*InsnID*/2,
6026        GIM_CheckIsSafeToFold, /*InsnID*/3,
6027        // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6028        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6032        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6033        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6034        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6035        GIR_EraseFromParent, /*InsnID*/0,
6036        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6037        // GIR_Coverage, 2731,
6038        GIR_Done,
6039      // Label 295: @14086
6040      GIM_Try, /*On fail goto*//*Label 296*/ 14181, // Rule ID 2764 //
6041        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6043        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6044        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
6045        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6046        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6047        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6048        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6049        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6050        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6051        // MIs[2] Operand 1
6052        // No operand predicates
6053        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6054        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6055        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6056        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6057        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6058        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
6059        GIM_CheckIsSafeToFold, /*InsnID*/1,
6060        GIM_CheckIsSafeToFold, /*InsnID*/2,
6061        GIM_CheckIsSafeToFold, /*InsnID*/3,
6062        // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6063        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6067        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6068        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6069        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6070        GIR_EraseFromParent, /*InsnID*/0,
6071        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6072        // GIR_Coverage, 2764,
6073        GIR_Done,
6074      // Label 296: @14181
6075      GIM_Try, /*On fail goto*//*Label 297*/ 14276, // Rule ID 2730 //
6076        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6078        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6079        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
6080        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6081        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6082        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6083        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6084        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6085        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16,
6086        // MIs[2] Operand 1
6087        // No operand predicates
6088        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6089        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6090        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6091        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6092        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6093        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
6094        GIM_CheckIsSafeToFold, /*InsnID*/1,
6095        GIM_CheckIsSafeToFold, /*InsnID*/2,
6096        GIM_CheckIsSafeToFold, /*InsnID*/3,
6097        // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
6098        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHTB,
6099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6100        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6101        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6102        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6103        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6104        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6105        GIR_EraseFromParent, /*InsnID*/0,
6106        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6107        // GIR_Coverage, 2730,
6108        GIR_Done,
6109      // Label 297: @14276
6110      GIM_Try, /*On fail goto*//*Label 298*/ 14371, // Rule ID 2763 //
6111        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6112        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6113        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6114        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
6115        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6116        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6117        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6118        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6119        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6120        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16,
6121        // MIs[2] Operand 1
6122        // No operand predicates
6123        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6124        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6125        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6126        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6127        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6128        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 4294901760,
6129        GIM_CheckIsSafeToFold, /*InsnID*/1,
6130        GIM_CheckIsSafeToFold, /*InsnID*/2,
6131        GIM_CheckIsSafeToFold, /*InsnID*/3,
6132        // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }))  =>  (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
6133        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHTB,
6134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6137        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6138        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6139        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6140        GIR_EraseFromParent, /*InsnID*/0,
6141        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6142        // GIR_Coverage, 2763,
6143        GIR_Done,
6144      // Label 298: @14371
6145      GIM_Try, /*On fail goto*//*Label 299*/ 14466, // Rule ID 2729 //
6146        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
6147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6148        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6149        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
6150        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6151        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6152        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6153        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6154        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6155        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6156        // MIs[2] Operand 1
6157        // No operand predicates
6158        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6159        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6160        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6161        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6162        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
6163        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535,
6164        GIM_CheckIsSafeToFold, /*InsnID*/1,
6165        GIM_CheckIsSafeToFold, /*InsnID*/2,
6166        GIM_CheckIsSafeToFold, /*InsnID*/3,
6167        // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }))  =>  (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6168        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::PKHBT,
6169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
6171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6172        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6173        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6174        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6175        GIR_EraseFromParent, /*InsnID*/0,
6176        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6177        // GIR_Coverage, 2729,
6178        GIR_Done,
6179      // Label 299: @14466
6180      GIM_Try, /*On fail goto*//*Label 300*/ 14561, // Rule ID 2762 //
6181        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
6182        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6183        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6184        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
6185        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6186        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6187        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6188        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6189        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6190        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_imm16_31,
6191        // MIs[2] Operand 1
6192        // No operand predicates
6193        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
6194        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
6195        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
6196        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
6197        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6198        GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 65535,
6199        GIM_CheckIsSafeToFold, /*InsnID*/1,
6200        GIM_CheckIsSafeToFold, /*InsnID*/2,
6201        GIM_CheckIsSafeToFold, /*InsnID*/3,
6202        // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }))  =>  (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
6203        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2PKHBT,
6204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
6206        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
6207        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
6208        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6209        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6210        GIR_EraseFromParent, /*InsnID*/0,
6211        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6212        // GIR_Coverage, 2762,
6213        GIR_Done,
6214      // Label 300: @14561
6215      GIM_Try, /*On fail goto*//*Label 301*/ 14634, // Rule ID 2551 //
6216        GIM_CheckFeatures, GIFBS_IsThumb2,
6217        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6218        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6219        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6220        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6221        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6222        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
6223        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6224        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6225        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6226        // MIs[2] Operand 1
6227        // No operand predicates
6228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6229        GIM_CheckIsSafeToFold, /*InsnID*/1,
6230        GIM_CheckIsSafeToFold, /*InsnID*/2,
6231        // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6232        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
6233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
6235        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6236        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6237        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6238        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6239        GIR_EraseFromParent, /*InsnID*/0,
6240        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6241        // GIR_Coverage, 2551,
6242        GIR_Done,
6243      // Label 301: @14634
6244      GIM_Try, /*On fail goto*//*Label 302*/ 14707, // Rule ID 2550 //
6245        GIM_CheckFeatures, GIFBS_IsThumb2,
6246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6247        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6248        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6249        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6250        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6251        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6252        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6253        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6254        // MIs[2] Operand 1
6255        // No operand predicates
6256        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
6257        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6258        GIM_CheckIsSafeToFold, /*InsnID*/1,
6259        GIM_CheckIsSafeToFold, /*InsnID*/2,
6260        // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6261        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
6262        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6263        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
6264        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6265        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6266        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6267        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6268        GIR_EraseFromParent, /*InsnID*/0,
6269        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6270        // GIR_Coverage, 2550,
6271        GIR_Done,
6272      // Label 302: @14707
6273      GIM_Try, /*On fail goto*//*Label 303*/ 14780, // Rule ID 2549 //
6274        GIM_CheckFeatures, GIFBS_IsThumb2,
6275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6277        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6278        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6279        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6280        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6281        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -1,
6282        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6283        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6284        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6285        // MIs[2] Operand 1
6286        // No operand predicates
6287        GIM_CheckIsSafeToFold, /*InsnID*/1,
6288        GIM_CheckIsSafeToFold, /*InsnID*/2,
6289        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm))  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6290        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
6291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6293        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6294        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6295        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6296        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6297        GIR_EraseFromParent, /*InsnID*/0,
6298        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6299        // GIR_Coverage, 2549,
6300        GIR_Done,
6301      // Label 303: @14780
6302      GIM_Try, /*On fail goto*//*Label 304*/ 14853, // Rule ID 500 //
6303        GIM_CheckFeatures, GIFBS_IsThumb2,
6304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6306        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6307        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6308        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6309        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6310        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6311        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
6312        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6313        // MIs[2] Operand 1
6314        // No operand predicates
6315        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
6316        GIM_CheckIsSafeToFold, /*InsnID*/1,
6317        GIM_CheckIsSafeToFold, /*InsnID*/2,
6318        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }))  =>  (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNri,
6320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6322        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6323        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6324        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6325        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6326        GIR_EraseFromParent, /*InsnID*/0,
6327        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6328        // GIR_Coverage, 500,
6329        GIR_Done,
6330      // Label 304: @14853
6331      GIM_Try, /*On fail goto*//*Label 305*/ 14919, // Rule ID 2552 //
6332        GIM_CheckFeatures, GIFBS_IsThumb2,
6333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6334        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6335        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6336        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6337        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6338        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6339        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
6340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6341        GIM_CheckIsSafeToFold, /*InsnID*/1,
6342        // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn)  =>  (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6343        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
6344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
6346        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6347        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6348        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6349        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6350        GIR_EraseFromParent, /*InsnID*/0,
6351        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6352        // GIR_Coverage, 2552,
6353        GIR_Done,
6354      // Label 305: @14919
6355      GIM_Try, /*On fail goto*//*Label 306*/ 14985, // Rule ID 501 //
6356        GIM_CheckFeatures, GIFBS_IsThumb2,
6357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6359        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6360        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
6361        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6362        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6363        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6364        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
6365        GIM_CheckIsSafeToFold, /*InsnID*/1,
6366        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6367        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORNrr,
6368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6371        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6372        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6373        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6374        GIR_EraseFromParent, /*InsnID*/0,
6375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6376        // GIR_Coverage, 501,
6377        GIR_Done,
6378      // Label 306: @14985
6379      GIM_Try, /*On fail goto*//*Label 307*/ 15026, // Rule ID 1702 //
6380        GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
6381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
6382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6383        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760,
6384        // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] })  =>  (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
6385        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVTi16,
6386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6388        GIR_AddImm, /*InsnID*/0, /*Imm*/65535,
6389        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6390        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6391        GIR_EraseFromParent, /*InsnID*/0,
6392        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6393        // GIR_Coverage, 1702,
6394        GIR_Done,
6395      // Label 307: @15026
6396      GIM_Try, /*On fail goto*//*Label 308*/ 15067, // Rule ID 1894 //
6397        GIM_CheckFeatures, GIFBS_IsThumb2,
6398        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6400        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294901760,
6401        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] })  =>  (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
6402        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVTi16,
6403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6405        GIR_AddImm, /*InsnID*/0, /*Imm*/65535,
6406        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6407        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6408        GIR_EraseFromParent, /*InsnID*/0,
6409        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6410        // GIR_Coverage, 1894,
6411        GIR_Done,
6412      // Label 308: @15067
6413      GIM_Try, /*On fail goto*//*Label 309*/ 15119, // Rule ID 153 //
6414        GIM_CheckFeatures, GIFBS_IsARM,
6415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6417        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6418        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6419        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
6420        // MIs[1] Operand 1
6421        // No operand predicates
6422        GIM_CheckIsSafeToFold, /*InsnID*/1,
6423        // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6424        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRri,
6425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6427        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6428        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6429        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6430        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6431        GIR_EraseFromParent, /*InsnID*/0,
6432        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6433        // GIR_Coverage, 153,
6434        GIR_Done,
6435      // Label 309: @15119
6436      GIM_Try, /*On fail goto*//*Label 310*/ 15171, // Rule ID 488 //
6437        GIM_CheckFeatures, GIFBS_IsThumb2,
6438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6440        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6441        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6442        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6443        // MIs[1] Operand 1
6444        // No operand predicates
6445        GIM_CheckIsSafeToFold, /*InsnID*/1,
6446        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6447        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRri,
6448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6450        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6451        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6452        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6453        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6454        GIR_EraseFromParent, /*InsnID*/0,
6455        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6456        // GIR_Coverage, 488,
6457        GIR_Done,
6458      // Label 310: @15171
6459      GIM_Try, /*On fail goto*//*Label 311*/ 15216, // Rule ID 154 //
6460        GIM_CheckFeatures, GIFBS_IsARM,
6461        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
6464        // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6465        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ORRrr,
6466        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6469        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6470        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6471        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6472        GIR_EraseFromParent, /*InsnID*/0,
6473        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6474        // GIR_Coverage, 154,
6475        GIR_Done,
6476      // Label 311: @15216
6477      GIM_Try, /*On fail goto*//*Label 312*/ 15261, // Rule ID 489 //
6478        GIM_CheckFeatures, GIFBS_IsThumb2,
6479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6481        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6482        // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6483        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ORRrr,
6484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6486        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6487        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6488        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6489        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6490        GIR_EraseFromParent, /*InsnID*/0,
6491        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6492        // GIR_Coverage, 489,
6493        GIR_Done,
6494      // Label 312: @15261
6495      GIM_Reject,
6496    // Label 268: @15262
6497    GIM_Reject,
6498    // Label 265: @15263
6499    GIM_Try, /*On fail goto*//*Label 313*/ 15313, // Rule ID 1106 //
6500      GIM_CheckFeatures, GIFBS_HasNEON,
6501      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6502      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
6503      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6504      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6505      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
6506      // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6507      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRd,
6508      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6509      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6510      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6511      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6512      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6513      GIR_EraseFromParent, /*InsnID*/0,
6514      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6515      // GIR_Coverage, 1106,
6516      GIR_Done,
6517    // Label 313: @15313
6518    GIM_Reject,
6519    // Label 266: @15314
6520    GIM_Try, /*On fail goto*//*Label 314*/ 15364, // Rule ID 1107 //
6521      GIM_CheckFeatures, GIFBS_HasNEON,
6522      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
6523      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6524      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
6525      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
6526      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
6527      // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
6528      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VORRq,
6529      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6530      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6532      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6533      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6534      GIR_EraseFromParent, /*InsnID*/0,
6535      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6536      // GIR_Coverage, 1107,
6537      GIR_Done,
6538    // Label 314: @15364
6539    GIM_Reject,
6540    // Label 267: @15365
6541    GIM_Reject,
6542    // Label 7: @15366
6543    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 318*/ 15864,
6544    /*GILLT_s32*//*Label 315*/ 15378, 0,
6545    /*GILLT_v2s32*//*Label 316*/ 15762, 0, 0,
6546    /*GILLT_v4s32*//*Label 317*/ 15813,
6547    // Label 315: @15378
6548    GIM_Try, /*On fail goto*//*Label 319*/ 15761,
6549      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
6550      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
6551      GIM_Try, /*On fail goto*//*Label 320*/ 15436, // Rule ID 2554 //
6552        GIM_CheckFeatures, GIFBS_IsThumb2,
6553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6554        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, -1,
6555        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6556        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6557        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6558        // MIs[1] Operand 1
6559        // No operand predicates
6560        GIM_CheckIsSafeToFold, /*InsnID*/1,
6561        // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
6562        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
6563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6564        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6565        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6566        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6567        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6568        GIR_EraseFromParent, /*InsnID*/0,
6569        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6570        // GIR_Coverage, 2554,
6571        GIR_Done,
6572      // Label 320: @15436
6573      GIM_Try, /*On fail goto*//*Label 321*/ 15484, // Rule ID 503 //
6574        GIM_CheckFeatures, GIFBS_IsThumb2,
6575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6576        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6577        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6578        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6579        // MIs[1] Operand 1
6580        // No operand predicates
6581        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
6582        GIM_CheckIsSafeToFold, /*InsnID*/1,
6583        // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })  =>  (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
6584        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNi,
6585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6586        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6587        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6588        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6589        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6590        GIR_EraseFromParent, /*InsnID*/0,
6591        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6592        // GIR_Coverage, 503,
6593        GIR_Done,
6594      // Label 321: @15484
6595      GIM_Try, /*On fail goto*//*Label 322*/ 15525, // Rule ID 504 //
6596        GIM_CheckFeatures, GIFBS_IsThumb2,
6597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6598        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6599        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
6600        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })  =>  (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
6601        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MVNr,
6602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
6604        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6605        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6606        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6607        GIR_EraseFromParent, /*InsnID*/0,
6608        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6609        // GIR_Coverage, 504,
6610        GIR_Done,
6611      // Label 322: @15525
6612      GIM_Try, /*On fail goto*//*Label 323*/ 15566, // Rule ID 167 //
6613        GIM_CheckFeatures, GIFBS_IsARM,
6614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6616        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
6617        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })  =>  (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
6618        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MVNr,
6619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
6621        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6622        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6623        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6624        GIR_EraseFromParent, /*InsnID*/0,
6625        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6626        // GIR_Coverage, 167,
6627        GIR_Done,
6628      // Label 323: @15566
6629      GIM_Try, /*On fail goto*//*Label 324*/ 15618, // Rule ID 157 //
6630        GIM_CheckFeatures, GIFBS_IsARM,
6631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6633        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6634        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6635        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
6636        // MIs[1] Operand 1
6637        // No operand predicates
6638        GIM_CheckIsSafeToFold, /*InsnID*/1,
6639        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)  =>  (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6640        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORri,
6641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6643        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6644        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6645        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6646        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6647        GIR_EraseFromParent, /*InsnID*/0,
6648        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6649        // GIR_Coverage, 157,
6650        GIR_Done,
6651      // Label 324: @15618
6652      GIM_Try, /*On fail goto*//*Label 325*/ 15670, // Rule ID 491 //
6653        GIM_CheckFeatures, GIFBS_IsThumb2,
6654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6655        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6656        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6657        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
6658        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
6659        // MIs[1] Operand 1
6660        // No operand predicates
6661        GIM_CheckIsSafeToFold, /*InsnID*/1,
6662        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)  =>  (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORri,
6664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6666        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6667        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6668        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6669        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6670        GIR_EraseFromParent, /*InsnID*/0,
6671        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6672        // GIR_Coverage, 491,
6673        GIR_Done,
6674      // Label 325: @15670
6675      GIM_Try, /*On fail goto*//*Label 326*/ 15715, // Rule ID 158 //
6676        GIM_CheckFeatures, GIFBS_IsARM,
6677        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6678        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6679        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
6680        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6681        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::EORrr,
6682        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6683        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6685        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6686        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6687        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6688        GIR_EraseFromParent, /*InsnID*/0,
6689        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6690        // GIR_Coverage, 158,
6691        GIR_Done,
6692      // Label 326: @15715
6693      GIM_Try, /*On fail goto*//*Label 327*/ 15760, // Rule ID 492 //
6694        GIM_CheckFeatures, GIFBS_IsThumb2,
6695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
6696        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
6697        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
6698        // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6699        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2EORrr,
6700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
6701        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
6702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
6703        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6704        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6705        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6706        GIR_EraseFromParent, /*InsnID*/0,
6707        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6708        // GIR_Coverage, 492,
6709        GIR_Done,
6710      // Label 327: @15760
6711      GIM_Reject,
6712    // Label 319: @15761
6713    GIM_Reject,
6714    // Label 316: @15762
6715    GIM_Try, /*On fail goto*//*Label 328*/ 15812, // Rule ID 1104 //
6716      GIM_CheckFeatures, GIFBS_HasNEON,
6717      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6718      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
6719      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6720      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6721      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
6722      // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6723      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORd,
6724      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6725      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6726      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6727      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6728      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6729      GIR_EraseFromParent, /*InsnID*/0,
6730      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6731      // GIR_Coverage, 1104,
6732      GIR_Done,
6733    // Label 328: @15812
6734    GIM_Reject,
6735    // Label 317: @15813
6736    GIM_Try, /*On fail goto*//*Label 329*/ 15863, // Rule ID 1105 //
6737      GIM_CheckFeatures, GIFBS_HasNEON,
6738      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
6739      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
6740      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
6741      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
6742      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
6743      // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
6744      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VEORq,
6745      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6746      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
6747      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
6748      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6749      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6750      GIR_EraseFromParent, /*InsnID*/0,
6751      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6752      // GIR_Coverage, 1105,
6753      GIR_Done,
6754    // Label 329: @15863
6755    GIM_Reject,
6756    // Label 318: @15864
6757    GIM_Reject,
6758    // Label 8: @15865
6759    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 10, /*)*//*default:*//*Label 339*/ 20252,
6760    /*GILLT_s32*//*Label 330*/ 15880,
6761    /*GILLT_s64*//*Label 331*/ 15956,
6762    /*GILLT_v2s32*//*Label 332*/ 16669,
6763    /*GILLT_v2s64*//*Label 333*/ 17310,
6764    /*GILLT_v4s16*//*Label 334*/ 18023,
6765    /*GILLT_v4s32*//*Label 335*/ 18418,
6766    /*GILLT_v8s8*//*Label 336*/ 19097,
6767    /*GILLT_v8s16*//*Label 337*/ 19458,
6768    /*GILLT_v16s8*//*Label 338*/ 19891,
6769    // Label 330: @15880
6770    GIM_Try, /*On fail goto*//*Label 340*/ 15955,
6771      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
6772      GIM_Try, /*On fail goto*//*Label 341*/ 15920, // Rule ID 686 //
6773        GIM_CheckFeatures, GIFBS_HasVFP2,
6774        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
6775        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
6776        // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn)  =>  (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
6777        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVRS,
6778        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
6779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
6780        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6781        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6782        GIR_EraseFromParent, /*InsnID*/0,
6783        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6784        // GIR_Coverage, 686,
6785        GIR_Done,
6786      // Label 341: @15920
6787      GIM_Try, /*On fail goto*//*Label 342*/ 15954, // Rule ID 687 //
6788        GIM_CheckFeatures, GIFBS_HasVFP2_UseVMOVSR,
6789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
6790        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
6791        // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt)  =>  (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt)
6792        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVSR,
6793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sn
6794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rt
6795        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6796        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6797        GIR_EraseFromParent, /*InsnID*/0,
6798        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6799        // GIR_Coverage, 687,
6800        GIR_Done,
6801      // Label 342: @15954
6802      GIM_Reject,
6803    // Label 340: @15955
6804    GIM_Reject,
6805    // Label 331: @15956
6806    GIM_Try, /*On fail goto*//*Label 343*/ 15990, // Rule ID 2321 //
6807      GIM_CheckFeatures, GIFBS_IsLE,
6808      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6809      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6810      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6811      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v1i64] }:$src
6812      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6813      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6814      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6815      GIR_EraseFromParent, /*InsnID*/0,
6816      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6817      // GIR_Coverage, 2321,
6818      GIR_Done,
6819    // Label 343: @15990
6820    GIM_Try, /*On fail goto*//*Label 344*/ 16024, // Rule ID 2322 //
6821      GIM_CheckFeatures, GIFBS_IsLE,
6822      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
6823      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6824      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6825      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v1i64] }:$src
6826      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6827      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6828      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6829      GIR_EraseFromParent, /*InsnID*/0,
6830      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6831      // GIR_Coverage, 2322,
6832      GIR_Done,
6833    // Label 344: @16024
6834    GIM_Try, /*On fail goto*//*Label 345*/ 16058, // Rule ID 2323 //
6835      GIM_CheckFeatures, GIFBS_IsLE,
6836      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
6837      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6838      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6839      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v1i64] }:$src
6840      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6841      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6842      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6843      GIR_EraseFromParent, /*InsnID*/0,
6844      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6845      // GIR_Coverage, 2323,
6846      GIR_Done,
6847    // Label 345: @16058
6848    GIM_Try, /*On fail goto*//*Label 346*/ 16090, // Rule ID 2324 //
6849      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
6850      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6851      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6852      // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v1i64] }:$src
6853      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6854      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6855      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6856      GIR_EraseFromParent, /*InsnID*/0,
6857      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6858      // GIR_Coverage, 2324,
6859      GIR_Done,
6860    // Label 346: @16090
6861    GIM_Try, /*On fail goto*//*Label 347*/ 16124, // Rule ID 2325 //
6862      GIM_CheckFeatures, GIFBS_IsLE,
6863      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6864      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6865      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6866      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v1i64] }:$src
6867      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6868      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6869      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6870      GIR_EraseFromParent, /*InsnID*/0,
6871      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6872      // GIR_Coverage, 2325,
6873      GIR_Done,
6874    // Label 347: @16124
6875    GIM_Try, /*On fail goto*//*Label 348*/ 16156, // Rule ID 2341 //
6876      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
6877      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6878      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6879      // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[f64] }:$src
6880      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6881      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6882      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6883      GIR_EraseFromParent, /*InsnID*/0,
6884      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6885      // GIR_Coverage, 2341,
6886      GIR_Done,
6887    // Label 348: @16156
6888    GIM_Try, /*On fail goto*//*Label 349*/ 16190, // Rule ID 2342 //
6889      GIM_CheckFeatures, GIFBS_IsLE,
6890      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6891      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6892      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6893      // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[f64] }:$src
6894      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6895      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6896      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6897      GIR_EraseFromParent, /*InsnID*/0,
6898      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6899      // GIR_Coverage, 2342,
6900      GIR_Done,
6901    // Label 349: @16190
6902    GIM_Try, /*On fail goto*//*Label 350*/ 16224, // Rule ID 2343 //
6903      GIM_CheckFeatures, GIFBS_IsLE,
6904      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
6905      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6906      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6907      // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[f64] }:$src
6908      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6909      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6910      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6911      GIR_EraseFromParent, /*InsnID*/0,
6912      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6913      // GIR_Coverage, 2343,
6914      GIR_Done,
6915    // Label 350: @16224
6916    GIM_Try, /*On fail goto*//*Label 351*/ 16258, // Rule ID 2344 //
6917      GIM_CheckFeatures, GIFBS_IsLE,
6918      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
6919      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6920      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6921      // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src)  =>  DPR:{ *:[f64] }:$src
6922      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6923      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6924      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6925      GIR_EraseFromParent, /*InsnID*/0,
6926      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6927      // GIR_Coverage, 2344,
6928      GIR_Done,
6929    // Label 351: @16258
6930    GIM_Try, /*On fail goto*//*Label 352*/ 16292, // Rule ID 2345 //
6931      GIM_CheckFeatures, GIFBS_IsLE,
6932      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
6933      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6934      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6935      // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[f64] }:$src
6936      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6937      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6938      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6939      GIR_EraseFromParent, /*InsnID*/0,
6940      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6941      // GIR_Coverage, 2345,
6942      GIR_Done,
6943    // Label 352: @16292
6944    GIM_Try, /*On fail goto*//*Label 353*/ 16326, // Rule ID 2346 //
6945      GIM_CheckFeatures, GIFBS_IsLE,
6946      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6947      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6948      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6949      // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[f64] }:$src
6950      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6951      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
6952      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6953      GIR_EraseFromParent, /*InsnID*/0,
6954      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
6955      // GIR_Coverage, 2346,
6956      GIR_Done,
6957    // Label 353: @16326
6958    GIM_Try, /*On fail goto*//*Label 354*/ 16364, // Rule ID 2385 //
6959      GIM_CheckFeatures, GIFBS_IsBE,
6960      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
6961      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6962      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6963      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)  =>  (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)
6964      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
6965      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6966      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6967      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6968      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6969      GIR_EraseFromParent, /*InsnID*/0,
6970      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6971      // GIR_Coverage, 2385,
6972      GIR_Done,
6973    // Label 354: @16364
6974    GIM_Try, /*On fail goto*//*Label 355*/ 16402, // Rule ID 2386 //
6975      GIM_CheckFeatures, GIFBS_IsBE,
6976      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
6977      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6978      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6979      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)  =>  (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)
6980      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
6981      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6982      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6983      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
6984      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
6985      GIR_EraseFromParent, /*InsnID*/0,
6986      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
6987      // GIR_Coverage, 2386,
6988      GIR_Done,
6989    // Label 355: @16402
6990    GIM_Try, /*On fail goto*//*Label 356*/ 16440, // Rule ID 2387 //
6991      GIM_CheckFeatures, GIFBS_IsBE,
6992      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
6993      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
6994      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
6995      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)  =>  (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)
6996      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
6997      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
6998      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
6999      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7000      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7001      GIR_EraseFromParent, /*InsnID*/0,
7002      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7003      // GIR_Coverage, 2387,
7004      GIR_Done,
7005    // Label 356: @16440
7006    GIM_Try, /*On fail goto*//*Label 357*/ 16478, // Rule ID 2388 //
7007      GIM_CheckFeatures, GIFBS_IsBE,
7008      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7009      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7010      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7011      // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)  =>  (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)
7012      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
7013      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7014      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7015      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7016      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7017      GIR_EraseFromParent, /*InsnID*/0,
7018      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7019      // GIR_Coverage, 2388,
7020      GIR_Done,
7021    // Label 357: @16478
7022    GIM_Try, /*On fail goto*//*Label 358*/ 16516, // Rule ID 2403 //
7023      GIM_CheckFeatures, GIFBS_IsBE,
7024      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7025      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7026      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7027      // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src)  =>  (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src)
7028      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
7029      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7030      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7031      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7032      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7033      GIR_EraseFromParent, /*InsnID*/0,
7034      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7035      // GIR_Coverage, 2403,
7036      GIR_Done,
7037    // Label 358: @16516
7038    GIM_Try, /*On fail goto*//*Label 359*/ 16554, // Rule ID 2404 //
7039      GIM_CheckFeatures, GIFBS_IsBE,
7040      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
7041      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7042      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7043      // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src)
7044      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
7045      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7046      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7047      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7048      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7049      GIR_EraseFromParent, /*InsnID*/0,
7050      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7051      // GIR_Coverage, 2404,
7052      GIR_Done,
7053    // Label 359: @16554
7054    GIM_Try, /*On fail goto*//*Label 360*/ 16592, // Rule ID 2405 //
7055      GIM_CheckFeatures, GIFBS_IsBE,
7056      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
7057      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7058      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7059      // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src)  =>  (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src)
7060      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
7061      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7062      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7063      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7064      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7065      GIR_EraseFromParent, /*InsnID*/0,
7066      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7067      // GIR_Coverage, 2405,
7068      GIR_Done,
7069    // Label 360: @16592
7070    GIM_Try, /*On fail goto*//*Label 361*/ 16630, // Rule ID 2406 //
7071      GIM_CheckFeatures, GIFBS_IsBE,
7072      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
7073      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7074      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7075      // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src)  =>  (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src)
7076      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
7077      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7078      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7079      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7080      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7081      GIR_EraseFromParent, /*InsnID*/0,
7082      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7083      // GIR_Coverage, 2406,
7084      GIR_Done,
7085    // Label 361: @16630
7086    GIM_Try, /*On fail goto*//*Label 362*/ 16668, // Rule ID 2407 //
7087      GIM_CheckFeatures, GIFBS_IsBE,
7088      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7089      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7090      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7091      // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src)  =>  (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src)
7092      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
7093      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7094      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7095      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7096      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7097      GIR_EraseFromParent, /*InsnID*/0,
7098      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7099      // GIR_Coverage, 2407,
7100      GIR_Done,
7101    // Label 362: @16668
7102    GIM_Reject,
7103    // Label 332: @16669
7104    GIM_Try, /*On fail goto*//*Label 363*/ 16703, // Rule ID 2326 //
7105      GIM_CheckFeatures, GIFBS_IsLE,
7106      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7107      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7108      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7109      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v2i32] }:$src
7110      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7111      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7112      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7113      GIR_EraseFromParent, /*InsnID*/0,
7114      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7115      // GIR_Coverage, 2326,
7116      GIR_Done,
7117    // Label 363: @16703
7118    GIM_Try, /*On fail goto*//*Label 364*/ 16737, // Rule ID 2327 //
7119      GIM_CheckFeatures, GIFBS_IsLE,
7120      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
7121      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7122      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7123      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v2i32] }:$src
7124      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7125      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7126      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7127      GIR_EraseFromParent, /*InsnID*/0,
7128      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7129      // GIR_Coverage, 2327,
7130      GIR_Done,
7131    // Label 364: @16737
7132    GIM_Try, /*On fail goto*//*Label 365*/ 16771, // Rule ID 2328 //
7133      GIM_CheckFeatures, GIFBS_IsLE,
7134      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
7135      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7136      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7137      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v2i32] }:$src
7138      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7139      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7140      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7141      GIR_EraseFromParent, /*InsnID*/0,
7142      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7143      // GIR_Coverage, 2328,
7144      GIR_Done,
7145    // Label 365: @16771
7146    GIM_Try, /*On fail goto*//*Label 366*/ 16805, // Rule ID 2329 //
7147      GIM_CheckFeatures, GIFBS_IsLE,
7148      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7149      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7150      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7151      // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v2i32] }:$src
7152      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7153      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7154      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7155      GIR_EraseFromParent, /*InsnID*/0,
7156      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7157      // GIR_Coverage, 2329,
7158      GIR_Done,
7159    // Label 366: @16805
7160    GIM_Try, /*On fail goto*//*Label 367*/ 16837, // Rule ID 2330 //
7161      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7162      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7163      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7164      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v2i32] }:$src
7165      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7166      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7167      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7168      GIR_EraseFromParent, /*InsnID*/0,
7169      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7170      // GIR_Coverage, 2330,
7171      GIR_Done,
7172    // Label 367: @16837
7173    GIM_Try, /*On fail goto*//*Label 368*/ 16871, // Rule ID 2347 //
7174      GIM_CheckFeatures, GIFBS_IsLE,
7175      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7176      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7177      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7178      // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v2f32] }:$src
7179      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7180      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7181      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7182      GIR_EraseFromParent, /*InsnID*/0,
7183      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7184      // GIR_Coverage, 2347,
7185      GIR_Done,
7186    // Label 368: @16871
7187    GIM_Try, /*On fail goto*//*Label 369*/ 16905, // Rule ID 2349 //
7188      GIM_CheckFeatures, GIFBS_IsLE,
7189      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7190      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7191      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7192      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v2f32] }:$src
7193      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7194      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7195      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7196      GIR_EraseFromParent, /*InsnID*/0,
7197      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7198      // GIR_Coverage, 2349,
7199      GIR_Done,
7200    // Label 369: @16905
7201    GIM_Try, /*On fail goto*//*Label 370*/ 16937, // Rule ID 2350 //
7202      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7203      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7204      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7205      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v2f32] }:$src
7206      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7207      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7208      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7209      GIR_EraseFromParent, /*InsnID*/0,
7210      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7211      // GIR_Coverage, 2350,
7212      GIR_Done,
7213    // Label 370: @16937
7214    GIM_Try, /*On fail goto*//*Label 371*/ 16971, // Rule ID 2351 //
7215      GIM_CheckFeatures, GIFBS_IsLE,
7216      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
7217      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7218      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7219      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v2f32] }:$src
7220      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7221      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7222      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7223      GIR_EraseFromParent, /*InsnID*/0,
7224      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7225      // GIR_Coverage, 2351,
7226      GIR_Done,
7227    // Label 371: @16971
7228    GIM_Try, /*On fail goto*//*Label 372*/ 17005, // Rule ID 2352 //
7229      GIM_CheckFeatures, GIFBS_IsLE,
7230      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
7231      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7232      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7233      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v2f32] }:$src
7234      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7235      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7236      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7237      GIR_EraseFromParent, /*InsnID*/0,
7238      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7239      // GIR_Coverage, 2352,
7240      GIR_Done,
7241    // Label 372: @17005
7242    GIM_Try, /*On fail goto*//*Label 373*/ 17043, // Rule ID 2389 //
7243      GIM_CheckFeatures, GIFBS_IsBE,
7244      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7245      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7246      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7247      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)
7248      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
7249      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7250      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7251      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7252      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7253      GIR_EraseFromParent, /*InsnID*/0,
7254      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7255      // GIR_Coverage, 2389,
7256      GIR_Done,
7257    // Label 373: @17043
7258    GIM_Try, /*On fail goto*//*Label 374*/ 17081, // Rule ID 2390 //
7259      GIM_CheckFeatures, GIFBS_IsBE,
7260      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
7261      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7262      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7263      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)  =>  (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)
7264      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
7265      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7266      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7267      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7268      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7269      GIR_EraseFromParent, /*InsnID*/0,
7270      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7271      // GIR_Coverage, 2390,
7272      GIR_Done,
7273    // Label 374: @17081
7274    GIM_Try, /*On fail goto*//*Label 375*/ 17119, // Rule ID 2391 //
7275      GIM_CheckFeatures, GIFBS_IsBE,
7276      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
7277      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7278      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7279      // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)  =>  (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)
7280      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
7281      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7282      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7283      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7284      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7285      GIR_EraseFromParent, /*InsnID*/0,
7286      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7287      // GIR_Coverage, 2391,
7288      GIR_Done,
7289    // Label 375: @17119
7290    GIM_Try, /*On fail goto*//*Label 376*/ 17157, // Rule ID 2392 //
7291      GIM_CheckFeatures, GIFBS_IsBE,
7292      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7293      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7294      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7295      // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src)  =>  (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src)
7296      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
7297      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7298      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7299      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7300      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7301      GIR_EraseFromParent, /*InsnID*/0,
7302      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7303      // GIR_Coverage, 2392,
7304      GIR_Done,
7305    // Label 376: @17157
7306    GIM_Try, /*On fail goto*//*Label 377*/ 17195, // Rule ID 2408 //
7307      GIM_CheckFeatures, GIFBS_IsBE,
7308      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7309      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7310      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7311      // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src)  =>  (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src)
7312      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
7313      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7314      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7315      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7316      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7317      GIR_EraseFromParent, /*InsnID*/0,
7318      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7319      // GIR_Coverage, 2408,
7320      GIR_Done,
7321    // Label 377: @17195
7322    GIM_Try, /*On fail goto*//*Label 378*/ 17233, // Rule ID 2409 //
7323      GIM_CheckFeatures, GIFBS_IsBE,
7324      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7325      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7326      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7327      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)
7328      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
7329      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7330      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7331      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7332      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7333      GIR_EraseFromParent, /*InsnID*/0,
7334      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7335      // GIR_Coverage, 2409,
7336      GIR_Done,
7337    // Label 378: @17233
7338    GIM_Try, /*On fail goto*//*Label 379*/ 17271, // Rule ID 2410 //
7339      GIM_CheckFeatures, GIFBS_IsBE,
7340      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
7341      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7342      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7343      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)  =>  (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)
7344      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
7345      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7346      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7347      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7348      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7349      GIR_EraseFromParent, /*InsnID*/0,
7350      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7351      // GIR_Coverage, 2410,
7352      GIR_Done,
7353    // Label 379: @17271
7354    GIM_Try, /*On fail goto*//*Label 380*/ 17309, // Rule ID 2411 //
7355      GIM_CheckFeatures, GIFBS_IsBE,
7356      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
7357      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7358      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7359      // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)  =>  (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)
7360      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
7361      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7362      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7363      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7364      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7365      GIR_EraseFromParent, /*InsnID*/0,
7366      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7367      // GIR_Coverage, 2411,
7368      GIR_Done,
7369    // Label 380: @17309
7370    GIM_Reject,
7371    // Label 333: @17310
7372    GIM_Try, /*On fail goto*//*Label 381*/ 17344, // Rule ID 2353 //
7373      GIM_CheckFeatures, GIFBS_IsLE,
7374      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7375      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7376      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7377      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v2i64] }:$src
7378      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7379      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7380      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7381      GIR_EraseFromParent, /*InsnID*/0,
7382      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7383      // GIR_Coverage, 2353,
7384      GIR_Done,
7385    // Label 381: @17344
7386    GIM_Try, /*On fail goto*//*Label 382*/ 17378, // Rule ID 2354 //
7387      GIM_CheckFeatures, GIFBS_IsLE,
7388      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7389      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7390      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7391      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v2i64] }:$src
7392      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7393      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7394      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7395      GIR_EraseFromParent, /*InsnID*/0,
7396      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7397      // GIR_Coverage, 2354,
7398      GIR_Done,
7399    // Label 382: @17378
7400    GIM_Try, /*On fail goto*//*Label 383*/ 17412, // Rule ID 2355 //
7401      GIM_CheckFeatures, GIFBS_IsLE,
7402      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
7403      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7404      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7405      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v2i64] }:$src
7406      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7407      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7408      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7409      GIR_EraseFromParent, /*InsnID*/0,
7410      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7411      // GIR_Coverage, 2355,
7412      GIR_Done,
7413    // Label 383: @17412
7414    GIM_Try, /*On fail goto*//*Label 384*/ 17444, // Rule ID 2356 //
7415      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7416      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7417      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7418      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v2i64] }:$src
7419      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7420      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7421      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7422      GIR_EraseFromParent, /*InsnID*/0,
7423      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7424      // GIR_Coverage, 2356,
7425      GIR_Done,
7426    // Label 384: @17444
7427    GIM_Try, /*On fail goto*//*Label 385*/ 17478, // Rule ID 2357 //
7428      GIM_CheckFeatures, GIFBS_IsLE,
7429      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7430      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7431      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7432      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v2i64] }:$src
7433      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7434      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7435      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7436      GIR_EraseFromParent, /*InsnID*/0,
7437      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7438      // GIR_Coverage, 2357,
7439      GIR_Done,
7440    // Label 385: @17478
7441    GIM_Try, /*On fail goto*//*Label 386*/ 17510, // Rule ID 2379 //
7442      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7443      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7444      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7445      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v2f64] }:$src
7446      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7447      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7448      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7449      GIR_EraseFromParent, /*InsnID*/0,
7450      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7451      // GIR_Coverage, 2379,
7452      GIR_Done,
7453    // Label 386: @17510
7454    GIM_Try, /*On fail goto*//*Label 387*/ 17544, // Rule ID 2380 //
7455      GIM_CheckFeatures, GIFBS_IsLE,
7456      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7457      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7458      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7459      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v2f64] }:$src
7460      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7461      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7462      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7463      GIR_EraseFromParent, /*InsnID*/0,
7464      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7465      // GIR_Coverage, 2380,
7466      GIR_Done,
7467    // Label 387: @17544
7468    GIM_Try, /*On fail goto*//*Label 388*/ 17578, // Rule ID 2381 //
7469      GIM_CheckFeatures, GIFBS_IsLE,
7470      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7471      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7472      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7473      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
7474      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7475      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7476      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7477      GIR_EraseFromParent, /*InsnID*/0,
7478      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7479      // GIR_Coverage, 2381,
7480      GIR_Done,
7481    // Label 388: @17578
7482    GIM_Try, /*On fail goto*//*Label 389*/ 17612, // Rule ID 2382 //
7483      GIM_CheckFeatures, GIFBS_IsLE,
7484      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7485      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7486      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7487      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)  =>  QPR:{ *:[v2f64] }:$src
7488      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7489      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7490      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7491      GIR_EraseFromParent, /*InsnID*/0,
7492      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7493      // GIR_Coverage, 2382,
7494      GIR_Done,
7495    // Label 389: @17612
7496    GIM_Try, /*On fail goto*//*Label 390*/ 17646, // Rule ID 2383 //
7497      GIM_CheckFeatures, GIFBS_IsLE,
7498      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
7499      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7500      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7501      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v2f64] }:$src
7502      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7503      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7504      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7505      GIR_EraseFromParent, /*InsnID*/0,
7506      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7507      // GIR_Coverage, 2383,
7508      GIR_Done,
7509    // Label 390: @17646
7510    GIM_Try, /*On fail goto*//*Label 391*/ 17680, // Rule ID 2384 //
7511      GIM_CheckFeatures, GIFBS_IsLE,
7512      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7513      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7514      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7515      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v2f64] }:$src
7516      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7517      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7518      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7519      GIR_EraseFromParent, /*InsnID*/0,
7520      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7521      // GIR_Coverage, 2384,
7522      GIR_Done,
7523    // Label 391: @17680
7524    GIM_Try, /*On fail goto*//*Label 392*/ 17718, // Rule ID 2412 //
7525      GIM_CheckFeatures, GIFBS_IsBE,
7526      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7527      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7529      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)  =>  (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)
7530      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
7531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7533      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7534      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7535      GIR_EraseFromParent, /*InsnID*/0,
7536      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7537      // GIR_Coverage, 2412,
7538      GIR_Done,
7539    // Label 392: @17718
7540    GIM_Try, /*On fail goto*//*Label 393*/ 17756, // Rule ID 2413 //
7541      GIM_CheckFeatures, GIFBS_IsBE,
7542      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7543      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7544      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7545      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)  =>  (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)
7546      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
7547      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7548      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7549      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7550      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7551      GIR_EraseFromParent, /*InsnID*/0,
7552      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7553      // GIR_Coverage, 2413,
7554      GIR_Done,
7555    // Label 393: @17756
7556    GIM_Try, /*On fail goto*//*Label 394*/ 17794, // Rule ID 2414 //
7557      GIM_CheckFeatures, GIFBS_IsBE,
7558      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
7559      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7560      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7561      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)  =>  (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)
7562      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
7563      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7564      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7565      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7566      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7567      GIR_EraseFromParent, /*InsnID*/0,
7568      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7569      // GIR_Coverage, 2414,
7570      GIR_Done,
7571    // Label 394: @17794
7572    GIM_Try, /*On fail goto*//*Label 395*/ 17832, // Rule ID 2415 //
7573      GIM_CheckFeatures, GIFBS_IsBE,
7574      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7575      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7576      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7577      // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)  =>  (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)
7578      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
7579      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7580      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7581      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7582      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7583      GIR_EraseFromParent, /*InsnID*/0,
7584      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7585      // GIR_Coverage, 2415,
7586      GIR_Done,
7587    // Label 395: @17832
7588    GIM_Try, /*On fail goto*//*Label 396*/ 17870, // Rule ID 2436 //
7589      GIM_CheckFeatures, GIFBS_IsBE,
7590      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7591      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7592      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7593      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)  =>  (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)
7594      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
7595      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7596      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7597      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7598      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7599      GIR_EraseFromParent, /*InsnID*/0,
7600      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7601      // GIR_Coverage, 2436,
7602      GIR_Done,
7603    // Label 396: @17870
7604    GIM_Try, /*On fail goto*//*Label 397*/ 17908, // Rule ID 2437 //
7605      GIM_CheckFeatures, GIFBS_IsBE,
7606      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7607      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7608      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7609      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)
7610      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
7611      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7612      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7613      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7614      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7615      GIR_EraseFromParent, /*InsnID*/0,
7616      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7617      // GIR_Coverage, 2437,
7618      GIR_Done,
7619    // Label 397: @17908
7620    GIM_Try, /*On fail goto*//*Label 398*/ 17946, // Rule ID 2438 //
7621      GIM_CheckFeatures, GIFBS_IsBE,
7622      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7623      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7624      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7625      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)  =>  (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)
7626      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
7627      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7628      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7629      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7630      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7631      GIR_EraseFromParent, /*InsnID*/0,
7632      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7633      // GIR_Coverage, 2438,
7634      GIR_Done,
7635    // Label 398: @17946
7636    GIM_Try, /*On fail goto*//*Label 399*/ 17984, // Rule ID 2439 //
7637      GIM_CheckFeatures, GIFBS_IsBE,
7638      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
7639      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7640      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7641      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)  =>  (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)
7642      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
7643      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7644      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7645      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7646      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7647      GIR_EraseFromParent, /*InsnID*/0,
7648      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7649      // GIR_Coverage, 2439,
7650      GIR_Done,
7651    // Label 399: @17984
7652    GIM_Try, /*On fail goto*//*Label 400*/ 18022, // Rule ID 2440 //
7653      GIM_CheckFeatures, GIFBS_IsBE,
7654      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7655      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7656      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7657      // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)  =>  (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)
7658      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
7659      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7660      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7661      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7662      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7663      GIR_EraseFromParent, /*InsnID*/0,
7664      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7665      // GIR_Coverage, 2440,
7666      GIR_Done,
7667    // Label 400: @18022
7668    GIM_Reject,
7669    // Label 334: @18023
7670    GIM_Try, /*On fail goto*//*Label 401*/ 18057, // Rule ID 2331 //
7671      GIM_CheckFeatures, GIFBS_IsLE,
7672      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7673      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7674      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7675      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v4i16] }:$src
7676      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7677      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7678      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7679      GIR_EraseFromParent, /*InsnID*/0,
7680      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7681      // GIR_Coverage, 2331,
7682      GIR_Done,
7683    // Label 401: @18057
7684    GIM_Try, /*On fail goto*//*Label 402*/ 18091, // Rule ID 2332 //
7685      GIM_CheckFeatures, GIFBS_IsLE,
7686      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7687      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7688      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7689      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v4i16] }:$src
7690      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7691      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7692      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7693      GIR_EraseFromParent, /*InsnID*/0,
7694      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7695      // GIR_Coverage, 2332,
7696      GIR_Done,
7697    // Label 402: @18091
7698    GIM_Try, /*On fail goto*//*Label 403*/ 18125, // Rule ID 2333 //
7699      GIM_CheckFeatures, GIFBS_IsLE,
7700      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
7701      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7702      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7703      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)  =>  DPR:{ *:[v4i16] }:$src
7704      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7705      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7706      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7707      GIR_EraseFromParent, /*InsnID*/0,
7708      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7709      // GIR_Coverage, 2333,
7710      GIR_Done,
7711    // Label 403: @18125
7712    GIM_Try, /*On fail goto*//*Label 404*/ 18159, // Rule ID 2334 //
7713      GIM_CheckFeatures, GIFBS_IsLE,
7714      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7715      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7716      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7717      // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4i16] }:$src
7718      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7719      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7720      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7721      GIR_EraseFromParent, /*InsnID*/0,
7722      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7723      // GIR_Coverage, 2334,
7724      GIR_Done,
7725    // Label 404: @18159
7726    GIM_Try, /*On fail goto*//*Label 405*/ 18193, // Rule ID 2335 //
7727      GIM_CheckFeatures, GIFBS_IsLE,
7728      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7729      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7730      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7731      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v4i16] }:$src
7732      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7733      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7734      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7735      GIR_EraseFromParent, /*InsnID*/0,
7736      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7737      // GIR_Coverage, 2335,
7738      GIR_Done,
7739    // Label 405: @18193
7740    GIM_Try, /*On fail goto*//*Label 406*/ 18227, // Rule ID 2348 //
7741      GIM_CheckFeatures, GIFBS_IsLE,
7742      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7743      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7744      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7745      // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v4f16] }:$src
7746      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7747      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7748      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7749      GIR_EraseFromParent, /*InsnID*/0,
7750      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
7751      // GIR_Coverage, 2348,
7752      GIR_Done,
7753    // Label 406: @18227
7754    GIM_Try, /*On fail goto*//*Label 407*/ 18265, // Rule ID 2393 //
7755      GIM_CheckFeatures, GIFBS_IsBE,
7756      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7757      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7758      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7759      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)
7760      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
7761      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7762      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7763      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7764      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7765      GIR_EraseFromParent, /*InsnID*/0,
7766      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7767      // GIR_Coverage, 2393,
7768      GIR_Done,
7769    // Label 407: @18265
7770    GIM_Try, /*On fail goto*//*Label 408*/ 18303, // Rule ID 2394 //
7771      GIM_CheckFeatures, GIFBS_IsBE,
7772      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7773      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7774      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7775      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)
7776      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
7777      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7778      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7779      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7780      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7781      GIR_EraseFromParent, /*InsnID*/0,
7782      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7783      // GIR_Coverage, 2394,
7784      GIR_Done,
7785    // Label 408: @18303
7786    GIM_Try, /*On fail goto*//*Label 409*/ 18341, // Rule ID 2395 //
7787      GIM_CheckFeatures, GIFBS_IsBE,
7788      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
7789      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7790      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7791      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)  =>  (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)
7792      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
7793      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7794      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7795      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7796      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7797      GIR_EraseFromParent, /*InsnID*/0,
7798      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7799      // GIR_Coverage, 2395,
7800      GIR_Done,
7801    // Label 409: @18341
7802    GIM_Try, /*On fail goto*//*Label 410*/ 18379, // Rule ID 2396 //
7803      GIM_CheckFeatures, GIFBS_IsBE,
7804      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
7805      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7806      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7807      // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src)  =>  (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src)
7808      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
7809      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7810      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7811      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7812      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7813      GIR_EraseFromParent, /*InsnID*/0,
7814      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7815      // GIR_Coverage, 2396,
7816      GIR_Done,
7817    // Label 410: @18379
7818    GIM_Try, /*On fail goto*//*Label 411*/ 18417, // Rule ID 2397 //
7819      GIM_CheckFeatures, GIFBS_IsBE,
7820      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
7821      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
7822      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
7823      // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)
7824      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d16,
7825      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7826      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7827      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7828      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7829      GIR_EraseFromParent, /*InsnID*/0,
7830      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7831      // GIR_Coverage, 2397,
7832      GIR_Done,
7833    // Label 411: @18417
7834    GIM_Reject,
7835    // Label 335: @18418
7836    GIM_Try, /*On fail goto*//*Label 412*/ 18452, // Rule ID 2358 //
7837      GIM_CheckFeatures, GIFBS_IsLE,
7838      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7839      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7840      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7841      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v4i32] }:$src
7842      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7843      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7844      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7845      GIR_EraseFromParent, /*InsnID*/0,
7846      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7847      // GIR_Coverage, 2358,
7848      GIR_Done,
7849    // Label 412: @18452
7850    GIM_Try, /*On fail goto*//*Label 413*/ 18486, // Rule ID 2359 //
7851      GIM_CheckFeatures, GIFBS_IsLE,
7852      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7853      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7854      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7855      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v4i32] }:$src
7856      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7857      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7858      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7859      GIR_EraseFromParent, /*InsnID*/0,
7860      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7861      // GIR_Coverage, 2359,
7862      GIR_Done,
7863    // Label 413: @18486
7864    GIM_Try, /*On fail goto*//*Label 414*/ 18520, // Rule ID 2360 //
7865      GIM_CheckFeatures, GIFBS_IsLE,
7866      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
7867      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7868      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7869      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v4i32] }:$src
7870      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7871      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7872      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7873      GIR_EraseFromParent, /*InsnID*/0,
7874      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7875      // GIR_Coverage, 2360,
7876      GIR_Done,
7877    // Label 414: @18520
7878    GIM_Try, /*On fail goto*//*Label 415*/ 18554, // Rule ID 2361 //
7879      GIM_CheckFeatures, GIFBS_IsLE,
7880      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7881      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7882      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7883      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v4i32] }:$src
7884      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7885      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7886      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7887      GIR_EraseFromParent, /*InsnID*/0,
7888      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7889      // GIR_Coverage, 2361,
7890      GIR_Done,
7891    // Label 415: @18554
7892    GIM_Try, /*On fail goto*//*Label 416*/ 18586, // Rule ID 2362 //
7893      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7894      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7895      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7896      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v4i32] }:$src
7897      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7898      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7899      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7900      GIR_EraseFromParent, /*InsnID*/0,
7901      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7902      // GIR_Coverage, 2362,
7903      GIR_Done,
7904    // Label 416: @18586
7905    GIM_Try, /*On fail goto*//*Label 417*/ 18620, // Rule ID 2374 //
7906      GIM_CheckFeatures, GIFBS_IsLE,
7907      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7908      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7909      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7910      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v4f32] }:$src
7911      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7912      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7913      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7914      GIR_EraseFromParent, /*InsnID*/0,
7915      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7916      // GIR_Coverage, 2374,
7917      GIR_Done,
7918    // Label 417: @18620
7919    GIM_Try, /*On fail goto*//*Label 418*/ 18652, // Rule ID 2375 //
7920      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
7921      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7922      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7923      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v4f32] }:$src
7924      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7925      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7926      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7927      GIR_EraseFromParent, /*InsnID*/0,
7928      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7929      // GIR_Coverage, 2375,
7930      GIR_Done,
7931    // Label 418: @18652
7932    GIM_Try, /*On fail goto*//*Label 419*/ 18686, // Rule ID 2376 //
7933      GIM_CheckFeatures, GIFBS_IsLE,
7934      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7935      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7936      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7937      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v4f32] }:$src
7938      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7939      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7940      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7941      GIR_EraseFromParent, /*InsnID*/0,
7942      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7943      // GIR_Coverage, 2376,
7944      GIR_Done,
7945    // Label 419: @18686
7946    GIM_Try, /*On fail goto*//*Label 420*/ 18720, // Rule ID 2377 //
7947      GIM_CheckFeatures, GIFBS_IsLE,
7948      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
7949      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7950      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7951      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v4f32] }:$src
7952      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7953      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7954      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7955      GIR_EraseFromParent, /*InsnID*/0,
7956      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7957      // GIR_Coverage, 2377,
7958      GIR_Done,
7959    // Label 420: @18720
7960    GIM_Try, /*On fail goto*//*Label 421*/ 18754, // Rule ID 2378 //
7961      GIM_CheckFeatures, GIFBS_IsLE,
7962      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7963      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7964      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7965      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v4f32] }:$src
7966      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7967      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
7968      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7969      GIR_EraseFromParent, /*InsnID*/0,
7970      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
7971      // GIR_Coverage, 2378,
7972      GIR_Done,
7973    // Label 421: @18754
7974    GIM_Try, /*On fail goto*//*Label 422*/ 18792, // Rule ID 2416 //
7975      GIM_CheckFeatures, GIFBS_IsBE,
7976      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
7977      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7978      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7979      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)
7980      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
7981      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7982      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7983      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
7984      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
7985      GIR_EraseFromParent, /*InsnID*/0,
7986      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
7987      // GIR_Coverage, 2416,
7988      GIR_Done,
7989    // Label 422: @18792
7990    GIM_Try, /*On fail goto*//*Label 423*/ 18830, // Rule ID 2417 //
7991      GIM_CheckFeatures, GIFBS_IsBE,
7992      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
7993      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
7994      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
7995      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)  =>  (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)
7996      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
7997      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
7998      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
7999      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8000      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8001      GIR_EraseFromParent, /*InsnID*/0,
8002      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8003      // GIR_Coverage, 2417,
8004      GIR_Done,
8005    // Label 423: @18830
8006    GIM_Try, /*On fail goto*//*Label 424*/ 18868, // Rule ID 2418 //
8007      GIM_CheckFeatures, GIFBS_IsBE,
8008      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8009      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8010      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8011      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)  =>  (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)
8012      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
8013      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8014      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8015      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8016      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8017      GIR_EraseFromParent, /*InsnID*/0,
8018      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8019      // GIR_Coverage, 2418,
8020      GIR_Done,
8021    // Label 424: @18868
8022    GIM_Try, /*On fail goto*//*Label 425*/ 18906, // Rule ID 2419 //
8023      GIM_CheckFeatures, GIFBS_IsBE,
8024      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8025      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8026      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8027      // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)
8028      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8029      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8030      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8031      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8032      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8033      GIR_EraseFromParent, /*InsnID*/0,
8034      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8035      // GIR_Coverage, 2419,
8036      GIR_Done,
8037    // Label 425: @18906
8038    GIM_Try, /*On fail goto*//*Label 426*/ 18944, // Rule ID 2431 //
8039      GIM_CheckFeatures, GIFBS_IsBE,
8040      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8041      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8042      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8043      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)
8044      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8045      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8046      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8047      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8048      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8049      GIR_EraseFromParent, /*InsnID*/0,
8050      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8051      // GIR_Coverage, 2431,
8052      GIR_Done,
8053    // Label 426: @18944
8054    GIM_Try, /*On fail goto*//*Label 427*/ 18982, // Rule ID 2432 //
8055      GIM_CheckFeatures, GIFBS_IsBE,
8056      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8057      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8058      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8059      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)
8060      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
8061      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8062      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8063      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8064      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8065      GIR_EraseFromParent, /*InsnID*/0,
8066      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8067      // GIR_Coverage, 2432,
8068      GIR_Done,
8069    // Label 427: @18982
8070    GIM_Try, /*On fail goto*//*Label 428*/ 19020, // Rule ID 2433 //
8071      GIM_CheckFeatures, GIFBS_IsBE,
8072      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8073      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8074      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8075      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)  =>  (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)
8076      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
8077      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8078      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8079      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8080      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8081      GIR_EraseFromParent, /*InsnID*/0,
8082      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8083      // GIR_Coverage, 2433,
8084      GIR_Done,
8085    // Label 428: @19020
8086    GIM_Try, /*On fail goto*//*Label 429*/ 19058, // Rule ID 2434 //
8087      GIM_CheckFeatures, GIFBS_IsBE,
8088      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8089      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8090      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8091      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)  =>  (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)
8092      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
8093      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8094      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8095      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8096      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8097      GIR_EraseFromParent, /*InsnID*/0,
8098      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8099      // GIR_Coverage, 2434,
8100      GIR_Done,
8101    // Label 429: @19058
8102    GIM_Try, /*On fail goto*//*Label 430*/ 19096, // Rule ID 2435 //
8103      GIM_CheckFeatures, GIFBS_IsBE,
8104      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8105      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8106      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8107      // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)
8108      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8109      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8110      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8111      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8112      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8113      GIR_EraseFromParent, /*InsnID*/0,
8114      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8115      // GIR_Coverage, 2435,
8116      GIR_Done,
8117    // Label 430: @19096
8118    GIM_Reject,
8119    // Label 336: @19097
8120    GIM_Try, /*On fail goto*//*Label 431*/ 19131, // Rule ID 2336 //
8121      GIM_CheckFeatures, GIFBS_IsLE,
8122      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8123      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8124      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8125      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)  =>  DPR:{ *:[v8i8] }:$src
8126      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8127      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8128      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8129      GIR_EraseFromParent, /*InsnID*/0,
8130      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
8131      // GIR_Coverage, 2336,
8132      GIR_Done,
8133    // Label 431: @19131
8134    GIM_Try, /*On fail goto*//*Label 432*/ 19165, // Rule ID 2337 //
8135      GIM_CheckFeatures, GIFBS_IsLE,
8136      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8137      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8138      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8139      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)  =>  DPR:{ *:[v8i8] }:$src
8140      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8141      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8142      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8143      GIR_EraseFromParent, /*InsnID*/0,
8144      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
8145      // GIR_Coverage, 2337,
8146      GIR_Done,
8147    // Label 432: @19165
8148    GIM_Try, /*On fail goto*//*Label 433*/ 19199, // Rule ID 2338 //
8149      GIM_CheckFeatures, GIFBS_IsLE,
8150      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8151      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8152      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8153      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)  =>  DPR:{ *:[v8i8] }:$src
8154      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8155      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8156      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8157      GIR_EraseFromParent, /*InsnID*/0,
8158      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
8159      // GIR_Coverage, 2338,
8160      GIR_Done,
8161    // Label 433: @19199
8162    GIM_Try, /*On fail goto*//*Label 434*/ 19233, // Rule ID 2339 //
8163      GIM_CheckFeatures, GIFBS_IsLE,
8164      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8165      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8166      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8167      // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src)  =>  DPR:{ *:[v8i8] }:$src
8168      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8169      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8170      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8171      GIR_EraseFromParent, /*InsnID*/0,
8172      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
8173      // GIR_Coverage, 2339,
8174      GIR_Done,
8175    // Label 434: @19233
8176    GIM_Try, /*On fail goto*//*Label 435*/ 19267, // Rule ID 2340 //
8177      GIM_CheckFeatures, GIFBS_IsLE,
8178      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8179      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8180      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8181      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)  =>  DPR:{ *:[v8i8] }:$src
8182      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8183      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8184      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8185      GIR_EraseFromParent, /*InsnID*/0,
8186      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DPR*/18,
8187      // GIR_Coverage, 2340,
8188      GIR_Done,
8189    // Label 435: @19267
8190    GIM_Try, /*On fail goto*//*Label 436*/ 19305, // Rule ID 2398 //
8191      GIM_CheckFeatures, GIFBS_IsBE,
8192      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8193      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8194      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8195      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)  =>  (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)
8196      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
8197      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8198      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8199      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8200      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8201      GIR_EraseFromParent, /*InsnID*/0,
8202      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8203      // GIR_Coverage, 2398,
8204      GIR_Done,
8205    // Label 436: @19305
8206    GIM_Try, /*On fail goto*//*Label 437*/ 19343, // Rule ID 2399 //
8207      GIM_CheckFeatures, GIFBS_IsBE,
8208      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8209      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8210      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8211      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)  =>  (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)
8212      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
8213      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8214      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8215      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8216      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8217      GIR_EraseFromParent, /*InsnID*/0,
8218      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8219      // GIR_Coverage, 2399,
8220      GIR_Done,
8221    // Label 437: @19343
8222    GIM_Try, /*On fail goto*//*Label 438*/ 19381, // Rule ID 2400 //
8223      GIM_CheckFeatures, GIFBS_IsBE,
8224      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
8225      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8226      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8227      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)  =>  (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)
8228      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16d8,
8229      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8230      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8231      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8232      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8233      GIR_EraseFromParent, /*InsnID*/0,
8234      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8235      // GIR_Coverage, 2400,
8236      GIR_Done,
8237    // Label 438: @19381
8238    GIM_Try, /*On fail goto*//*Label 439*/ 19419, // Rule ID 2401 //
8239      GIM_CheckFeatures, GIFBS_IsBE,
8240      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
8241      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8242      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8243      // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src)  =>  (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src)
8244      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d8,
8245      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8246      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8247      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8248      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8249      GIR_EraseFromParent, /*InsnID*/0,
8250      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8251      // GIR_Coverage, 2401,
8252      GIR_Done,
8253    // Label 439: @19419
8254    GIM_Try, /*On fail goto*//*Label 440*/ 19457, // Rule ID 2402 //
8255      GIM_CheckFeatures, GIFBS_IsBE,
8256      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
8257      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8258      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
8259      // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)  =>  (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)
8260      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32d8,
8261      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8262      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8263      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8264      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8265      GIR_EraseFromParent, /*InsnID*/0,
8266      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8267      // GIR_Coverage, 2402,
8268      GIR_Done,
8269    // Label 440: @19457
8270    GIM_Reject,
8271    // Label 337: @19458
8272    GIM_Try, /*On fail goto*//*Label 441*/ 19492, // Rule ID 2363 //
8273      GIM_CheckFeatures, GIFBS_IsLE,
8274      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8275      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8276      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8277      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v8i16] }:$src
8278      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8279      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8280      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8281      GIR_EraseFromParent, /*InsnID*/0,
8282      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8283      // GIR_Coverage, 2363,
8284      GIR_Done,
8285    // Label 441: @19492
8286    GIM_Try, /*On fail goto*//*Label 442*/ 19526, // Rule ID 2364 //
8287      GIM_CheckFeatures, GIFBS_IsLE,
8288      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8289      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8290      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8291      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v8i16] }:$src
8292      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8293      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8294      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8295      GIR_EraseFromParent, /*InsnID*/0,
8296      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8297      // GIR_Coverage, 2364,
8298      GIR_Done,
8299    // Label 442: @19526
8300    GIM_Try, /*On fail goto*//*Label 443*/ 19560, // Rule ID 2365 //
8301      GIM_CheckFeatures, GIFBS_IsLE,
8302      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8303      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8304      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8305      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)  =>  QPR:{ *:[v8i16] }:$src
8306      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8307      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8308      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8309      GIR_EraseFromParent, /*InsnID*/0,
8310      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8311      // GIR_Coverage, 2365,
8312      GIR_Done,
8313    // Label 443: @19560
8314    GIM_Try, /*On fail goto*//*Label 444*/ 19594, // Rule ID 2366 //
8315      GIM_CheckFeatures, GIFBS_IsLE,
8316      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8317      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8318      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8319      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8i16] }:$src
8320      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8321      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8322      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8323      GIR_EraseFromParent, /*InsnID*/0,
8324      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8325      // GIR_Coverage, 2366,
8326      GIR_Done,
8327    // Label 444: @19594
8328    GIM_Try, /*On fail goto*//*Label 445*/ 19628, // Rule ID 2367 //
8329      GIM_CheckFeatures, GIFBS_IsLE,
8330      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8331      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8333      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v8i16] }:$src
8334      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8335      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8336      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8337      GIR_EraseFromParent, /*InsnID*/0,
8338      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8339      // GIR_Coverage, 2367,
8340      GIR_Done,
8341    // Label 445: @19628
8342    GIM_Try, /*On fail goto*//*Label 446*/ 19662, // Rule ID 2368 //
8343      GIM_CheckFeatures, GIFBS_IsLE,
8344      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8345      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8346      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8347      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v8f16] }:$src
8348      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8349      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8350      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8351      GIR_EraseFromParent, /*InsnID*/0,
8352      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8353      // GIR_Coverage, 2368,
8354      GIR_Done,
8355    // Label 446: @19662
8356    GIM_Try, /*On fail goto*//*Label 447*/ 19700, // Rule ID 2420 //
8357      GIM_CheckFeatures, GIFBS_IsBE,
8358      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8359      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8360      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8361      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)
8362      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
8363      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8364      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8365      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8366      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8367      GIR_EraseFromParent, /*InsnID*/0,
8368      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8369      // GIR_Coverage, 2420,
8370      GIR_Done,
8371    // Label 447: @19700
8372    GIM_Try, /*On fail goto*//*Label 448*/ 19738, // Rule ID 2421 //
8373      GIM_CheckFeatures, GIFBS_IsBE,
8374      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8375      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8376      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8377      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)
8378      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
8379      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8380      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8381      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8382      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8383      GIR_EraseFromParent, /*InsnID*/0,
8384      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8385      // GIR_Coverage, 2421,
8386      GIR_Done,
8387    // Label 448: @19738
8388    GIM_Try, /*On fail goto*//*Label 449*/ 19776, // Rule ID 2422 //
8389      GIM_CheckFeatures, GIFBS_IsBE,
8390      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
8391      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8393      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)  =>  (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)
8394      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
8395      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8396      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8397      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8398      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8399      GIR_EraseFromParent, /*InsnID*/0,
8400      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8401      // GIR_Coverage, 2422,
8402      GIR_Done,
8403    // Label 449: @19776
8404    GIM_Try, /*On fail goto*//*Label 450*/ 19814, // Rule ID 2423 //
8405      GIM_CheckFeatures, GIFBS_IsBE,
8406      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8407      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8408      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8409      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)
8410      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
8411      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8412      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8413      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8414      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8415      GIR_EraseFromParent, /*InsnID*/0,
8416      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8417      // GIR_Coverage, 2423,
8418      GIR_Done,
8419    // Label 450: @19814
8420    GIM_Try, /*On fail goto*//*Label 451*/ 19852, // Rule ID 2424 //
8421      GIM_CheckFeatures, GIFBS_IsBE,
8422      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8423      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8424      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8425      // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)
8426      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
8427      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8428      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8429      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8430      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8431      GIR_EraseFromParent, /*InsnID*/0,
8432      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8433      // GIR_Coverage, 2424,
8434      GIR_Done,
8435    // Label 451: @19852
8436    GIM_Try, /*On fail goto*//*Label 452*/ 19890, // Rule ID 2425 //
8437      GIM_CheckFeatures, GIFBS_IsBE,
8438      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8439      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8440      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8441      // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)
8442      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q16,
8443      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8444      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8445      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8446      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8447      GIR_EraseFromParent, /*InsnID*/0,
8448      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8449      // GIR_Coverage, 2425,
8450      GIR_Done,
8451    // Label 452: @19890
8452    GIM_Reject,
8453    // Label 338: @19891
8454    GIM_Try, /*On fail goto*//*Label 453*/ 19925, // Rule ID 2369 //
8455      GIM_CheckFeatures, GIFBS_IsLE,
8456      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8457      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8458      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8459      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)  =>  QPR:{ *:[v16i8] }:$src
8460      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8461      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8462      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8463      GIR_EraseFromParent, /*InsnID*/0,
8464      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8465      // GIR_Coverage, 2369,
8466      GIR_Done,
8467    // Label 453: @19925
8468    GIM_Try, /*On fail goto*//*Label 454*/ 19959, // Rule ID 2370 //
8469      GIM_CheckFeatures, GIFBS_IsLE,
8470      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8471      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8472      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8473      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)  =>  QPR:{ *:[v16i8] }:$src
8474      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8475      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8476      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8477      GIR_EraseFromParent, /*InsnID*/0,
8478      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8479      // GIR_Coverage, 2370,
8480      GIR_Done,
8481    // Label 454: @19959
8482    GIM_Try, /*On fail goto*//*Label 455*/ 19993, // Rule ID 2371 //
8483      GIM_CheckFeatures, GIFBS_IsLE,
8484      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8485      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8486      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8487      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)  =>  QPR:{ *:[v16i8] }:$src
8488      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8489      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8490      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8491      GIR_EraseFromParent, /*InsnID*/0,
8492      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8493      // GIR_Coverage, 2371,
8494      GIR_Done,
8495    // Label 455: @19993
8496    GIM_Try, /*On fail goto*//*Label 456*/ 20027, // Rule ID 2372 //
8497      GIM_CheckFeatures, GIFBS_IsLE,
8498      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8499      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8500      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8501      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)  =>  QPR:{ *:[v16i8] }:$src
8502      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8503      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8504      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8505      GIR_EraseFromParent, /*InsnID*/0,
8506      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8507      // GIR_Coverage, 2372,
8508      GIR_Done,
8509    // Label 456: @20027
8510    GIM_Try, /*On fail goto*//*Label 457*/ 20061, // Rule ID 2373 //
8511      GIM_CheckFeatures, GIFBS_IsLE,
8512      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8513      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8514      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8515      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)  =>  QPR:{ *:[v16i8] }:$src
8516      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8517      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
8518      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8519      GIR_EraseFromParent, /*InsnID*/0,
8520      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC QPR*/36,
8521      // GIR_Coverage, 2373,
8522      GIR_Done,
8523    // Label 457: @20061
8524    GIM_Try, /*On fail goto*//*Label 458*/ 20099, // Rule ID 2426 //
8525      GIM_CheckFeatures, GIFBS_IsBE,
8526      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8527      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8528      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8529      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)  =>  (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)
8530      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
8531      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8532      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8533      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8534      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8535      GIR_EraseFromParent, /*InsnID*/0,
8536      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8537      // GIR_Coverage, 2426,
8538      GIR_Done,
8539    // Label 458: @20099
8540    GIM_Try, /*On fail goto*//*Label 459*/ 20137, // Rule ID 2427 //
8541      GIM_CheckFeatures, GIFBS_IsBE,
8542      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8543      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8544      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8545      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)  =>  (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)
8546      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
8547      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8548      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8549      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8550      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8551      GIR_EraseFromParent, /*InsnID*/0,
8552      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8553      // GIR_Coverage, 2427,
8554      GIR_Done,
8555    // Label 459: @20137
8556    GIM_Try, /*On fail goto*//*Label 460*/ 20175, // Rule ID 2428 //
8557      GIM_CheckFeatures, GIFBS_IsBE,
8558      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
8559      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8560      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8561      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)  =>  (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)
8562      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV16q8,
8563      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8564      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8565      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8566      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8567      GIR_EraseFromParent, /*InsnID*/0,
8568      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8569      // GIR_Coverage, 2428,
8570      GIR_Done,
8571    // Label 460: @20175
8572    GIM_Try, /*On fail goto*//*Label 461*/ 20213, // Rule ID 2429 //
8573      GIM_CheckFeatures, GIFBS_IsBE,
8574      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
8575      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8576      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8577      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)  =>  (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)
8578      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q8,
8579      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8580      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8581      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8582      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8583      GIR_EraseFromParent, /*InsnID*/0,
8584      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8585      // GIR_Coverage, 2429,
8586      GIR_Done,
8587    // Label 461: @20213
8588    GIM_Try, /*On fail goto*//*Label 462*/ 20251, // Rule ID 2430 //
8589      GIM_CheckFeatures, GIFBS_IsBE,
8590      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
8591      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8592      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
8593      // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)  =>  (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)
8594      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV32q8,
8595      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8596      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
8597      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8598      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8599      GIR_EraseFromParent, /*InsnID*/0,
8600      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8601      // GIR_Coverage, 2430,
8602      GIR_Done,
8603    // Label 462: @20251
8604    GIM_Reject,
8605    // Label 339: @20252
8606    GIM_Reject,
8607    // Label 9: @20253
8608    GIM_Try, /*On fail goto*//*Label 463*/ 25477,
8609      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
8610      GIM_Try, /*On fail goto*//*Label 464*/ 20307, // Rule ID 1708 //
8611        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
8612        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16,
8613        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8614        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
8616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
8617        // (intrinsic_wo_chain:{ *:[i32] } 1217:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src)  =>  (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
8618        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB16,
8619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
8621        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8622        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8623        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8624        GIR_EraseFromParent, /*InsnID*/0,
8625        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8626        // GIR_Coverage, 1708,
8627        GIR_Done,
8628      // Label 464: @20307
8629      GIM_Try, /*On fail goto*//*Label 465*/ 20356, // Rule ID 1908 //
8630        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
8631        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtb16,
8632        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8633        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
8635        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
8636        // (intrinsic_wo_chain:{ *:[i32] } 1217:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm)  =>  (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
8637        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTB16,
8638        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
8639        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
8640        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
8641        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8642        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8643        GIR_EraseFromParent, /*InsnID*/0,
8644        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8645        // GIR_Coverage, 1908,
8646        GIR_Done,
8647      // Label 465: @20356
8648      GIM_Try, /*On fail goto*//*Label 466*/ 20396, // Rule ID 678 //
8649        GIM_CheckFeatures, GIFBS_HasFPARMv8,
8650        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
8651        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8652        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
8654        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
8655        // (intrinsic_wo_chain:{ *:[f32] } 1103:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
8656        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNS,
8657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
8658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
8659        GIR_EraseFromParent, /*InsnID*/0,
8660        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8661        // GIR_Coverage, 678,
8662        GIR_Done,
8663      // Label 466: @20396
8664      GIM_Try, /*On fail goto*//*Label 467*/ 20436, // Rule ID 679 //
8665        GIM_CheckFeatures, GIFBS_HasDPVFP_HasFPARMv8,
8666        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
8667        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
8668        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
8669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8670        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8671        // (intrinsic_wo_chain:{ *:[f64] } 1103:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
8672        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTND,
8673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
8674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8675        GIR_EraseFromParent, /*InsnID*/0,
8676        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8677        // GIR_Coverage, 679,
8678        GIR_Done,
8679      // Label 467: @20436
8680      GIM_Try, /*On fail goto*//*Label 468*/ 20482, // Rule ID 692 //
8681        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
8682        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr,
8683        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8684        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
8685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
8686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8687        // (intrinsic_wo_chain:{ *:[f32] } 1218:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
8688        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRD,
8689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
8690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8691        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8692        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8693        GIR_EraseFromParent, /*InsnID*/0,
8694        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8695        // GIR_Coverage, 692,
8696        GIR_Done,
8697      // Label 468: @20482
8698      GIM_Try, /*On fail goto*//*Label 469*/ 20528, // Rule ID 693 //
8699        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
8700        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtr,
8701        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8702        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
8704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
8705        // (intrinsic_wo_chain:{ *:[f32] } 1218:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
8706        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOSIRS,
8707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
8708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
8709        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8710        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8711        GIR_EraseFromParent, /*InsnID*/0,
8712        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8713        // GIR_Coverage, 693,
8714        GIR_Done,
8715      // Label 469: @20528
8716      GIM_Try, /*On fail goto*//*Label 470*/ 20574, // Rule ID 694 //
8717        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
8718        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru,
8719        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8720        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
8721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
8722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8723        // (intrinsic_wo_chain:{ *:[f32] } 1219:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm)  =>  (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
8724        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRD,
8725        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
8726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
8727        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8728        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8729        GIR_EraseFromParent, /*InsnID*/0,
8730        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8731        // GIR_Coverage, 694,
8732        GIR_Done,
8733      // Label 470: @20574
8734      GIM_Try, /*On fail goto*//*Label 471*/ 20620, // Rule ID 695 //
8735        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
8736        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_vcvtru,
8737        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
8738        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
8739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
8740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
8741        // (intrinsic_wo_chain:{ *:[f32] } 1219:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm)  =>  (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
8742        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTOUIRS,
8743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
8744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
8745        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8746        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8747        GIR_EraseFromParent, /*InsnID*/0,
8748        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8749        // GIR_Coverage, 695,
8750        GIR_Done,
8751      // Label 471: @20620
8752      GIM_Try, /*On fail goto*//*Label 472*/ 20666, // Rule ID 1213 //
8753        GIM_CheckFeatures, GIFBS_HasNEON,
8754        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
8755        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
8756        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
8757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8759        // (intrinsic_wo_chain:{ *:[v4i16] } 1067:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
8760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i8,
8761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8763        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8764        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8765        GIR_EraseFromParent, /*InsnID*/0,
8766        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8767        // GIR_Coverage, 1213,
8768        GIR_Done,
8769      // Label 472: @20666
8770      GIM_Try, /*On fail goto*//*Label 473*/ 20712, // Rule ID 1214 //
8771        GIM_CheckFeatures, GIFBS_HasNEON,
8772        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
8773        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
8774        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
8775        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8776        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8777        // (intrinsic_wo_chain:{ *:[v2i32] } 1067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
8778        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i16,
8779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8781        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8782        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8783        GIR_EraseFromParent, /*InsnID*/0,
8784        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8785        // GIR_Coverage, 1214,
8786        GIR_Done,
8787      // Label 473: @20712
8788      GIM_Try, /*On fail goto*//*Label 474*/ 20758, // Rule ID 1215 //
8789        GIM_CheckFeatures, GIFBS_HasNEON,
8790        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
8791        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
8792        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
8793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8795        // (intrinsic_wo_chain:{ *:[v1i64] } 1067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
8796        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv2i32,
8797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8799        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8800        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8801        GIR_EraseFromParent, /*InsnID*/0,
8802        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8803        // GIR_Coverage, 1215,
8804        GIR_Done,
8805      // Label 474: @20758
8806      GIM_Try, /*On fail goto*//*Label 475*/ 20804, // Rule ID 1216 //
8807        GIM_CheckFeatures, GIFBS_HasNEON,
8808        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
8809        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8810        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8813        // (intrinsic_wo_chain:{ *:[v8i16] } 1067:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
8814        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv16i8,
8815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8817        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8818        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8819        GIR_EraseFromParent, /*InsnID*/0,
8820        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8821        // GIR_Coverage, 1216,
8822        GIR_Done,
8823      // Label 475: @20804
8824      GIM_Try, /*On fail goto*//*Label 476*/ 20850, // Rule ID 1217 //
8825        GIM_CheckFeatures, GIFBS_HasNEON,
8826        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
8827        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8828        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8831        // (intrinsic_wo_chain:{ *:[v4i32] } 1067:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
8832        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv8i16,
8833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8835        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8836        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8837        GIR_EraseFromParent, /*InsnID*/0,
8838        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8839        // GIR_Coverage, 1217,
8840        GIR_Done,
8841      // Label 476: @20850
8842      GIM_Try, /*On fail goto*//*Label 477*/ 20896, // Rule ID 1218 //
8843        GIM_CheckFeatures, GIFBS_HasNEON,
8844        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddls,
8845        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8846        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8849        // (intrinsic_wo_chain:{ *:[v2i64] } 1067:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
8850        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLsv4i32,
8851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8853        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8854        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8855        GIR_EraseFromParent, /*InsnID*/0,
8856        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8857        // GIR_Coverage, 1218,
8858        GIR_Done,
8859      // Label 477: @20896
8860      GIM_Try, /*On fail goto*//*Label 478*/ 20942, // Rule ID 1219 //
8861        GIM_CheckFeatures, GIFBS_HasNEON,
8862        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
8863        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
8864        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
8865        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8867        // (intrinsic_wo_chain:{ *:[v4i16] } 1068:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
8868        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i8,
8869        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8871        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8872        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8873        GIR_EraseFromParent, /*InsnID*/0,
8874        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8875        // GIR_Coverage, 1219,
8876        GIR_Done,
8877      // Label 478: @20942
8878      GIM_Try, /*On fail goto*//*Label 479*/ 20988, // Rule ID 1220 //
8879        GIM_CheckFeatures, GIFBS_HasNEON,
8880        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
8881        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
8882        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
8883        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8885        // (intrinsic_wo_chain:{ *:[v2i32] } 1068:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
8886        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i16,
8887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8889        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8890        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8891        GIR_EraseFromParent, /*InsnID*/0,
8892        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8893        // GIR_Coverage, 1220,
8894        GIR_Done,
8895      // Label 479: @20988
8896      GIM_Try, /*On fail goto*//*Label 480*/ 21034, // Rule ID 1221 //
8897        GIM_CheckFeatures, GIFBS_HasNEON,
8898        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
8899        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
8900        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
8901        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8902        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8903        // (intrinsic_wo_chain:{ *:[v1i64] } 1068:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
8904        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv2i32,
8905        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8906        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8907        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8908        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8909        GIR_EraseFromParent, /*InsnID*/0,
8910        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8911        // GIR_Coverage, 1221,
8912        GIR_Done,
8913      // Label 480: @21034
8914      GIM_Try, /*On fail goto*//*Label 481*/ 21080, // Rule ID 1222 //
8915        GIM_CheckFeatures, GIFBS_HasNEON,
8916        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
8917        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
8918        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
8919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8920        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8921        // (intrinsic_wo_chain:{ *:[v8i16] } 1068:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
8922        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv16i8,
8923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8925        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8926        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8927        GIR_EraseFromParent, /*InsnID*/0,
8928        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8929        // GIR_Coverage, 1222,
8930        GIR_Done,
8931      // Label 481: @21080
8932      GIM_Try, /*On fail goto*//*Label 482*/ 21126, // Rule ID 1223 //
8933        GIM_CheckFeatures, GIFBS_HasNEON,
8934        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
8935        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8936        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
8937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8938        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8939        // (intrinsic_wo_chain:{ *:[v4i32] } 1068:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
8940        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv8i16,
8941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8943        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8944        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8945        GIR_EraseFromParent, /*InsnID*/0,
8946        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8947        // GIR_Coverage, 1223,
8948        GIR_Done,
8949      // Label 482: @21126
8950      GIM_Try, /*On fail goto*//*Label 483*/ 21172, // Rule ID 1224 //
8951        GIM_CheckFeatures, GIFBS_HasNEON,
8952        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpaddlu,
8953        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
8954        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8957        // (intrinsic_wo_chain:{ *:[v2i64] } 1068:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
8958        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDLuv4i32,
8959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8961        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8962        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8963        GIR_EraseFromParent, /*InsnID*/0,
8964        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8965        // GIR_Coverage, 1224,
8966        GIR_Done,
8967      // Label 483: @21172
8968      GIM_Try, /*On fail goto*//*Label 484*/ 21218, // Rule ID 1253 //
8969        GIM_CheckFeatures, GIFBS_HasNEON,
8970        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
8971        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
8972        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
8973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
8974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
8975        // (intrinsic_wo_chain:{ *:[v2i32] } 1097:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
8976        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEd,
8977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8979        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8980        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8981        GIR_EraseFromParent, /*InsnID*/0,
8982        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
8983        // GIR_Coverage, 1253,
8984        GIR_Done,
8985      // Label 484: @21218
8986      GIM_Try, /*On fail goto*//*Label 485*/ 21264, // Rule ID 1254 //
8987        GIM_CheckFeatures, GIFBS_HasNEON,
8988        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
8989        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
8990        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
8991        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
8992        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
8993        // (intrinsic_wo_chain:{ *:[v4i32] } 1097:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
8994        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEq,
8995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
8996        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
8997        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
8998        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
8999        GIR_EraseFromParent, /*InsnID*/0,
9000        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9001        // GIR_Coverage, 1254,
9002        GIR_Done,
9003      // Label 485: @21264
9004      GIM_Try, /*On fail goto*//*Label 486*/ 21310, // Rule ID 1255 //
9005        GIM_CheckFeatures, GIFBS_HasNEON,
9006        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
9007        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9008        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9011        // (intrinsic_wo_chain:{ *:[v2f32] } 1097:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
9012        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfd,
9013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9015        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9016        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9017        GIR_EraseFromParent, /*InsnID*/0,
9018        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9019        // GIR_Coverage, 1255,
9020        GIR_Done,
9021      // Label 486: @21310
9022      GIM_Try, /*On fail goto*//*Label 487*/ 21356, // Rule ID 1256 //
9023        GIM_CheckFeatures, GIFBS_HasNEON,
9024        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
9025        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9026        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9027        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9028        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9029        // (intrinsic_wo_chain:{ *:[v4f32] } 1097:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
9030        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEfq,
9031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9032        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9033        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9034        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9035        GIR_EraseFromParent, /*InsnID*/0,
9036        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9037        // GIR_Coverage, 1256,
9038        GIR_Done,
9039      // Label 487: @21356
9040      GIM_Try, /*On fail goto*//*Label 488*/ 21402, // Rule ID 1257 //
9041        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
9042        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
9043        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9044        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9047        // (intrinsic_wo_chain:{ *:[v4f16] } 1097:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
9048        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhd,
9049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9051        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9052        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9053        GIR_EraseFromParent, /*InsnID*/0,
9054        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9055        // GIR_Coverage, 1257,
9056        GIR_Done,
9057      // Label 488: @21402
9058      GIM_Try, /*On fail goto*//*Label 489*/ 21448, // Rule ID 1258 //
9059        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
9060        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecpe,
9061        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9062        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9065        // (intrinsic_wo_chain:{ *:[v8f16] } 1097:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
9066        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPEhq,
9067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9069        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9070        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9071        GIR_EraseFromParent, /*InsnID*/0,
9072        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9073        // GIR_Coverage, 1258,
9074        GIR_Done,
9075      // Label 489: @21448
9076      GIM_Try, /*On fail goto*//*Label 490*/ 21494, // Rule ID 1263 //
9077        GIM_CheckFeatures, GIFBS_HasNEON,
9078        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
9079        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9080        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9083        // (intrinsic_wo_chain:{ *:[v2i32] } 1110:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
9084        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEd,
9085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9087        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9088        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9089        GIR_EraseFromParent, /*InsnID*/0,
9090        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9091        // GIR_Coverage, 1263,
9092        GIR_Done,
9093      // Label 490: @21494
9094      GIM_Try, /*On fail goto*//*Label 491*/ 21540, // Rule ID 1264 //
9095        GIM_CheckFeatures, GIFBS_HasNEON,
9096        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
9097        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9098        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9099        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9101        // (intrinsic_wo_chain:{ *:[v4i32] } 1110:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
9102        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEq,
9103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9105        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9106        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9107        GIR_EraseFromParent, /*InsnID*/0,
9108        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9109        // GIR_Coverage, 1264,
9110        GIR_Done,
9111      // Label 491: @21540
9112      GIM_Try, /*On fail goto*//*Label 492*/ 21586, // Rule ID 1265 //
9113        GIM_CheckFeatures, GIFBS_HasNEON,
9114        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
9115        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9116        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9117        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9118        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9119        // (intrinsic_wo_chain:{ *:[v2f32] } 1110:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
9120        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfd,
9121        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9122        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9123        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9124        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9125        GIR_EraseFromParent, /*InsnID*/0,
9126        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9127        // GIR_Coverage, 1265,
9128        GIR_Done,
9129      // Label 492: @21586
9130      GIM_Try, /*On fail goto*//*Label 493*/ 21632, // Rule ID 1266 //
9131        GIM_CheckFeatures, GIFBS_HasNEON,
9132        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
9133        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9134        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9135        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9136        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9137        // (intrinsic_wo_chain:{ *:[v4f32] } 1110:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
9138        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEfq,
9139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9141        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9142        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9143        GIR_EraseFromParent, /*InsnID*/0,
9144        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9145        // GIR_Coverage, 1266,
9146        GIR_Done,
9147      // Label 493: @21632
9148      GIM_Try, /*On fail goto*//*Label 494*/ 21678, // Rule ID 1267 //
9149        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
9150        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
9151        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9152        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9154        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9155        // (intrinsic_wo_chain:{ *:[v4f16] } 1110:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
9156        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhd,
9157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9159        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9160        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9161        GIR_EraseFromParent, /*InsnID*/0,
9162        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9163        // GIR_Coverage, 1267,
9164        GIR_Done,
9165      // Label 494: @21678
9166      GIM_Try, /*On fail goto*//*Label 495*/ 21724, // Rule ID 1268 //
9167        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
9168        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrte,
9169        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9170        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9173        // (intrinsic_wo_chain:{ *:[v8f16] } 1110:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
9174        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTEhq,
9175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9177        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9178        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9179        GIR_EraseFromParent, /*InsnID*/0,
9180        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9181        // GIR_Coverage, 1268,
9182        GIR_Done,
9183      // Label 495: @21724
9184      GIM_Try, /*On fail goto*//*Label 496*/ 21770, // Rule ID 1489 //
9185        GIM_CheckFeatures, GIFBS_HasNEON,
9186        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
9187        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
9188        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
9189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9191        // (intrinsic_wo_chain:{ *:[v8i8] } 1073:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
9192        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i8,
9193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9195        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9196        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9197        GIR_EraseFromParent, /*InsnID*/0,
9198        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9199        // GIR_Coverage, 1489,
9200        GIR_Done,
9201      // Label 496: @21770
9202      GIM_Try, /*On fail goto*//*Label 497*/ 21816, // Rule ID 1490 //
9203        GIM_CheckFeatures, GIFBS_HasNEON,
9204        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
9205        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9206        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9209        // (intrinsic_wo_chain:{ *:[v4i16] } 1073:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
9210        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i16,
9211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9213        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9214        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9215        GIR_EraseFromParent, /*InsnID*/0,
9216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9217        // GIR_Coverage, 1490,
9218        GIR_Done,
9219      // Label 497: @21816
9220      GIM_Try, /*On fail goto*//*Label 498*/ 21862, // Rule ID 1491 //
9221        GIM_CheckFeatures, GIFBS_HasNEON,
9222        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
9223        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9224        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9227        // (intrinsic_wo_chain:{ *:[v2i32] } 1073:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
9228        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv2i32,
9229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9231        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9232        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9233        GIR_EraseFromParent, /*InsnID*/0,
9234        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9235        // GIR_Coverage, 1491,
9236        GIR_Done,
9237      // Label 498: @21862
9238      GIM_Try, /*On fail goto*//*Label 499*/ 21908, // Rule ID 1492 //
9239        GIM_CheckFeatures, GIFBS_HasNEON,
9240        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
9241        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9242        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9243        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9244        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9245        // (intrinsic_wo_chain:{ *:[v16i8] } 1073:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
9246        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv16i8,
9247        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9248        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9249        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9250        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9251        GIR_EraseFromParent, /*InsnID*/0,
9252        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9253        // GIR_Coverage, 1492,
9254        GIR_Done,
9255      // Label 499: @21908
9256      GIM_Try, /*On fail goto*//*Label 500*/ 21954, // Rule ID 1493 //
9257        GIM_CheckFeatures, GIFBS_HasNEON,
9258        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
9259        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9260        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9263        // (intrinsic_wo_chain:{ *:[v8i16] } 1073:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
9264        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv8i16,
9265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9267        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9268        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9269        GIR_EraseFromParent, /*InsnID*/0,
9270        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9271        // GIR_Coverage, 1493,
9272        GIR_Done,
9273      // Label 500: @21954
9274      GIM_Try, /*On fail goto*//*Label 501*/ 22000, // Rule ID 1494 //
9275        GIM_CheckFeatures, GIFBS_HasNEON,
9276        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqabs,
9277        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9278        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9279        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9280        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9281        // (intrinsic_wo_chain:{ *:[v4i32] } 1073:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
9282        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQABSv4i32,
9283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9284        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9285        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9286        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9287        GIR_EraseFromParent, /*InsnID*/0,
9288        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9289        // GIR_Coverage, 1494,
9290        GIR_Done,
9291      // Label 501: @22000
9292      GIM_Try, /*On fail goto*//*Label 502*/ 22046, // Rule ID 1505 //
9293        GIM_CheckFeatures, GIFBS_HasNEON,
9294        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
9295        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
9296        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
9297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9299        // (intrinsic_wo_chain:{ *:[v8i8] } 1081:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
9300        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i8,
9301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9303        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9304        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9305        GIR_EraseFromParent, /*InsnID*/0,
9306        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9307        // GIR_Coverage, 1505,
9308        GIR_Done,
9309      // Label 502: @22046
9310      GIM_Try, /*On fail goto*//*Label 503*/ 22092, // Rule ID 1506 //
9311        GIM_CheckFeatures, GIFBS_HasNEON,
9312        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
9313        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9314        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9317        // (intrinsic_wo_chain:{ *:[v4i16] } 1081:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
9318        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i16,
9319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9321        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9322        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9323        GIR_EraseFromParent, /*InsnID*/0,
9324        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9325        // GIR_Coverage, 1506,
9326        GIR_Done,
9327      // Label 503: @22092
9328      GIM_Try, /*On fail goto*//*Label 504*/ 22138, // Rule ID 1507 //
9329        GIM_CheckFeatures, GIFBS_HasNEON,
9330        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
9331        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9332        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9335        // (intrinsic_wo_chain:{ *:[v2i32] } 1081:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
9336        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv2i32,
9337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9339        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9340        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9341        GIR_EraseFromParent, /*InsnID*/0,
9342        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9343        // GIR_Coverage, 1507,
9344        GIR_Done,
9345      // Label 504: @22138
9346      GIM_Try, /*On fail goto*//*Label 505*/ 22184, // Rule ID 1508 //
9347        GIM_CheckFeatures, GIFBS_HasNEON,
9348        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
9349        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9350        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9353        // (intrinsic_wo_chain:{ *:[v16i8] } 1081:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
9354        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv16i8,
9355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9357        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9358        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9359        GIR_EraseFromParent, /*InsnID*/0,
9360        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9361        // GIR_Coverage, 1508,
9362        GIR_Done,
9363      // Label 505: @22184
9364      GIM_Try, /*On fail goto*//*Label 506*/ 22230, // Rule ID 1509 //
9365        GIM_CheckFeatures, GIFBS_HasNEON,
9366        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
9367        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9368        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9369        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9370        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9371        // (intrinsic_wo_chain:{ *:[v8i16] } 1081:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
9372        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv8i16,
9373        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9374        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9375        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9376        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9377        GIR_EraseFromParent, /*InsnID*/0,
9378        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9379        // GIR_Coverage, 1509,
9380        GIR_Done,
9381      // Label 506: @22230
9382      GIM_Try, /*On fail goto*//*Label 507*/ 22276, // Rule ID 1510 //
9383        GIM_CheckFeatures, GIFBS_HasNEON,
9384        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqneg,
9385        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9386        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9389        // (intrinsic_wo_chain:{ *:[v4i32] } 1081:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
9390        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQNEGv4i32,
9391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9393        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9394        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9395        GIR_EraseFromParent, /*InsnID*/0,
9396        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9397        // GIR_Coverage, 1510,
9398        GIR_Done,
9399      // Label 507: @22276
9400      GIM_Try, /*On fail goto*//*Label 508*/ 22322, // Rule ID 1511 //
9401        GIM_CheckFeatures, GIFBS_HasNEON,
9402        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
9403        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
9404        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
9405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9407        // (intrinsic_wo_chain:{ *:[v8i8] } 1022:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm)  =>  (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
9408        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i8,
9409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9411        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9412        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9413        GIR_EraseFromParent, /*InsnID*/0,
9414        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9415        // GIR_Coverage, 1511,
9416        GIR_Done,
9417      // Label 508: @22322
9418      GIM_Try, /*On fail goto*//*Label 509*/ 22368, // Rule ID 1512 //
9419        GIM_CheckFeatures, GIFBS_HasNEON,
9420        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
9421        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9422        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9425        // (intrinsic_wo_chain:{ *:[v4i16] } 1022:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
9426        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i16,
9427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9429        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9430        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9431        GIR_EraseFromParent, /*InsnID*/0,
9432        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9433        // GIR_Coverage, 1512,
9434        GIR_Done,
9435      // Label 509: @22368
9436      GIM_Try, /*On fail goto*//*Label 510*/ 22414, // Rule ID 1513 //
9437        GIM_CheckFeatures, GIFBS_HasNEON,
9438        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
9439        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9440        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9441        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9443        // (intrinsic_wo_chain:{ *:[v2i32] } 1022:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm)  =>  (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
9444        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv2i32,
9445        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9447        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9448        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9449        GIR_EraseFromParent, /*InsnID*/0,
9450        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9451        // GIR_Coverage, 1513,
9452        GIR_Done,
9453      // Label 510: @22414
9454      GIM_Try, /*On fail goto*//*Label 511*/ 22460, // Rule ID 1514 //
9455        GIM_CheckFeatures, GIFBS_HasNEON,
9456        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
9457        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
9458        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
9459        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9461        // (intrinsic_wo_chain:{ *:[v16i8] } 1022:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
9462        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv16i8,
9463        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9464        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9465        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9466        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9467        GIR_EraseFromParent, /*InsnID*/0,
9468        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9469        // GIR_Coverage, 1514,
9470        GIR_Done,
9471      // Label 511: @22460
9472      GIM_Try, /*On fail goto*//*Label 512*/ 22506, // Rule ID 1515 //
9473        GIM_CheckFeatures, GIFBS_HasNEON,
9474        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
9475        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9476        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9479        // (intrinsic_wo_chain:{ *:[v8i16] } 1022:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
9480        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv8i16,
9481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9483        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9484        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9485        GIR_EraseFromParent, /*InsnID*/0,
9486        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9487        // GIR_Coverage, 1515,
9488        GIR_Done,
9489      // Label 512: @22506
9490      GIM_Try, /*On fail goto*//*Label 513*/ 22552, // Rule ID 1516 //
9491        GIM_CheckFeatures, GIFBS_HasNEON,
9492        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcls,
9493        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9494        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9495        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9497        // (intrinsic_wo_chain:{ *:[v4i32] } 1022:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
9498        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCLSv4i32,
9499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9501        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9502        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9503        GIR_EraseFromParent, /*InsnID*/0,
9504        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9505        // GIR_Coverage, 1516,
9506        GIR_Done,
9507      // Label 513: @22552
9508      GIM_Try, /*On fail goto*//*Label 514*/ 22598, // Rule ID 1560 //
9509        GIM_CheckFeatures, GIFBS_HasNEON,
9510        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
9511        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
9512        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9515        // (intrinsic_wo_chain:{ *:[v8i8] } 1078:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
9516        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv8i8,
9517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9519        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9520        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9521        GIR_EraseFromParent, /*InsnID*/0,
9522        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9523        // GIR_Coverage, 1560,
9524        GIR_Done,
9525      // Label 514: @22598
9526      GIM_Try, /*On fail goto*//*Label 515*/ 22644, // Rule ID 1561 //
9527        GIM_CheckFeatures, GIFBS_HasNEON,
9528        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
9529        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9530        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9531        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9533        // (intrinsic_wo_chain:{ *:[v4i16] } 1078:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
9534        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv4i16,
9535        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9536        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9537        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9538        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9539        GIR_EraseFromParent, /*InsnID*/0,
9540        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9541        // GIR_Coverage, 1561,
9542        GIR_Done,
9543      // Label 515: @22644
9544      GIM_Try, /*On fail goto*//*Label 516*/ 22690, // Rule ID 1562 //
9545        GIM_CheckFeatures, GIFBS_HasNEON,
9546        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovns,
9547        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9548        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9550        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9551        // (intrinsic_wo_chain:{ *:[v2i32] } 1078:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
9552        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsv2i32,
9553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9555        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9556        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9557        GIR_EraseFromParent, /*InsnID*/0,
9558        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9559        // GIR_Coverage, 1562,
9560        GIR_Done,
9561      // Label 516: @22690
9562      GIM_Try, /*On fail goto*//*Label 517*/ 22736, // Rule ID 1563 //
9563        GIM_CheckFeatures, GIFBS_HasNEON,
9564        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
9565        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
9566        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9569        // (intrinsic_wo_chain:{ *:[v8i8] } 1080:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
9570        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv8i8,
9571        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9573        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9574        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9575        GIR_EraseFromParent, /*InsnID*/0,
9576        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9577        // GIR_Coverage, 1563,
9578        GIR_Done,
9579      // Label 517: @22736
9580      GIM_Try, /*On fail goto*//*Label 518*/ 22782, // Rule ID 1564 //
9581        GIM_CheckFeatures, GIFBS_HasNEON,
9582        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
9583        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9584        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9585        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9587        // (intrinsic_wo_chain:{ *:[v4i16] } 1080:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
9588        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv4i16,
9589        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9590        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9591        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9592        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9593        GIR_EraseFromParent, /*InsnID*/0,
9594        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9595        // GIR_Coverage, 1564,
9596        GIR_Done,
9597      // Label 518: @22782
9598      GIM_Try, /*On fail goto*//*Label 519*/ 22828, // Rule ID 1565 //
9599        GIM_CheckFeatures, GIFBS_HasNEON,
9600        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnu,
9601        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9602        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9603        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9604        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9605        // (intrinsic_wo_chain:{ *:[v2i32] } 1080:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
9606        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNuv2i32,
9607        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9609        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9610        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9611        GIR_EraseFromParent, /*InsnID*/0,
9612        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9613        // GIR_Coverage, 1565,
9614        GIR_Done,
9615      // Label 519: @22828
9616      GIM_Try, /*On fail goto*//*Label 520*/ 22874, // Rule ID 1566 //
9617        GIM_CheckFeatures, GIFBS_HasNEON,
9618        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
9619        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
9620        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9621        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9623        // (intrinsic_wo_chain:{ *:[v8i8] } 1079:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm)  =>  (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
9624        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv8i8,
9625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9627        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9628        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9629        GIR_EraseFromParent, /*InsnID*/0,
9630        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9631        // GIR_Coverage, 1566,
9632        GIR_Done,
9633      // Label 520: @22874
9634      GIM_Try, /*On fail goto*//*Label 521*/ 22920, // Rule ID 1567 //
9635        GIM_CheckFeatures, GIFBS_HasNEON,
9636        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
9637        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9638        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9641        // (intrinsic_wo_chain:{ *:[v4i16] } 1079:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm)  =>  (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
9642        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv4i16,
9643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9645        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9646        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9647        GIR_EraseFromParent, /*InsnID*/0,
9648        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9649        // GIR_Coverage, 1567,
9650        GIR_Done,
9651      // Label 521: @22920
9652      GIM_Try, /*On fail goto*//*Label 522*/ 22966, // Rule ID 1568 //
9653        GIM_CheckFeatures, GIFBS_HasNEON,
9654        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqmovnsu,
9655        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9656        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
9657        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9659        // (intrinsic_wo_chain:{ *:[v2i32] } 1079:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm)  =>  (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
9660        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQMOVNsuv2i32,
9661        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9663        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
9664        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
9665        GIR_EraseFromParent, /*InsnID*/0,
9666        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9667        // GIR_Coverage, 1568,
9668        GIR_Done,
9669      // Label 522: @22966
9670      GIM_Try, /*On fail goto*//*Label 523*/ 23006, // Rule ID 1591 //
9671        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9672        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
9673        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9674        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9675        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9676        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9677        // (intrinsic_wo_chain:{ *:[v2i32] } 1023:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
9678        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDf,
9679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9680        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9681        GIR_EraseFromParent, /*InsnID*/0,
9682        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9683        // GIR_Coverage, 1591,
9684        GIR_Done,
9685      // Label 523: @23006
9686      GIM_Try, /*On fail goto*//*Label 524*/ 23046, // Rule ID 1592 //
9687        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9688        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
9689        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9690        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9691        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9692        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9693        // (intrinsic_wo_chain:{ *:[v4i32] } 1023:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
9694        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQf,
9695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9696        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9697        GIR_EraseFromParent, /*InsnID*/0,
9698        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9699        // GIR_Coverage, 1592,
9700        GIR_Done,
9701      // Label 524: @23046
9702      GIM_Try, /*On fail goto*//*Label 525*/ 23086, // Rule ID 1593 //
9703        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9704        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
9705        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9706        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9709        // (intrinsic_wo_chain:{ *:[v2i32] } 1024:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
9710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDf,
9711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9713        GIR_EraseFromParent, /*InsnID*/0,
9714        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9715        // GIR_Coverage, 1593,
9716        GIR_Done,
9717      // Label 525: @23086
9718      GIM_Try, /*On fail goto*//*Label 526*/ 23126, // Rule ID 1594 //
9719        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9720        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
9721        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9722        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9725        // (intrinsic_wo_chain:{ *:[v4i32] } 1024:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
9726        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQf,
9727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9729        GIR_EraseFromParent, /*InsnID*/0,
9730        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9731        // GIR_Coverage, 1594,
9732        GIR_Done,
9733      // Label 526: @23126
9734      GIM_Try, /*On fail goto*//*Label 527*/ 23166, // Rule ID 1595 //
9735        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
9736        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
9737        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9738        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9739        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9740        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9741        // (intrinsic_wo_chain:{ *:[v4i16] } 1023:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
9742        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSDh,
9743        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9744        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9745        GIR_EraseFromParent, /*InsnID*/0,
9746        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9747        // GIR_Coverage, 1595,
9748        GIR_Done,
9749      // Label 527: @23166
9750      GIM_Try, /*On fail goto*//*Label 528*/ 23206, // Rule ID 1596 //
9751        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
9752        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtas,
9753        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9754        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9757        // (intrinsic_wo_chain:{ *:[v8i16] } 1023:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
9758        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANSQh,
9759        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9761        GIR_EraseFromParent, /*InsnID*/0,
9762        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9763        // GIR_Coverage, 1596,
9764        GIR_Done,
9765      // Label 528: @23206
9766      GIM_Try, /*On fail goto*//*Label 529*/ 23246, // Rule ID 1597 //
9767        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
9768        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
9769        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9770        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9773        // (intrinsic_wo_chain:{ *:[v4i16] } 1024:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
9774        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUDh,
9775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9777        GIR_EraseFromParent, /*InsnID*/0,
9778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9779        // GIR_Coverage, 1597,
9780        GIR_Done,
9781      // Label 529: @23246
9782      GIM_Try, /*On fail goto*//*Label 530*/ 23286, // Rule ID 1598 //
9783        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
9784        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtau,
9785        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9786        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9789        // (intrinsic_wo_chain:{ *:[v8i16] } 1024:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
9790        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTANUQh,
9791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9793        GIR_EraseFromParent, /*InsnID*/0,
9794        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9795        // GIR_Coverage, 1598,
9796        GIR_Done,
9797      // Label 530: @23286
9798      GIM_Try, /*On fail goto*//*Label 531*/ 23326, // Rule ID 1599 //
9799        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9800        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
9801        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9802        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9804        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9805        // (intrinsic_wo_chain:{ *:[v2i32] } 1033:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
9806        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDf,
9807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9809        GIR_EraseFromParent, /*InsnID*/0,
9810        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9811        // GIR_Coverage, 1599,
9812        GIR_Done,
9813      // Label 531: @23326
9814      GIM_Try, /*On fail goto*//*Label 532*/ 23366, // Rule ID 1600 //
9815        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9816        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
9817        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9818        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9821        // (intrinsic_wo_chain:{ *:[v4i32] } 1033:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
9822        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQf,
9823        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9825        GIR_EraseFromParent, /*InsnID*/0,
9826        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9827        // GIR_Coverage, 1600,
9828        GIR_Done,
9829      // Label 532: @23366
9830      GIM_Try, /*On fail goto*//*Label 533*/ 23406, // Rule ID 1601 //
9831        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9832        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
9833        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9834        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9836        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9837        // (intrinsic_wo_chain:{ *:[v2i32] } 1034:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
9838        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDf,
9839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9841        GIR_EraseFromParent, /*InsnID*/0,
9842        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9843        // GIR_Coverage, 1601,
9844        GIR_Done,
9845      // Label 533: @23406
9846      GIM_Try, /*On fail goto*//*Label 534*/ 23446, // Rule ID 1602 //
9847        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9848        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
9849        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9850        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9851        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9853        // (intrinsic_wo_chain:{ *:[v4i32] } 1034:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
9854        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQf,
9855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9857        GIR_EraseFromParent, /*InsnID*/0,
9858        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9859        // GIR_Coverage, 1602,
9860        GIR_Done,
9861      // Label 534: @23446
9862      GIM_Try, /*On fail goto*//*Label 535*/ 23486, // Rule ID 1603 //
9863        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
9864        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
9865        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9866        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9869        // (intrinsic_wo_chain:{ *:[v4i16] } 1033:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
9870        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSDh,
9871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9873        GIR_EraseFromParent, /*InsnID*/0,
9874        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9875        // GIR_Coverage, 1603,
9876        GIR_Done,
9877      // Label 535: @23486
9878      GIM_Try, /*On fail goto*//*Label 536*/ 23526, // Rule ID 1604 //
9879        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
9880        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtns,
9881        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9882        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9883        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9885        // (intrinsic_wo_chain:{ *:[v8i16] } 1033:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
9886        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNSQh,
9887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9889        GIR_EraseFromParent, /*InsnID*/0,
9890        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9891        // GIR_Coverage, 1604,
9892        GIR_Done,
9893      // Label 536: @23526
9894      GIM_Try, /*On fail goto*//*Label 537*/ 23566, // Rule ID 1605 //
9895        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
9896        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
9897        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9898        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9899        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9900        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9901        // (intrinsic_wo_chain:{ *:[v4i16] } 1034:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
9902        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUDh,
9903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9904        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9905        GIR_EraseFromParent, /*InsnID*/0,
9906        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9907        // GIR_Coverage, 1605,
9908        GIR_Done,
9909      // Label 537: @23566
9910      GIM_Try, /*On fail goto*//*Label 538*/ 23606, // Rule ID 1606 //
9911        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
9912        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtnu,
9913        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
9914        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
9915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9917        // (intrinsic_wo_chain:{ *:[v8i16] } 1034:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
9918        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTNNUQh,
9919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9921        GIR_EraseFromParent, /*InsnID*/0,
9922        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9923        // GIR_Coverage, 1606,
9924        GIR_Done,
9925      // Label 538: @23606
9926      GIM_Try, /*On fail goto*//*Label 539*/ 23646, // Rule ID 1607 //
9927        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9928        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
9929        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9930        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9933        // (intrinsic_wo_chain:{ *:[v2i32] } 1035:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
9934        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDf,
9935        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9937        GIR_EraseFromParent, /*InsnID*/0,
9938        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9939        // GIR_Coverage, 1607,
9940        GIR_Done,
9941      // Label 539: @23646
9942      GIM_Try, /*On fail goto*//*Label 540*/ 23686, // Rule ID 1608 //
9943        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9944        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
9945        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9946        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9948        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9949        // (intrinsic_wo_chain:{ *:[v4i32] } 1035:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
9950        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQf,
9951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9953        GIR_EraseFromParent, /*InsnID*/0,
9954        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9955        // GIR_Coverage, 1608,
9956        GIR_Done,
9957      // Label 540: @23686
9958      GIM_Try, /*On fail goto*//*Label 541*/ 23726, // Rule ID 1609 //
9959        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9960        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
9961        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
9962        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
9963        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9965        // (intrinsic_wo_chain:{ *:[v2i32] } 1036:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
9966        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDf,
9967        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9969        GIR_EraseFromParent, /*InsnID*/0,
9970        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9971        // GIR_Coverage, 1609,
9972        GIR_Done,
9973      // Label 541: @23726
9974      GIM_Try, /*On fail goto*//*Label 542*/ 23766, // Rule ID 1610 //
9975        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
9976        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
9977        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
9978        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
9979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
9980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
9981        // (intrinsic_wo_chain:{ *:[v4i32] } 1036:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
9982        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQf,
9983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
9984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
9985        GIR_EraseFromParent, /*InsnID*/0,
9986        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
9987        // GIR_Coverage, 1610,
9988        GIR_Done,
9989      // Label 542: @23766
9990      GIM_Try, /*On fail goto*//*Label 543*/ 23806, // Rule ID 1611 //
9991        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
9992        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
9993        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
9994        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
9995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
9996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
9997        // (intrinsic_wo_chain:{ *:[v4i16] } 1035:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
9998        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSDh,
9999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10001        GIR_EraseFromParent, /*InsnID*/0,
10002        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10003        // GIR_Coverage, 1611,
10004        GIR_Done,
10005      // Label 543: @23806
10006      GIM_Try, /*On fail goto*//*Label 544*/ 23846, // Rule ID 1612 //
10007        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10008        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtps,
10009        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10010        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10013        // (intrinsic_wo_chain:{ *:[v8i16] } 1035:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
10014        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNSQh,
10015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10017        GIR_EraseFromParent, /*InsnID*/0,
10018        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10019        // GIR_Coverage, 1612,
10020        GIR_Done,
10021      // Label 544: @23846
10022      GIM_Try, /*On fail goto*//*Label 545*/ 23886, // Rule ID 1613 //
10023        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10024        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
10025        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10026        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10027        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10028        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10029        // (intrinsic_wo_chain:{ *:[v4i16] } 1036:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
10030        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUDh,
10031        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10032        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10033        GIR_EraseFromParent, /*InsnID*/0,
10034        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10035        // GIR_Coverage, 1613,
10036        GIR_Done,
10037      // Label 545: @23886
10038      GIM_Try, /*On fail goto*//*Label 546*/ 23926, // Rule ID 1614 //
10039        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10040        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtpu,
10041        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10042        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10045        // (intrinsic_wo_chain:{ *:[v8i16] } 1036:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
10046        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTPNUQh,
10047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10049        GIR_EraseFromParent, /*InsnID*/0,
10050        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10051        // GIR_Coverage, 1614,
10052        GIR_Done,
10053      // Label 546: @23926
10054      GIM_Try, /*On fail goto*//*Label 547*/ 23966, // Rule ID 1615 //
10055        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10056        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
10057        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10058        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10061        // (intrinsic_wo_chain:{ *:[v2i32] } 1031:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
10062        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDf,
10063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10065        GIR_EraseFromParent, /*InsnID*/0,
10066        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10067        // GIR_Coverage, 1615,
10068        GIR_Done,
10069      // Label 547: @23966
10070      GIM_Try, /*On fail goto*//*Label 548*/ 24006, // Rule ID 1616 //
10071        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10072        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
10073        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10074        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10077        // (intrinsic_wo_chain:{ *:[v4i32] } 1031:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
10078        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQf,
10079        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10081        GIR_EraseFromParent, /*InsnID*/0,
10082        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10083        // GIR_Coverage, 1616,
10084        GIR_Done,
10085      // Label 548: @24006
10086      GIM_Try, /*On fail goto*//*Label 549*/ 24046, // Rule ID 1617 //
10087        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10088        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
10089        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10090        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10091        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10093        // (intrinsic_wo_chain:{ *:[v2i32] } 1032:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
10094        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDf,
10095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10097        GIR_EraseFromParent, /*InsnID*/0,
10098        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10099        // GIR_Coverage, 1617,
10100        GIR_Done,
10101      // Label 549: @24046
10102      GIM_Try, /*On fail goto*//*Label 550*/ 24086, // Rule ID 1618 //
10103        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10104        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
10105        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10106        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10109        // (intrinsic_wo_chain:{ *:[v4i32] } 1032:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
10110        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQf,
10111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10113        GIR_EraseFromParent, /*InsnID*/0,
10114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10115        // GIR_Coverage, 1618,
10116        GIR_Done,
10117      // Label 550: @24086
10118      GIM_Try, /*On fail goto*//*Label 551*/ 24126, // Rule ID 1619 //
10119        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10120        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
10121        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10122        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10125        // (intrinsic_wo_chain:{ *:[v4i16] } 1031:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
10126        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSDh,
10127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10129        GIR_EraseFromParent, /*InsnID*/0,
10130        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10131        // GIR_Coverage, 1619,
10132        GIR_Done,
10133      // Label 551: @24126
10134      GIM_Try, /*On fail goto*//*Label 552*/ 24166, // Rule ID 1620 //
10135        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10136        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtms,
10137        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10138        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10139        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10140        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10141        // (intrinsic_wo_chain:{ *:[v8i16] } 1031:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
10142        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNSQh,
10143        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10144        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10145        GIR_EraseFromParent, /*InsnID*/0,
10146        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10147        // GIR_Coverage, 1620,
10148        GIR_Done,
10149      // Label 552: @24166
10150      GIM_Try, /*On fail goto*//*Label 553*/ 24206, // Rule ID 1621 //
10151        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10152        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
10153        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10154        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10157        // (intrinsic_wo_chain:{ *:[v4i16] } 1032:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
10158        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUDh,
10159        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10161        GIR_EraseFromParent, /*InsnID*/0,
10162        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10163        // GIR_Coverage, 1621,
10164        GIR_Done,
10165      // Label 553: @24206
10166      GIM_Try, /*On fail goto*//*Label 554*/ 24246, // Rule ID 1622 //
10167        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10168        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtmu,
10169        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10170        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10173        // (intrinsic_wo_chain:{ *:[v8i16] } 1032:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
10174        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTMNUQh,
10175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10177        GIR_EraseFromParent, /*InsnID*/0,
10178        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10179        // GIR_Coverage, 1622,
10180        GIR_Done,
10181      // Label 554: @24246
10182      GIM_Try, /*On fail goto*//*Label 555*/ 24292, // Rule ID 1639 //
10183        GIM_CheckFeatures, GIFBS_HasFP16_HasNEON,
10184        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2hf,
10185        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10186        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10189        // (intrinsic_wo_chain:{ *:[v4i16] } 1027:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm)
10190        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2h,
10191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10193        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10194        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10195        GIR_EraseFromParent, /*InsnID*/0,
10196        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10197        // GIR_Coverage, 1639,
10198        GIR_Done,
10199      // Label 555: @24292
10200      GIM_Try, /*On fail goto*//*Label 556*/ 24338, // Rule ID 1640 //
10201        GIM_CheckFeatures, GIFBS_HasFP16_HasNEON,
10202        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvthf2fp,
10203        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10204        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10207        // (intrinsic_wo_chain:{ *:[v4f32] } 1030:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm)
10208        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2f,
10209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10211        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10212        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10213        GIR_EraseFromParent, /*InsnID*/0,
10214        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10215        // GIR_Coverage, 1640,
10216        GIR_Done,
10217      // Label 556: @24338
10218      GIM_Try, /*On fail goto*//*Label 557*/ 24378, // Rule ID 1662 //
10219        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10220        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
10221        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10222        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10223        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10224        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10225        // (intrinsic_wo_chain:{ *:[v2f32] } 1103:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
10226        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDf,
10227        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10228        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10229        GIR_EraseFromParent, /*InsnID*/0,
10230        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10231        // GIR_Coverage, 1662,
10232        GIR_Done,
10233      // Label 557: @24378
10234      GIM_Try, /*On fail goto*//*Label 558*/ 24418, // Rule ID 1663 //
10235        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10236        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
10237        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10238        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10241        // (intrinsic_wo_chain:{ *:[v4f32] } 1103:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
10242        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQf,
10243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10245        GIR_EraseFromParent, /*InsnID*/0,
10246        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10247        // GIR_Coverage, 1663,
10248        GIR_Done,
10249      // Label 558: @24418
10250      GIM_Try, /*On fail goto*//*Label 559*/ 24458, // Rule ID 1664 //
10251        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10252        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
10253        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10254        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10257        // (intrinsic_wo_chain:{ *:[v4f16] } 1103:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
10258        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNDh,
10259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10261        GIR_EraseFromParent, /*InsnID*/0,
10262        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10263        // GIR_Coverage, 1664,
10264        GIR_Done,
10265      // Label 559: @24458
10266      GIM_Try, /*On fail goto*//*Label 560*/ 24498, // Rule ID 1665 //
10267        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10268        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintn,
10269        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10270        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10272        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10273        // (intrinsic_wo_chain:{ *:[v8f16] } 1103:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
10274        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTNNQh,
10275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10277        GIR_EraseFromParent, /*InsnID*/0,
10278        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10279        // GIR_Coverage, 1665,
10280        GIR_Done,
10281      // Label 560: @24498
10282      GIM_Try, /*On fail goto*//*Label 561*/ 24538, // Rule ID 1666 //
10283        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10284        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
10285        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10286        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10287        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10289        // (intrinsic_wo_chain:{ *:[v2f32] } 1105:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
10290        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDf,
10291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10292        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10293        GIR_EraseFromParent, /*InsnID*/0,
10294        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10295        // GIR_Coverage, 1666,
10296        GIR_Done,
10297      // Label 561: @24538
10298      GIM_Try, /*On fail goto*//*Label 562*/ 24578, // Rule ID 1667 //
10299        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10300        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
10301        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10302        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10305        // (intrinsic_wo_chain:{ *:[v4f32] } 1105:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
10306        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQf,
10307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10309        GIR_EraseFromParent, /*InsnID*/0,
10310        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10311        // GIR_Coverage, 1667,
10312        GIR_Done,
10313      // Label 562: @24578
10314      GIM_Try, /*On fail goto*//*Label 563*/ 24618, // Rule ID 1668 //
10315        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10316        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
10317        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10318        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10320        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10321        // (intrinsic_wo_chain:{ *:[v4f16] } 1105:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
10322        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNDh,
10323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10325        GIR_EraseFromParent, /*InsnID*/0,
10326        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10327        // GIR_Coverage, 1668,
10328        GIR_Done,
10329      // Label 563: @24618
10330      GIM_Try, /*On fail goto*//*Label 564*/ 24658, // Rule ID 1669 //
10331        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10332        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintx,
10333        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10334        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10337        // (intrinsic_wo_chain:{ *:[v8f16] } 1105:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
10338        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTXNQh,
10339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10341        GIR_EraseFromParent, /*InsnID*/0,
10342        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10343        // GIR_Coverage, 1669,
10344        GIR_Done,
10345      // Label 564: @24658
10346      GIM_Try, /*On fail goto*//*Label 565*/ 24698, // Rule ID 1670 //
10347        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10348        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
10349        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10350        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10353        // (intrinsic_wo_chain:{ *:[v2f32] } 1101:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
10354        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDf,
10355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10357        GIR_EraseFromParent, /*InsnID*/0,
10358        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10359        // GIR_Coverage, 1670,
10360        GIR_Done,
10361      // Label 565: @24698
10362      GIM_Try, /*On fail goto*//*Label 566*/ 24738, // Rule ID 1671 //
10363        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10364        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
10365        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10366        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10368        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10369        // (intrinsic_wo_chain:{ *:[v4f32] } 1101:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
10370        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQf,
10371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10373        GIR_EraseFromParent, /*InsnID*/0,
10374        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10375        // GIR_Coverage, 1671,
10376        GIR_Done,
10377      // Label 566: @24738
10378      GIM_Try, /*On fail goto*//*Label 567*/ 24778, // Rule ID 1672 //
10379        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10380        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
10381        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10382        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10383        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10384        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10385        // (intrinsic_wo_chain:{ *:[v4f16] } 1101:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
10386        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANDh,
10387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10388        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10389        GIR_EraseFromParent, /*InsnID*/0,
10390        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10391        // GIR_Coverage, 1672,
10392        GIR_Done,
10393      // Label 567: @24778
10394      GIM_Try, /*On fail goto*//*Label 568*/ 24818, // Rule ID 1673 //
10395        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10396        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrinta,
10397        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10398        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10401        // (intrinsic_wo_chain:{ *:[v8f16] } 1101:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
10402        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTANQh,
10403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10405        GIR_EraseFromParent, /*InsnID*/0,
10406        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10407        // GIR_Coverage, 1673,
10408        GIR_Done,
10409      // Label 568: @24818
10410      GIM_Try, /*On fail goto*//*Label 569*/ 24858, // Rule ID 1674 //
10411        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10412        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
10413        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10414        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10417        // (intrinsic_wo_chain:{ *:[v2f32] } 1106:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
10418        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDf,
10419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10421        GIR_EraseFromParent, /*InsnID*/0,
10422        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10423        // GIR_Coverage, 1674,
10424        GIR_Done,
10425      // Label 569: @24858
10426      GIM_Try, /*On fail goto*//*Label 570*/ 24898, // Rule ID 1675 //
10427        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10428        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
10429        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10430        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10431        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10432        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10433        // (intrinsic_wo_chain:{ *:[v4f32] } 1106:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
10434        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQf,
10435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10436        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10437        GIR_EraseFromParent, /*InsnID*/0,
10438        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10439        // GIR_Coverage, 1675,
10440        GIR_Done,
10441      // Label 570: @24898
10442      GIM_Try, /*On fail goto*//*Label 571*/ 24938, // Rule ID 1676 //
10443        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10444        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
10445        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10446        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10447        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10449        // (intrinsic_wo_chain:{ *:[v4f16] } 1106:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
10450        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNDh,
10451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10452        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10453        GIR_EraseFromParent, /*InsnID*/0,
10454        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10455        // GIR_Coverage, 1676,
10456        GIR_Done,
10457      // Label 571: @24938
10458      GIM_Try, /*On fail goto*//*Label 572*/ 24978, // Rule ID 1677 //
10459        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10460        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintz,
10461        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10462        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10465        // (intrinsic_wo_chain:{ *:[v8f16] } 1106:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
10466        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTZNQh,
10467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10469        GIR_EraseFromParent, /*InsnID*/0,
10470        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10471        // GIR_Coverage, 1677,
10472        GIR_Done,
10473      // Label 572: @24978
10474      GIM_Try, /*On fail goto*//*Label 573*/ 25018, // Rule ID 1678 //
10475        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10476        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
10477        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10478        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10481        // (intrinsic_wo_chain:{ *:[v2f32] } 1102:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
10482        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDf,
10483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10485        GIR_EraseFromParent, /*InsnID*/0,
10486        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10487        // GIR_Coverage, 1678,
10488        GIR_Done,
10489      // Label 573: @25018
10490      GIM_Try, /*On fail goto*//*Label 574*/ 25058, // Rule ID 1679 //
10491        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10492        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
10493        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10494        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10495        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10497        // (intrinsic_wo_chain:{ *:[v4f32] } 1102:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
10498        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQf,
10499        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10500        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10501        GIR_EraseFromParent, /*InsnID*/0,
10502        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10503        // GIR_Coverage, 1679,
10504        GIR_Done,
10505      // Label 574: @25058
10506      GIM_Try, /*On fail goto*//*Label 575*/ 25098, // Rule ID 1680 //
10507        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10508        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
10509        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10510        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10513        // (intrinsic_wo_chain:{ *:[v4f16] } 1102:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
10514        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNDh,
10515        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10517        GIR_EraseFromParent, /*InsnID*/0,
10518        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10519        // GIR_Coverage, 1680,
10520        GIR_Done,
10521      // Label 575: @25098
10522      GIM_Try, /*On fail goto*//*Label 576*/ 25138, // Rule ID 1681 //
10523        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10524        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintm,
10525        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10526        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10528        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10529        // (intrinsic_wo_chain:{ *:[v8f16] } 1102:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
10530        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTMNQh,
10531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10533        GIR_EraseFromParent, /*InsnID*/0,
10534        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10535        // GIR_Coverage, 1681,
10536        GIR_Done,
10537      // Label 576: @25138
10538      GIM_Try, /*On fail goto*//*Label 577*/ 25178, // Rule ID 1682 //
10539        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10540        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
10541        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10542        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10545        // (intrinsic_wo_chain:{ *:[v2f32] } 1104:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm)  =>  (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
10546        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDf,
10547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10549        GIR_EraseFromParent, /*InsnID*/0,
10550        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10551        // GIR_Coverage, 1682,
10552        GIR_Done,
10553      // Label 577: @25178
10554      GIM_Try, /*On fail goto*//*Label 578*/ 25218, // Rule ID 1683 //
10555        GIM_CheckFeatures, GIFBS_HasNEON_HasV8,
10556        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
10557        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10558        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10560        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10561        // (intrinsic_wo_chain:{ *:[v4f32] } 1104:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm)  =>  (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
10562        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQf,
10563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10565        GIR_EraseFromParent, /*InsnID*/0,
10566        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10567        // GIR_Coverage, 1683,
10568        GIR_Done,
10569      // Label 578: @25218
10570      GIM_Try, /*On fail goto*//*Label 579*/ 25258, // Rule ID 1684 //
10571        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10572        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
10573        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10574        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10577        // (intrinsic_wo_chain:{ *:[v4f16] } 1104:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm)  =>  (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
10578        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNDh,
10579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10581        GIR_EraseFromParent, /*InsnID*/0,
10582        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10583        // GIR_Coverage, 1684,
10584        GIR_Done,
10585      // Label 579: @25258
10586      GIM_Try, /*On fail goto*//*Label 580*/ 25298, // Rule ID 1685 //
10587        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_HasV8,
10588        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrintp,
10589        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10590        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10592        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10593        // (intrinsic_wo_chain:{ *:[v8f16] } 1104:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm)  =>  (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
10594        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRINTPNQh,
10595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10597        GIR_EraseFromParent, /*InsnID*/0,
10598        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10599        // GIR_Coverage, 1685,
10600        GIR_Done,
10601      // Label 580: @25298
10602      GIM_Try, /*On fail goto*//*Label 581*/ 25338, // Rule ID 1688 //
10603        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
10604        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesimc,
10605        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
10606        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
10607        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10609        // (intrinsic_wo_chain:{ *:[v16i8] } 1002:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
10610        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESIMC,
10611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10612        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10613        GIR_EraseFromParent, /*InsnID*/0,
10614        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10615        // GIR_Coverage, 1688,
10616        GIR_Done,
10617      // Label 581: @25338
10618      GIM_Try, /*On fail goto*//*Label 582*/ 25378, // Rule ID 1689 //
10619        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
10620        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesmc,
10621        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
10622        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
10623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10625        // (intrinsic_wo_chain:{ *:[v16i8] } 1003:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm)  =>  (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
10626        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESMC,
10627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
10629        GIR_EraseFromParent, /*InsnID*/0,
10630        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10631        // GIR_Coverage, 1689,
10632        GIR_Done,
10633      // Label 582: @25378
10634      GIM_Try, /*On fail goto*//*Label 583*/ 25427, // Rule ID 1705 //
10635        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
10636        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16,
10637        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10638        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
10640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
10641        // (intrinsic_wo_chain:{ *:[i32] } 1192:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src)  =>  (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
10642        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTB16,
10643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
10644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Src
10645        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10646        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10647        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10648        GIR_EraseFromParent, /*InsnID*/0,
10649        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10650        // GIR_Coverage, 1705,
10651        GIR_Done,
10652      // Label 583: @25427
10653      GIM_Try, /*On fail goto*//*Label 584*/ 25476, // Rule ID 1899 //
10654        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
10655        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtb16,
10656        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10657        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
10659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
10660        // (intrinsic_wo_chain:{ *:[i32] } 1192:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn)  =>  (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] })
10661        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTB16,
10662        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
10663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
10664        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10665        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10666        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10667        GIR_EraseFromParent, /*InsnID*/0,
10668        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10669        // GIR_Coverage, 1899,
10670        GIR_Done,
10671      // Label 584: @25476
10672      GIM_Reject,
10673    // Label 463: @25477
10674    GIM_Try, /*On fail goto*//*Label 585*/ 46795,
10675      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
10676      GIM_Try, /*On fail goto*//*Label 586*/ 25543, // Rule ID 1914 //
10677        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
10678        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16,
10679        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10680        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10681        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
10683        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
10684        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
10685        // (intrinsic_wo_chain:{ *:[i32] } 1216:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
10686        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB16,
10687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
10688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
10689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
10690        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
10691        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10692        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10693        GIR_EraseFromParent, /*InsnID*/0,
10694        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10695        // GIR_Coverage, 1914,
10696        GIR_Done,
10697      // Label 586: @25543
10698      GIM_Try, /*On fail goto*//*Label 587*/ 25633, // Rule ID 2794 //
10699        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
10700        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
10701        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10702        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10703        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
10704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10705        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10706        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10707        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10708        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
10709        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
10710        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
10711        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10712        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
10713        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
10714        GIM_CheckIsSafeToFold, /*InsnID*/1,
10715        // (intrinsic_wo_chain:{ *:[v4i16] } 1074:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v4i16] } 1082:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1)  =>  (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
10716        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i16,
10717        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10718        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
10719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
10720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
10721        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10722        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10723        GIR_EraseFromParent, /*InsnID*/0,
10724        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10725        // GIR_Coverage, 2794,
10726        GIR_Done,
10727      // Label 587: @25633
10728      GIM_Try, /*On fail goto*//*Label 588*/ 25723, // Rule ID 2795 //
10729        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
10730        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
10731        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10732        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10733        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
10734        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10735        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10736        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10737        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10738        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
10739        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
10740        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
10741        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10742        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
10743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
10744        GIM_CheckIsSafeToFold, /*InsnID*/1,
10745        // (intrinsic_wo_chain:{ *:[v2i32] } 1074:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v2i32] } 1082:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1)  =>  (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10746        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv2i32,
10747        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10748        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
10749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
10750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
10751        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10752        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10753        GIR_EraseFromParent, /*InsnID*/0,
10754        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10755        // GIR_Coverage, 2795,
10756        GIR_Done,
10757      // Label 588: @25723
10758      GIM_Try, /*On fail goto*//*Label 589*/ 25813, // Rule ID 2796 //
10759        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
10760        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
10761        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10762        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10763        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
10764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10765        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10766        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10767        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10768        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
10769        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
10770        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
10771        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10772        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
10773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
10774        GIM_CheckIsSafeToFold, /*InsnID*/1,
10775        // (intrinsic_wo_chain:{ *:[v8i16] } 1074:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v8i16] } 1082:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1)  =>  (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
10776        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv8i16,
10777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10778        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
10779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
10780        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
10781        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10782        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10783        GIR_EraseFromParent, /*InsnID*/0,
10784        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10785        // GIR_Coverage, 2796,
10786        GIR_Done,
10787      // Label 589: @25813
10788      GIM_Try, /*On fail goto*//*Label 590*/ 25903, // Rule ID 2797 //
10789        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
10790        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
10791        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10792        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10793        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10795        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10796        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10797        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10798        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
10799        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
10800        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
10801        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
10802        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
10803        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
10804        GIM_CheckIsSafeToFold, /*InsnID*/1,
10805        // (intrinsic_wo_chain:{ *:[v4i32] } 1074:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v4i32] } 1082:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
10806        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i32,
10807        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10808        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
10809        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
10810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
10811        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10812        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10813        GIR_EraseFromParent, /*InsnID*/0,
10814        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10815        // GIR_Coverage, 2797,
10816        GIR_Done,
10817      // Label 590: @25903
10818      GIM_Try, /*On fail goto*//*Label 591*/ 25991, // Rule ID 2814 //
10819        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
10820        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
10821        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
10822        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
10823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10824        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10825        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10826        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10827        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
10828        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
10829        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
10830        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10831        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
10832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
10833        GIM_CheckIsSafeToFold, /*InsnID*/1,
10834        // (intrinsic_wo_chain:{ *:[v4i32] } 1074:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v4i32] } 1077:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1)  =>  (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
10835        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
10836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
10838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
10839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
10840        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10841        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10842        GIR_EraseFromParent, /*InsnID*/0,
10843        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10844        // GIR_Coverage, 2814,
10845        GIR_Done,
10846      // Label 591: @25991
10847      GIM_Try, /*On fail goto*//*Label 592*/ 26079, // Rule ID 2815 //
10848        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
10849        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
10850        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
10851        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
10852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
10853        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10854        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10855        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10856        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
10857        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
10858        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
10859        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10860        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
10861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
10862        GIM_CheckIsSafeToFold, /*InsnID*/1,
10863        // (intrinsic_wo_chain:{ *:[v2i64] } 1074:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v2i64] } 1077:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1)  =>  (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10864        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
10865        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
10867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
10868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
10869        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10870        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10871        GIR_EraseFromParent, /*InsnID*/0,
10872        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10873        // GIR_Coverage, 2815,
10874        GIR_Done,
10875      // Label 592: @26079
10876      GIM_Try, /*On fail goto*//*Label 593*/ 26162, // Rule ID 111 //
10877        GIM_CheckFeatures, GIFBS_IsARM,
10878        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
10879        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10880        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10881        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10882        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
10883        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10884        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10885        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10886        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
10887        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
10888        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
10889        // MIs[1] Rm
10890        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
10891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
10892        GIM_CheckIsSafeToFold, /*InsnID*/1,
10893        // (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Rn)  =>  (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
10894        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
10895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
10896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
10897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
10898        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10899        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10900        GIR_EraseFromParent, /*InsnID*/0,
10901        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10902        // GIR_Coverage, 111,
10903        GIR_Done,
10904      // Label 593: @26162
10905      GIM_Try, /*On fail goto*//*Label 594*/ 26245, // Rule ID 1927 //
10906        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
10907        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
10908        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
10909        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
10910        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
10911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
10912        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
10913        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10914        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10915        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
10916        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
10917        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
10918        // MIs[1] Rm
10919        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
10920        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
10921        GIM_CheckIsSafeToFold, /*InsnID*/1,
10922        // (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Rn)  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
10923        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
10924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
10925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
10926        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
10927        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10928        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10929        GIR_EraseFromParent, /*InsnID*/0,
10930        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10931        // GIR_Coverage, 1927,
10932        GIR_Done,
10933      // Label 594: @26245
10934      GIM_Try, /*On fail goto*//*Label 595*/ 26335, // Rule ID 2164 //
10935        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
10936        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
10937        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
10938        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
10939        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
10940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10942        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
10943        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10944        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10945        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
10946        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
10947        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
10948        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10949        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
10950        GIM_CheckIsSafeToFold, /*InsnID*/1,
10951        // (intrinsic_wo_chain:{ *:[v4i16] } 1074:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1082:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
10952        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i16,
10953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
10955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
10956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
10957        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10958        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10959        GIR_EraseFromParent, /*InsnID*/0,
10960        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10961        // GIR_Coverage, 2164,
10962        GIR_Done,
10963      // Label 595: @26335
10964      GIM_Try, /*On fail goto*//*Label 596*/ 26425, // Rule ID 2165 //
10965        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
10966        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
10967        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
10968        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
10969        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
10970        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
10971        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10972        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
10973        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
10974        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
10975        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
10976        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
10977        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
10978        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
10979        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
10980        GIM_CheckIsSafeToFold, /*InsnID*/1,
10981        // (intrinsic_wo_chain:{ *:[v2i32] } 1074:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1082:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10982        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv2i32,
10983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
10984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
10985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
10986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
10987        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
10988        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
10989        GIR_EraseFromParent, /*InsnID*/0,
10990        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
10991        // GIR_Coverage, 2165,
10992        GIR_Done,
10993      // Label 596: @26425
10994      GIM_Try, /*On fail goto*//*Label 597*/ 26515, // Rule ID 2166 //
10995        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
10996        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
10997        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
10998        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
10999        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
11000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11002        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11003        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11004        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11005        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
11006        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
11007        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
11008        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11009        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
11010        GIM_CheckIsSafeToFold, /*InsnID*/1,
11011        // (intrinsic_wo_chain:{ *:[v8i16] } 1074:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1082:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
11012        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv8i16,
11013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11017        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11018        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11019        GIR_EraseFromParent, /*InsnID*/0,
11020        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11021        // GIR_Coverage, 2166,
11022        GIR_Done,
11023      // Label 597: @26515
11024      GIM_Try, /*On fail goto*//*Label 598*/ 26605, // Rule ID 2167 //
11025        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
11026        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
11027        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
11028        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
11029        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
11030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11032        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11033        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11034        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11035        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
11036        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11037        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
11038        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11039        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
11040        GIM_CheckIsSafeToFold, /*InsnID*/1,
11041        // (intrinsic_wo_chain:{ *:[v4i32] } 1074:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1082:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
11042        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLAHv4i32,
11043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11047        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11048        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11049        GIR_EraseFromParent, /*InsnID*/0,
11050        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11051        // GIR_Coverage, 2167,
11052        GIR_Done,
11053      // Label 598: @26605
11054      GIM_Try, /*On fail goto*//*Label 599*/ 26695, // Rule ID 2172 //
11055        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
11056        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
11057        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
11058        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
11059        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
11060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11062        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11063        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11064        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11065        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
11066        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
11067        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
11068        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11069        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
11070        GIM_CheckIsSafeToFold, /*InsnID*/1,
11071        // (intrinsic_wo_chain:{ *:[v4i16] } 1094:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, (intrinsic_wo_chain:{ *:[v4i16] } 1082:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
11072        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i16,
11073        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11074        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11075        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11077        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11078        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11079        GIR_EraseFromParent, /*InsnID*/0,
11080        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11081        // GIR_Coverage, 2172,
11082        GIR_Done,
11083      // Label 599: @26695
11084      GIM_Try, /*On fail goto*//*Label 600*/ 26785, // Rule ID 2173 //
11085        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
11086        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
11087        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
11088        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
11089        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
11090        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11091        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11092        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11093        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11094        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11095        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
11096        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
11097        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
11098        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11099        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
11100        GIM_CheckIsSafeToFold, /*InsnID*/1,
11101        // (intrinsic_wo_chain:{ *:[v2i32] } 1094:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1082:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
11102        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv2i32,
11103        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11107        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11108        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11109        GIR_EraseFromParent, /*InsnID*/0,
11110        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11111        // GIR_Coverage, 2173,
11112        GIR_Done,
11113      // Label 600: @26785
11114      GIM_Try, /*On fail goto*//*Label 601*/ 26875, // Rule ID 2174 //
11115        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
11116        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
11117        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
11118        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
11119        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
11120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11122        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11123        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11124        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11125        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
11126        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
11127        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
11128        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11129        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
11130        GIM_CheckIsSafeToFold, /*InsnID*/1,
11131        // (intrinsic_wo_chain:{ *:[v8i16] } 1094:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, (intrinsic_wo_chain:{ *:[v8i16] } 1082:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm))  =>  (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
11132        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv8i16,
11133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11137        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11138        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11139        GIR_EraseFromParent, /*InsnID*/0,
11140        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11141        // GIR_Coverage, 2174,
11142        GIR_Done,
11143      // Label 601: @26875
11144      GIM_Try, /*On fail goto*//*Label 602*/ 26965, // Rule ID 2175 //
11145        GIM_CheckFeatures, GIFBS_HasNEON_HasV8_1a,
11146        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
11147        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
11148        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
11149        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
11150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11152        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11153        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11154        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11155        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
11156        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
11157        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
11158        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11159        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::QPRRegClassID,
11160        GIM_CheckIsSafeToFold, /*InsnID*/1,
11161        // (intrinsic_wo_chain:{ *:[v4i32] } 1094:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1082:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm))  =>  (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
11162        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMLSHv4i32,
11163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11166        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11167        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11168        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11169        GIR_EraseFromParent, /*InsnID*/0,
11170        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11171        // GIR_Coverage, 2175,
11172        GIR_Done,
11173      // Label 602: @26965
11174      GIM_Try, /*On fail goto*//*Label 603*/ 27053, // Rule ID 2180 //
11175        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
11176        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
11177        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
11178        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
11179        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11180        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11181        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11182        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11183        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11184        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
11185        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
11186        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
11187        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11188        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
11189        GIM_CheckIsSafeToFold, /*InsnID*/1,
11190        // (intrinsic_wo_chain:{ *:[v4i32] } 1074:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1077:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
11191        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv4i32,
11192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11196        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11197        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11198        GIR_EraseFromParent, /*InsnID*/0,
11199        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11200        // GIR_Coverage, 2180,
11201        GIR_Done,
11202      // Label 603: @27053
11203      GIM_Try, /*On fail goto*//*Label 604*/ 27141, // Rule ID 2181 //
11204        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
11205        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
11206        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
11207        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
11208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11210        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11211        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11212        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11213        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
11214        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
11215        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
11216        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11217        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
11218        GIM_CheckIsSafeToFold, /*InsnID*/1,
11219        // (intrinsic_wo_chain:{ *:[v2i64] } 1074:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 1077:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
11220        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLALv2i64,
11221        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11225        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11226        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11227        GIR_EraseFromParent, /*InsnID*/0,
11228        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11229        // GIR_Coverage, 2181,
11230        GIR_Done,
11231      // Label 604: @27141
11232      GIM_Try, /*On fail goto*//*Label 605*/ 27229, // Rule ID 2187 //
11233        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
11234        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
11235        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
11236        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
11237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11238        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11239        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11240        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11241        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11242        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
11243        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
11244        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
11245        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11246        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
11247        GIM_CheckIsSafeToFold, /*InsnID*/1,
11248        // (intrinsic_wo_chain:{ *:[v4i32] } 1094:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 1077:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
11249        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv4i32,
11250        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11254        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11255        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11256        GIR_EraseFromParent, /*InsnID*/0,
11257        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11258        // GIR_Coverage, 2187,
11259        GIR_Done,
11260      // Label 605: @27229
11261      GIM_Try, /*On fail goto*//*Label 606*/ 27317, // Rule ID 2188 //
11262        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
11263        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
11264        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
11265        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
11266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11268        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11269        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11270        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11271        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vqdmull,
11272        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
11273        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
11274        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11275        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
11276        GIM_CheckIsSafeToFold, /*InsnID*/1,
11277        // (intrinsic_wo_chain:{ *:[v2i64] } 1094:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 1077:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
11278        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMLSLv2i64,
11279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
11281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
11282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
11283        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11284        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11285        GIR_EraseFromParent, /*InsnID*/0,
11286        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11287        // GIR_Coverage, 2188,
11288        GIR_Done,
11289      // Label 606: @27317
11290      GIM_Try, /*On fail goto*//*Label 607*/ 27400, // Rule ID 112 //
11291        GIM_CheckFeatures, GIFBS_IsARM,
11292        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
11293        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11294        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11295        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11298        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11299        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11300        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11301        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
11302        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
11303        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11304        // MIs[1] Rn
11305        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
11306        GIM_CheckIsSafeToFold, /*InsnID*/1,
11307        // (intrinsic_wo_chain:{ *:[i32] } 1139:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn))  =>  (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
11308        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDSUB,
11309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11310        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
11311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
11312        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11313        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11314        GIR_EraseFromParent, /*InsnID*/0,
11315        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11316        // GIR_Coverage, 112,
11317        GIR_Done,
11318      // Label 607: @27400
11319      GIM_Try, /*On fail goto*//*Label 608*/ 27483, // Rule ID 1928 //
11320        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
11321        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
11322        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11323        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11324        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11325        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
11326        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
11327        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11328        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11329        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11330        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
11331        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
11332        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
11333        // MIs[1] Rn
11334        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
11335        GIM_CheckIsSafeToFold, /*InsnID*/1,
11336        // (intrinsic_wo_chain:{ *:[i32] } 1139:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn))  =>  (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
11337        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDSUB,
11338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
11340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
11341        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11342        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11343        GIR_EraseFromParent, /*InsnID*/0,
11344        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11345        // GIR_Coverage, 1928,
11346        GIR_Done,
11347      // Label 608: @27483
11348      GIM_Try, /*On fail goto*//*Label 609*/ 27566, // Rule ID 2504 //
11349        GIM_CheckFeatures, GIFBS_IsARM,
11350        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
11351        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11352        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11353        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11356        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11357        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11358        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11359        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
11360        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
11361        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11362        // MIs[1] Rm
11363        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
11364        GIM_CheckIsSafeToFold, /*InsnID*/1,
11365        // (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rm))  =>  (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
11366        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QDADD,
11367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
11369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
11370        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11371        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11372        GIR_EraseFromParent, /*InsnID*/0,
11373        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11374        // GIR_Coverage, 2504,
11375        GIR_Done,
11376      // Label 609: @27566
11377      GIM_Try, /*On fail goto*//*Label 610*/ 27649, // Rule ID 2755 //
11378        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
11379        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
11380        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11381        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11382        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11383        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
11384        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
11385        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11386        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
11387        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
11388        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_qadd,
11389        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
11390        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
11391        // MIs[1] Rm
11392        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
11393        GIM_CheckIsSafeToFold, /*InsnID*/1,
11394        // (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rm))  =>  (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
11395        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QDADD,
11396        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11397        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
11398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
11399        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11400        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11401        GIR_EraseFromParent, /*InsnID*/0,
11402        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11403        // GIR_Coverage, 2755,
11404        GIR_Done,
11405      // Label 610: @27649
11406      GIM_Try, /*On fail goto*//*Label 611*/ 27717, // Rule ID 1719 //
11407        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
11408        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
11409        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11410        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11411        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11412        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11413        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11414        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11415        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11416        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
11417        // MIs[1] Operand 1
11418        // No operand predicates
11419        GIM_CheckIsSafeToFold, /*InsnID*/1,
11420        // (intrinsic_wo_chain:{ *:[i32] } 1211:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] })
11421        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT,
11422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11423        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
11424        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
11425        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11426        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11427        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11428        GIR_EraseFromParent, /*InsnID*/0,
11429        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11430        // GIR_Coverage, 1719,
11431        GIR_Done,
11432      // Label 611: @27717
11433      GIM_Try, /*On fail goto*//*Label 612*/ 27782, // Rule ID 1723 //
11434        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
11435        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
11436        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11437        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11438        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11439        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11440        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11441        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11442        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11443        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
11444        // MIs[1] Operand 1
11445        // No operand predicates
11446        GIM_CheckIsSafeToFold, /*InsnID*/1,
11447        // (intrinsic_wo_chain:{ *:[i32] } 1212:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos)  =>  (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a)
11448        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAT16,
11449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11450        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
11451        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
11452        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11453        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11454        GIR_EraseFromParent, /*InsnID*/0,
11455        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11456        // GIR_Coverage, 1723,
11457        GIR_Done,
11458      // Label 612: @27782
11459      GIM_Try, /*On fail goto*//*Label 613*/ 27850, // Rule ID 1932 //
11460        GIM_CheckFeatures, GIFBS_IsThumb2,
11461        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat,
11462        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11463        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11464        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11465        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
11466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
11467        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11468        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11469        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_31,
11470        // MIs[1] Operand 1
11471        // No operand predicates
11472        GIM_CheckIsSafeToFold, /*InsnID*/1,
11473        // (intrinsic_wo_chain:{ *:[i32] } 1211:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos)  =>  (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] })
11474        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT,
11475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11476        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
11477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
11478        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
11479        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11480        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11481        GIR_EraseFromParent, /*InsnID*/0,
11482        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11483        // GIR_Coverage, 1932,
11484        GIR_Done,
11485      // Label 613: @27850
11486      GIM_Try, /*On fail goto*//*Label 614*/ 27915, // Rule ID 1934 //
11487        GIM_CheckFeatures, GIFBS_IsThumb2,
11488        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usat16,
11489        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11490        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11491        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
11493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
11494        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11495        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11496        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
11497        // MIs[1] Operand 1
11498        // No operand predicates
11499        GIM_CheckIsSafeToFold, /*InsnID*/1,
11500        // (intrinsic_wo_chain:{ *:[i32] } 1212:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos)  =>  (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a)
11501        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAT16,
11502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11503        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
11504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
11505        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11506        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11507        GIR_EraseFromParent, /*InsnID*/0,
11508        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11509        // GIR_Coverage, 1934,
11510        GIR_Done,
11511      // Label 614: @27915
11512      GIM_Try, /*On fail goto*//*Label 615*/ 27977, // Rule ID 1623 //
11513        GIM_CheckFeatures, GIFBS_HasNEON,
11514        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
11515        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
11516        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
11517        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11519        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11520        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11521        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11522        // MIs[1] Operand 1
11523        // No operand predicates
11524        GIM_CheckIsSafeToFold, /*InsnID*/1,
11525        // (intrinsic_wo_chain:{ *:[v2i32] } 1025:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11526        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsd,
11527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11529        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11530        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11531        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11532        GIR_EraseFromParent, /*InsnID*/0,
11533        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11534        // GIR_Coverage, 1623,
11535        GIR_Done,
11536      // Label 615: @27977
11537      GIM_Try, /*On fail goto*//*Label 616*/ 28039, // Rule ID 1624 //
11538        GIM_CheckFeatures, GIFBS_HasNEON,
11539        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
11540        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
11541        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
11542        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11545        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11546        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11547        // MIs[1] Operand 1
11548        // No operand predicates
11549        GIM_CheckIsSafeToFold, /*InsnID*/1,
11550        // (intrinsic_wo_chain:{ *:[v2i32] } 1026:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11551        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xud,
11552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11554        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11555        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11556        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11557        GIR_EraseFromParent, /*InsnID*/0,
11558        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11559        // GIR_Coverage, 1624,
11560        GIR_Done,
11561      // Label 616: @28039
11562      GIM_Try, /*On fail goto*//*Label 617*/ 28101, // Rule ID 1625 //
11563        GIM_CheckFeatures, GIFBS_HasNEON,
11564        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
11565        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
11566        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
11567        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11570        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11571        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11572        // MIs[1] Operand 1
11573        // No operand predicates
11574        GIM_CheckIsSafeToFold, /*InsnID*/1,
11575        // (intrinsic_wo_chain:{ *:[v2f32] } 1028:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11576        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fd,
11577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11579        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11580        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11581        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11582        GIR_EraseFromParent, /*InsnID*/0,
11583        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11584        // GIR_Coverage, 1625,
11585        GIR_Done,
11586      // Label 617: @28101
11587      GIM_Try, /*On fail goto*//*Label 618*/ 28163, // Rule ID 1626 //
11588        GIM_CheckFeatures, GIFBS_HasNEON,
11589        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
11590        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
11591        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
11592        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11593        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11594        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11595        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11596        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11597        // MIs[1] Operand 1
11598        // No operand predicates
11599        GIM_CheckIsSafeToFold, /*InsnID*/1,
11600        // (intrinsic_wo_chain:{ *:[v2f32] } 1029:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11601        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fd,
11602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11604        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11605        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11606        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11607        GIR_EraseFromParent, /*InsnID*/0,
11608        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11609        // GIR_Coverage, 1626,
11610        GIR_Done,
11611      // Label 618: @28163
11612      GIM_Try, /*On fail goto*//*Label 619*/ 28225, // Rule ID 1627 //
11613        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
11614        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
11615        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
11616        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
11617        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11620        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11621        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11622        // MIs[1] Operand 1
11623        // No operand predicates
11624        GIM_CheckIsSafeToFold, /*InsnID*/1,
11625        // (intrinsic_wo_chain:{ *:[v4i16] } 1025:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11626        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsd,
11627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11629        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11630        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11631        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11632        GIR_EraseFromParent, /*InsnID*/0,
11633        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11634        // GIR_Coverage, 1627,
11635        GIR_Done,
11636      // Label 619: @28225
11637      GIM_Try, /*On fail goto*//*Label 620*/ 28287, // Rule ID 1628 //
11638        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
11639        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
11640        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
11641        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
11642        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11645        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11646        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11647        // MIs[1] Operand 1
11648        // No operand predicates
11649        GIM_CheckIsSafeToFold, /*InsnID*/1,
11650        // (intrinsic_wo_chain:{ *:[v4i16] } 1026:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11651        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xud,
11652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11654        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11655        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11656        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11657        GIR_EraseFromParent, /*InsnID*/0,
11658        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11659        // GIR_Coverage, 1628,
11660        GIR_Done,
11661      // Label 620: @28287
11662      GIM_Try, /*On fail goto*//*Label 621*/ 28349, // Rule ID 1629 //
11663        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
11664        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
11665        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
11666        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
11667        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11668        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11670        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11671        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11672        // MIs[1] Operand 1
11673        // No operand predicates
11674        GIM_CheckIsSafeToFold, /*InsnID*/1,
11675        // (intrinsic_wo_chain:{ *:[v4f16] } 1028:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11676        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hd,
11677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11679        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11680        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11681        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11682        GIR_EraseFromParent, /*InsnID*/0,
11683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11684        // GIR_Coverage, 1629,
11685        GIR_Done,
11686      // Label 621: @28349
11687      GIM_Try, /*On fail goto*//*Label 622*/ 28411, // Rule ID 1630 //
11688        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
11689        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
11690        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
11691        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
11692        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
11694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
11695        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11696        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11697        // MIs[1] Operand 1
11698        // No operand predicates
11699        GIM_CheckIsSafeToFold, /*InsnID*/1,
11700        // (intrinsic_wo_chain:{ *:[v4f16] } 1029:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11701        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hd,
11702        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11703        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11704        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11705        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11706        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11707        GIR_EraseFromParent, /*InsnID*/0,
11708        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11709        // GIR_Coverage, 1630,
11710        GIR_Done,
11711      // Label 622: @28411
11712      GIM_Try, /*On fail goto*//*Label 623*/ 28473, // Rule ID 1631 //
11713        GIM_CheckFeatures, GIFBS_HasNEON,
11714        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
11715        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
11716        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
11717        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11718        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11719        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11720        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11721        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11722        // MIs[1] Operand 1
11723        // No operand predicates
11724        GIM_CheckIsSafeToFold, /*InsnID*/1,
11725        // (intrinsic_wo_chain:{ *:[v4i32] } 1025:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11726        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xsq,
11727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11729        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11730        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11731        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11732        GIR_EraseFromParent, /*InsnID*/0,
11733        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11734        // GIR_Coverage, 1631,
11735        GIR_Done,
11736      // Label 623: @28473
11737      GIM_Try, /*On fail goto*//*Label 624*/ 28535, // Rule ID 1632 //
11738        GIM_CheckFeatures, GIFBS_HasNEON,
11739        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
11740        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
11741        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
11742        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11745        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11746        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11747        // MIs[1] Operand 1
11748        // No operand predicates
11749        GIM_CheckIsSafeToFold, /*InsnID*/1,
11750        // (intrinsic_wo_chain:{ *:[v4i32] } 1026:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2xuq,
11752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11754        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11755        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11756        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11757        GIR_EraseFromParent, /*InsnID*/0,
11758        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11759        // GIR_Coverage, 1632,
11760        GIR_Done,
11761      // Label 624: @28535
11762      GIM_Try, /*On fail goto*//*Label 625*/ 28597, // Rule ID 1633 //
11763        GIM_CheckFeatures, GIFBS_HasNEON,
11764        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
11765        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
11766        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
11767        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11768        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11770        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11771        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11772        // MIs[1] Operand 1
11773        // No operand predicates
11774        GIM_CheckIsSafeToFold, /*InsnID*/1,
11775        // (intrinsic_wo_chain:{ *:[v4f32] } 1028:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11776        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2fq,
11777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11778        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11779        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11780        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11781        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11782        GIR_EraseFromParent, /*InsnID*/0,
11783        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11784        // GIR_Coverage, 1633,
11785        GIR_Done,
11786      // Label 625: @28597
11787      GIM_Try, /*On fail goto*//*Label 626*/ 28659, // Rule ID 1634 //
11788        GIM_CheckFeatures, GIFBS_HasNEON,
11789        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
11790        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
11791        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
11792        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11795        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11796        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11797        // MIs[1] Operand 1
11798        // No operand predicates
11799        GIM_CheckIsSafeToFold, /*InsnID*/1,
11800        // (intrinsic_wo_chain:{ *:[v4f32] } 1029:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11801        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2fq,
11802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11804        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11805        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11806        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11807        GIR_EraseFromParent, /*InsnID*/0,
11808        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11809        // GIR_Coverage, 1634,
11810        GIR_Done,
11811      // Label 626: @28659
11812      GIM_Try, /*On fail goto*//*Label 627*/ 28721, // Rule ID 1635 //
11813        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
11814        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxs,
11815        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
11816        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
11817        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11818        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11820        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11821        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11822        // MIs[1] Operand 1
11823        // No operand predicates
11824        GIM_CheckIsSafeToFold, /*InsnID*/1,
11825        // (intrinsic_wo_chain:{ *:[v8i16] } 1025:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11826        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xsq,
11827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11829        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11830        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11831        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11832        GIR_EraseFromParent, /*InsnID*/0,
11833        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11834        // GIR_Coverage, 1635,
11835        GIR_Done,
11836      // Label 627: @28721
11837      GIM_Try, /*On fail goto*//*Label 628*/ 28783, // Rule ID 1636 //
11838        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
11839        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfp2fxu,
11840        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
11841        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
11842        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11845        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11846        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11847        // MIs[1] Operand 1
11848        // No operand predicates
11849        GIM_CheckIsSafeToFold, /*InsnID*/1,
11850        // (intrinsic_wo_chain:{ *:[v8i16] } 1026:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11851        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2xuq,
11852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11854        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11855        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11856        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11857        GIR_EraseFromParent, /*InsnID*/0,
11858        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11859        // GIR_Coverage, 1636,
11860        GIR_Done,
11861      // Label 628: @28783
11862      GIM_Try, /*On fail goto*//*Label 629*/ 28845, // Rule ID 1637 //
11863        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
11864        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxs2fp,
11865        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
11866        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
11867        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11870        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11871        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11872        // MIs[1] Operand 1
11873        // No operand predicates
11874        GIM_CheckIsSafeToFold, /*InsnID*/1,
11875        // (intrinsic_wo_chain:{ *:[v8f16] } 1028:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11876        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxs2hq,
11877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11879        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11880        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11881        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11882        GIR_EraseFromParent, /*InsnID*/0,
11883        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11884        // GIR_Coverage, 1637,
11885        GIR_Done,
11886      // Label 629: @28845
11887      GIM_Try, /*On fail goto*//*Label 630*/ 28907, // Rule ID 1638 //
11888        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
11889        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vcvtfxu2fp,
11890        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
11891        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
11892        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11893        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
11894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
11895        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
11896        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
11897        // MIs[1] Operand 1
11898        // No operand predicates
11899        GIM_CheckIsSafeToFold, /*InsnID*/1,
11900        // (intrinsic_wo_chain:{ *:[v8f16] } 1029:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)  =>  (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
11901        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTxu2hq,
11902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
11903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
11904        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
11905        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11906        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11907        GIR_EraseFromParent, /*InsnID*/0,
11908        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11909        // GIR_Coverage, 1638,
11910        GIR_Done,
11911      // Label 630: @28907
11912      GIM_Try, /*On fail goto*//*Label 631*/ 28965, // Rule ID 107 //
11913        GIM_CheckFeatures, GIFBS_IsARM,
11914        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
11915        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11916        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11917        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11919        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11920        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
11921        // (intrinsic_wo_chain:{ *:[i32] } 1136:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
11922        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD8,
11923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11924        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
11925        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
11926        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11927        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11928        GIR_EraseFromParent, /*InsnID*/0,
11929        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11930        // GIR_Coverage, 107,
11931        GIR_Done,
11932      // Label 631: @28965
11933      GIM_Try, /*On fail goto*//*Label 632*/ 29023, // Rule ID 108 //
11934        GIM_CheckFeatures, GIFBS_IsARM,
11935        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
11936        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11937        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11938        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11939        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
11942        // (intrinsic_wo_chain:{ *:[i32] } 1135:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
11943        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD16,
11944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
11946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
11947        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11948        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11949        GIR_EraseFromParent, /*InsnID*/0,
11950        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11951        // GIR_Coverage, 108,
11952        GIR_Done,
11953      // Label 632: @29023
11954      GIM_Try, /*On fail goto*//*Label 633*/ 29081, // Rule ID 109 //
11955        GIM_CheckFeatures, GIFBS_IsARM,
11956        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
11957        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11958        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11959        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11961        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
11963        // (intrinsic_wo_chain:{ *:[i32] } 1140:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
11964        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB16,
11965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11966        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
11967        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
11968        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11969        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11970        GIR_EraseFromParent, /*InsnID*/0,
11971        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11972        // GIR_Coverage, 109,
11973        GIR_Done,
11974      // Label 633: @29081
11975      GIM_Try, /*On fail goto*//*Label 634*/ 29139, // Rule ID 110 //
11976        GIM_CheckFeatures, GIFBS_IsARM,
11977        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
11978        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
11979        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
11980        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
11981        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
11982        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
11983        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
11984        // (intrinsic_wo_chain:{ *:[i32] } 1141:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
11985        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB8,
11986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
11987        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
11988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
11989        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
11990        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
11991        GIR_EraseFromParent, /*InsnID*/0,
11992        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
11993        // GIR_Coverage, 110,
11994        GIR_Done,
11995      // Label 634: @29139
11996      GIM_Try, /*On fail goto*//*Label 635*/ 29197, // Rule ID 113 //
11997        GIM_CheckFeatures, GIFBS_IsARM,
11998        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
11999        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12000        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12001        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12002        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12003        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12004        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12005        // (intrinsic_wo_chain:{ *:[i32] } 1139:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
12006        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSUB,
12007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12008        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
12009        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
12010        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12011        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12012        GIR_EraseFromParent, /*InsnID*/0,
12013        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12014        // GIR_Coverage, 113,
12015        GIR_Done,
12016      // Label 635: @29197
12017      GIM_Try, /*On fail goto*//*Label 636*/ 29255, // Rule ID 114 //
12018        GIM_CheckFeatures, GIFBS_IsARM,
12019        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
12020        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12021        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12022        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12025        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12026        // (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)  =>  (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
12027        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QADD,
12028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12029        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
12030        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
12031        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12032        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12033        GIR_EraseFromParent, /*InsnID*/0,
12034        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12035        // GIR_Coverage, 114,
12036        GIR_Done,
12037      // Label 636: @29255
12038      GIM_Try, /*On fail goto*//*Label 637*/ 29313, // Rule ID 115 //
12039        GIM_CheckFeatures, GIFBS_IsARM,
12040        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
12041        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12042        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12043        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12045        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12046        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12047        // (intrinsic_wo_chain:{ *:[i32] } 1203:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12048        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD16,
12049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12050        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12051        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12052        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12053        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12054        GIR_EraseFromParent, /*InsnID*/0,
12055        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12056        // GIR_Coverage, 115,
12057        GIR_Done,
12058      // Label 637: @29313
12059      GIM_Try, /*On fail goto*//*Label 638*/ 29371, // Rule ID 116 //
12060        GIM_CheckFeatures, GIFBS_IsARM,
12061        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
12062        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12063        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12064        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12066        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12067        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12068        // (intrinsic_wo_chain:{ *:[i32] } 1204:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12069        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQADD8,
12070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12071        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12072        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12073        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12074        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12075        GIR_EraseFromParent, /*InsnID*/0,
12076        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12077        // GIR_Coverage, 116,
12078        GIR_Done,
12079      // Label 638: @29371
12080      GIM_Try, /*On fail goto*//*Label 639*/ 29429, // Rule ID 117 //
12081        GIM_CheckFeatures, GIFBS_IsARM,
12082        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
12083        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12084        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12085        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12088        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12089        // (intrinsic_wo_chain:{ *:[i32] } 1207:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12090        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB16,
12091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12093        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12094        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12095        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12096        GIR_EraseFromParent, /*InsnID*/0,
12097        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12098        // GIR_Coverage, 117,
12099        GIR_Done,
12100      // Label 639: @29429
12101      GIM_Try, /*On fail goto*//*Label 640*/ 29487, // Rule ID 118 //
12102        GIM_CheckFeatures, GIFBS_IsARM,
12103        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
12104        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12105        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12106        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12110        // (intrinsic_wo_chain:{ *:[i32] } 1208:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12111        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSUB8,
12112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12114        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12115        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12116        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12117        GIR_EraseFromParent, /*InsnID*/0,
12118        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12119        // GIR_Coverage, 118,
12120        GIR_Done,
12121      // Label 640: @29487
12122      GIM_Try, /*On fail goto*//*Label 641*/ 29545, // Rule ID 119 //
12123        GIM_CheckFeatures, GIFBS_IsARM,
12124        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
12125        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12126        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12127        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12131        // (intrinsic_wo_chain:{ *:[i32] } 1137:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12132        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QASX,
12133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12136        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12137        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12138        GIR_EraseFromParent, /*InsnID*/0,
12139        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12140        // GIR_Coverage, 119,
12141        GIR_Done,
12142      // Label 641: @29545
12143      GIM_Try, /*On fail goto*//*Label 642*/ 29603, // Rule ID 120 //
12144        GIM_CheckFeatures, GIFBS_IsARM,
12145        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
12146        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12147        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12148        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12150        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12152        // (intrinsic_wo_chain:{ *:[i32] } 1138:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::QSAX,
12154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12157        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12158        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12159        GIR_EraseFromParent, /*InsnID*/0,
12160        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12161        // GIR_Coverage, 120,
12162        GIR_Done,
12163      // Label 642: @29603
12164      GIM_Try, /*On fail goto*//*Label 643*/ 29661, // Rule ID 121 //
12165        GIM_CheckFeatures, GIFBS_IsARM,
12166        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
12167        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12168        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12169        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12171        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12172        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12173        // (intrinsic_wo_chain:{ *:[i32] } 1205:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12174        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQASX,
12175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12176        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12177        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12178        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12179        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12180        GIR_EraseFromParent, /*InsnID*/0,
12181        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12182        // GIR_Coverage, 121,
12183        GIR_Done,
12184      // Label 643: @29661
12185      GIM_Try, /*On fail goto*//*Label 644*/ 29719, // Rule ID 122 //
12186        GIM_CheckFeatures, GIFBS_IsARM,
12187        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
12188        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12189        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12190        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12192        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12193        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12194        // (intrinsic_wo_chain:{ *:[i32] } 1206:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12195        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UQSAX,
12196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12197        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12198        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12199        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12200        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12201        GIR_EraseFromParent, /*InsnID*/0,
12202        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12203        // GIR_Coverage, 122,
12204        GIR_Done,
12205      // Label 644: @29719
12206      GIM_Try, /*On fail goto*//*Label 645*/ 29777, // Rule ID 135 //
12207        GIM_CheckFeatures, GIFBS_IsARM,
12208        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
12209        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12210        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12211        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12213        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12214        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12215        // (intrinsic_wo_chain:{ *:[i32] } 1149:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12216        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHASX,
12217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12218        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12219        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12220        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12221        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12222        GIR_EraseFromParent, /*InsnID*/0,
12223        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12224        // GIR_Coverage, 135,
12225        GIR_Done,
12226      // Label 645: @29777
12227      GIM_Try, /*On fail goto*//*Label 646*/ 29835, // Rule ID 136 //
12228        GIM_CheckFeatures, GIFBS_IsARM,
12229        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
12230        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12231        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12232        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12234        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12235        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12236        // (intrinsic_wo_chain:{ *:[i32] } 1147:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12237        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD16,
12238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12239        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12240        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12241        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12242        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12243        GIR_EraseFromParent, /*InsnID*/0,
12244        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12245        // GIR_Coverage, 136,
12246        GIR_Done,
12247      // Label 646: @29835
12248      GIM_Try, /*On fail goto*//*Label 647*/ 29893, // Rule ID 137 //
12249        GIM_CheckFeatures, GIFBS_IsARM,
12250        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
12251        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12252        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12253        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12256        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12257        // (intrinsic_wo_chain:{ *:[i32] } 1148:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12258        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHADD8,
12259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12261        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12262        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12263        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12264        GIR_EraseFromParent, /*InsnID*/0,
12265        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12266        // GIR_Coverage, 137,
12267        GIR_Done,
12268      // Label 647: @29893
12269      GIM_Try, /*On fail goto*//*Label 648*/ 29951, // Rule ID 138 //
12270        GIM_CheckFeatures, GIFBS_IsARM,
12271        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
12272        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12273        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12274        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12278        // (intrinsic_wo_chain:{ *:[i32] } 1150:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12279        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSAX,
12280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12283        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12284        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12285        GIR_EraseFromParent, /*InsnID*/0,
12286        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12287        // GIR_Coverage, 138,
12288        GIR_Done,
12289      // Label 648: @29951
12290      GIM_Try, /*On fail goto*//*Label 649*/ 30009, // Rule ID 139 //
12291        GIM_CheckFeatures, GIFBS_IsARM,
12292        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
12293        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12294        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12295        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12297        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12299        // (intrinsic_wo_chain:{ *:[i32] } 1151:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12300        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB16,
12301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12302        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12304        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12305        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12306        GIR_EraseFromParent, /*InsnID*/0,
12307        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12308        // GIR_Coverage, 139,
12309        GIR_Done,
12310      // Label 649: @30009
12311      GIM_Try, /*On fail goto*//*Label 650*/ 30067, // Rule ID 140 //
12312        GIM_CheckFeatures, GIFBS_IsARM,
12313        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
12314        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12315        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12316        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12318        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12319        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12320        // (intrinsic_wo_chain:{ *:[i32] } 1152:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12321        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHSUB8,
12322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12325        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12326        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12327        GIR_EraseFromParent, /*InsnID*/0,
12328        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12329        // GIR_Coverage, 140,
12330        GIR_Done,
12331      // Label 650: @30067
12332      GIM_Try, /*On fail goto*//*Label 651*/ 30125, // Rule ID 141 //
12333        GIM_CheckFeatures, GIFBS_IsARM,
12334        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
12335        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12336        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12337        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12339        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12340        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12341        // (intrinsic_wo_chain:{ *:[i32] } 1198:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12342        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHASX,
12343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12344        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12345        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12346        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12347        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12348        GIR_EraseFromParent, /*InsnID*/0,
12349        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12350        // GIR_Coverage, 141,
12351        GIR_Done,
12352      // Label 651: @30125
12353      GIM_Try, /*On fail goto*//*Label 652*/ 30183, // Rule ID 142 //
12354        GIM_CheckFeatures, GIFBS_IsARM,
12355        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
12356        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12357        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12358        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12360        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12361        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12362        // (intrinsic_wo_chain:{ *:[i32] } 1196:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12363        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD16,
12364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12365        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12366        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12367        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12368        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12369        GIR_EraseFromParent, /*InsnID*/0,
12370        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12371        // GIR_Coverage, 142,
12372        GIR_Done,
12373      // Label 652: @30183
12374      GIM_Try, /*On fail goto*//*Label 653*/ 30241, // Rule ID 143 //
12375        GIM_CheckFeatures, GIFBS_IsARM,
12376        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
12377        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12378        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12379        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12383        // (intrinsic_wo_chain:{ *:[i32] } 1197:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12384        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHADD8,
12385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12386        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12388        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12389        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12390        GIR_EraseFromParent, /*InsnID*/0,
12391        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12392        // GIR_Coverage, 143,
12393        GIR_Done,
12394      // Label 653: @30241
12395      GIM_Try, /*On fail goto*//*Label 654*/ 30299, // Rule ID 144 //
12396        GIM_CheckFeatures, GIFBS_IsARM,
12397        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
12398        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12399        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12400        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12401        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12402        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12404        // (intrinsic_wo_chain:{ *:[i32] } 1199:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12405        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSAX,
12406        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12407        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12409        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12410        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12411        GIR_EraseFromParent, /*InsnID*/0,
12412        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12413        // GIR_Coverage, 144,
12414        GIR_Done,
12415      // Label 654: @30299
12416      GIM_Try, /*On fail goto*//*Label 655*/ 30357, // Rule ID 145 //
12417        GIM_CheckFeatures, GIFBS_IsARM,
12418        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
12419        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12420        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12421        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12423        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12424        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12425        // (intrinsic_wo_chain:{ *:[i32] } 1200:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12426        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB16,
12427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12428        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12429        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12430        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12431        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12432        GIR_EraseFromParent, /*InsnID*/0,
12433        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12434        // GIR_Coverage, 145,
12435        GIR_Done,
12436      // Label 655: @30357
12437      GIM_Try, /*On fail goto*//*Label 656*/ 30415, // Rule ID 146 //
12438        GIM_CheckFeatures, GIFBS_IsARM,
12439        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
12440        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12441        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12442        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12444        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12445        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12446        // (intrinsic_wo_chain:{ *:[i32] } 1201:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12447        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UHSUB8,
12448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12449        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12450        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12451        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12452        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12453        GIR_EraseFromParent, /*InsnID*/0,
12454        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12455        // GIR_Coverage, 146,
12456        GIR_Done,
12457      // Label 656: @30415
12458      GIM_Try, /*On fail goto*//*Label 657*/ 30473, // Rule ID 147 //
12459        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
12460        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
12461        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12462        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12463        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
12465        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
12466        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
12467        // (intrinsic_wo_chain:{ *:[i32] } 1209:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
12468        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAD8,
12469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12470        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12471        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12472        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12473        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12474        GIR_EraseFromParent, /*InsnID*/0,
12475        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12476        // GIR_Coverage, 147,
12477        GIR_Done,
12478      // Label 657: @30473
12479      GIM_Try, /*On fail goto*//*Label 658*/ 30525, // Rule ID 206 //
12480        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
12481        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
12482        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12483        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12484        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12486        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12487        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12488        // (intrinsic_wo_chain:{ *:[i32] } 972:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12489        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32B,
12490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12491        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12492        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12493        GIR_EraseFromParent, /*InsnID*/0,
12494        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12495        // GIR_Coverage, 206,
12496        GIR_Done,
12497      // Label 658: @30525
12498      GIM_Try, /*On fail goto*//*Label 659*/ 30577, // Rule ID 207 //
12499        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
12500        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
12501        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12502        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12503        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12507        // (intrinsic_wo_chain:{ *:[i32] } 973:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12508        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CB,
12509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12512        GIR_EraseFromParent, /*InsnID*/0,
12513        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12514        // GIR_Coverage, 207,
12515        GIR_Done,
12516      // Label 659: @30577
12517      GIM_Try, /*On fail goto*//*Label 660*/ 30629, // Rule ID 208 //
12518        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
12519        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
12520        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12521        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12522        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12526        // (intrinsic_wo_chain:{ *:[i32] } 976:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12527        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32H,
12528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12531        GIR_EraseFromParent, /*InsnID*/0,
12532        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12533        // GIR_Coverage, 208,
12534        GIR_Done,
12535      // Label 660: @30629
12536      GIM_Try, /*On fail goto*//*Label 661*/ 30681, // Rule ID 209 //
12537        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
12538        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
12539        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12540        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12541        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12544        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12545        // (intrinsic_wo_chain:{ *:[i32] } 974:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12546        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CH,
12547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12549        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12550        GIR_EraseFromParent, /*InsnID*/0,
12551        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12552        // GIR_Coverage, 209,
12553        GIR_Done,
12554      // Label 661: @30681
12555      GIM_Try, /*On fail goto*//*Label 662*/ 30733, // Rule ID 210 //
12556        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
12557        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
12558        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12559        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12560        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12564        // (intrinsic_wo_chain:{ *:[i32] } 977:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12565        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32W,
12566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12569        GIR_EraseFromParent, /*InsnID*/0,
12570        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12571        // GIR_Coverage, 210,
12572        GIR_Done,
12573      // Label 662: @30733
12574      GIM_Try, /*On fail goto*//*Label 663*/ 30785, // Rule ID 211 //
12575        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsARM,
12576        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
12577        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12578        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12579        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
12581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
12582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
12583        // (intrinsic_wo_chain:{ *:[i32] } 975:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
12584        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CRC32CW,
12585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12588        GIR_EraseFromParent, /*InsnID*/0,
12589        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12590        // GIR_Coverage, 211,
12591        GIR_Done,
12592      // Label 663: @30785
12593      GIM_Try, /*On fail goto*//*Label 664*/ 30843, // Rule ID 436 //
12594        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12595        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd16,
12596        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12597        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12598        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12599        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12600        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12602        // (intrinsic_wo_chain:{ *:[i32] } 1135:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12603        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD16,
12604        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12605        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12606        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12607        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12608        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12609        GIR_EraseFromParent, /*InsnID*/0,
12610        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12611        // GIR_Coverage, 436,
12612        GIR_Done,
12613      // Label 664: @30843
12614      GIM_Try, /*On fail goto*//*Label 665*/ 30901, // Rule ID 437 //
12615        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12616        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd8,
12617        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12618        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12619        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12620        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12621        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12623        // (intrinsic_wo_chain:{ *:[i32] } 1136:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12624        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD8,
12625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12628        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12629        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12630        GIR_EraseFromParent, /*InsnID*/0,
12631        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12632        // GIR_Coverage, 437,
12633        GIR_Done,
12634      // Label 665: @30901
12635      GIM_Try, /*On fail goto*//*Label 666*/ 30959, // Rule ID 438 //
12636        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12637        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qasx,
12638        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12639        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12640        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12641        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12642        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12644        // (intrinsic_wo_chain:{ *:[i32] } 1137:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12645        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QASX,
12646        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12647        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12648        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12649        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12650        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12651        GIR_EraseFromParent, /*InsnID*/0,
12652        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12653        // GIR_Coverage, 438,
12654        GIR_Done,
12655      // Label 666: @30959
12656      GIM_Try, /*On fail goto*//*Label 667*/ 31017, // Rule ID 439 //
12657        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12658        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub8,
12659        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12660        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12661        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12662        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12663        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12664        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12665        // (intrinsic_wo_chain:{ *:[i32] } 1208:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12666        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB8,
12667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12668        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12669        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12670        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12671        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12672        GIR_EraseFromParent, /*InsnID*/0,
12673        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12674        // GIR_Coverage, 439,
12675        GIR_Done,
12676      // Label 667: @31017
12677      GIM_Try, /*On fail goto*//*Label 668*/ 31075, // Rule ID 440 //
12678        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12679        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsax,
12680        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12681        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12682        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12683        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12684        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12686        // (intrinsic_wo_chain:{ *:[i32] } 1138:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12687        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSAX,
12688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12691        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12692        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12693        GIR_EraseFromParent, /*InsnID*/0,
12694        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12695        // GIR_Coverage, 440,
12696        GIR_Done,
12697      // Label 668: @31075
12698      GIM_Try, /*On fail goto*//*Label 669*/ 31133, // Rule ID 441 //
12699        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12700        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub16,
12701        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12702        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12703        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12705        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12707        // (intrinsic_wo_chain:{ *:[i32] } 1140:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12708        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB16,
12709        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12710        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12712        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12713        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12714        GIR_EraseFromParent, /*InsnID*/0,
12715        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12716        // GIR_Coverage, 441,
12717        GIR_Done,
12718      // Label 669: @31133
12719      GIM_Try, /*On fail goto*//*Label 670*/ 31191, // Rule ID 442 //
12720        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12721        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub8,
12722        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12723        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12724        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12728        // (intrinsic_wo_chain:{ *:[i32] } 1141:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12729        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB8,
12730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12733        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12734        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12735        GIR_EraseFromParent, /*InsnID*/0,
12736        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12737        // GIR_Coverage, 442,
12738        GIR_Done,
12739      // Label 670: @31191
12740      GIM_Try, /*On fail goto*//*Label 671*/ 31249, // Rule ID 443 //
12741        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12742        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd16,
12743        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12744        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12745        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12749        // (intrinsic_wo_chain:{ *:[i32] } 1203:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12750        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD16,
12751        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12754        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12755        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12756        GIR_EraseFromParent, /*InsnID*/0,
12757        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12758        // GIR_Coverage, 443,
12759        GIR_Done,
12760      // Label 671: @31249
12761      GIM_Try, /*On fail goto*//*Label 672*/ 31307, // Rule ID 444 //
12762        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12763        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqadd8,
12764        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12765        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12766        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12767        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12768        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12770        // (intrinsic_wo_chain:{ *:[i32] } 1204:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12771        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQADD8,
12772        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12773        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12775        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12776        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12777        GIR_EraseFromParent, /*InsnID*/0,
12778        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12779        // GIR_Coverage, 444,
12780        GIR_Done,
12781      // Label 672: @31307
12782      GIM_Try, /*On fail goto*//*Label 673*/ 31365, // Rule ID 445 //
12783        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12784        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqasx,
12785        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12786        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12787        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12788        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12789        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12790        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12791        // (intrinsic_wo_chain:{ *:[i32] } 1205:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12792        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQASX,
12793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12794        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12796        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12797        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12798        GIR_EraseFromParent, /*InsnID*/0,
12799        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12800        // GIR_Coverage, 445,
12801        GIR_Done,
12802      // Label 673: @31365
12803      GIM_Try, /*On fail goto*//*Label 674*/ 31423, // Rule ID 446 //
12804        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12805        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsax,
12806        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12807        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12808        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12809        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12810        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12812        // (intrinsic_wo_chain:{ *:[i32] } 1206:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12813        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSAX,
12814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12817        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12818        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12819        GIR_EraseFromParent, /*InsnID*/0,
12820        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12821        // GIR_Coverage, 446,
12822        GIR_Done,
12823      // Label 674: @31423
12824      GIM_Try, /*On fail goto*//*Label 675*/ 31481, // Rule ID 447 //
12825        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12826        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uqsub16,
12827        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12828        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12829        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12830        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12831        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12833        // (intrinsic_wo_chain:{ *:[i32] } 1207:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12834        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UQSUB16,
12835        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12836        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12838        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12839        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12840        GIR_EraseFromParent, /*InsnID*/0,
12841        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12842        // GIR_Coverage, 447,
12843        GIR_Done,
12844      // Label 675: @31481
12845      GIM_Try, /*On fail goto*//*Label 676*/ 31539, // Rule ID 460 //
12846        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12847        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shasx,
12848        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12849        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12850        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12851        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12852        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12854        // (intrinsic_wo_chain:{ *:[i32] } 1149:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12855        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHASX,
12856        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12857        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12859        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12860        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12861        GIR_EraseFromParent, /*InsnID*/0,
12862        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12863        // GIR_Coverage, 460,
12864        GIR_Done,
12865      // Label 676: @31539
12866      GIM_Try, /*On fail goto*//*Label 677*/ 31597, // Rule ID 461 //
12867        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12868        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd16,
12869        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12870        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12871        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12872        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12875        // (intrinsic_wo_chain:{ *:[i32] } 1147:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12876        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD16,
12877        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12878        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12880        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12881        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12882        GIR_EraseFromParent, /*InsnID*/0,
12883        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12884        // GIR_Coverage, 461,
12885        GIR_Done,
12886      // Label 677: @31597
12887      GIM_Try, /*On fail goto*//*Label 678*/ 31655, // Rule ID 462 //
12888        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12889        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shadd8,
12890        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12891        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12892        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12893        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12894        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12896        // (intrinsic_wo_chain:{ *:[i32] } 1148:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12897        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHADD8,
12898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12901        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12902        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12903        GIR_EraseFromParent, /*InsnID*/0,
12904        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12905        // GIR_Coverage, 462,
12906        GIR_Done,
12907      // Label 678: @31655
12908      GIM_Try, /*On fail goto*//*Label 679*/ 31713, // Rule ID 463 //
12909        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12910        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsax,
12911        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12912        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12913        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12917        // (intrinsic_wo_chain:{ *:[i32] } 1150:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12918        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSAX,
12919        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12922        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12923        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12924        GIR_EraseFromParent, /*InsnID*/0,
12925        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12926        // GIR_Coverage, 463,
12927        GIR_Done,
12928      // Label 679: @31713
12929      GIM_Try, /*On fail goto*//*Label 680*/ 31771, // Rule ID 464 //
12930        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12931        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub16,
12932        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12933        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12934        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12938        // (intrinsic_wo_chain:{ *:[i32] } 1151:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12939        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB16,
12940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12943        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12944        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12945        GIR_EraseFromParent, /*InsnID*/0,
12946        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12947        // GIR_Coverage, 464,
12948        GIR_Done,
12949      // Label 680: @31771
12950      GIM_Try, /*On fail goto*//*Label 681*/ 31829, // Rule ID 465 //
12951        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12952        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_shsub8,
12953        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12954        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12955        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12956        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12957        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12959        // (intrinsic_wo_chain:{ *:[i32] } 1152:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12960        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SHSUB8,
12961        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12962        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12964        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12965        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12966        GIR_EraseFromParent, /*InsnID*/0,
12967        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12968        // GIR_Coverage, 465,
12969        GIR_Done,
12970      // Label 681: @31829
12971      GIM_Try, /*On fail goto*//*Label 682*/ 31887, // Rule ID 466 //
12972        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12973        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhasx,
12974        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12975        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12976        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12978        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
12979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
12980        // (intrinsic_wo_chain:{ *:[i32] } 1198:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
12981        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHASX,
12982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
12983        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
12984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
12985        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
12986        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
12987        GIR_EraseFromParent, /*InsnID*/0,
12988        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
12989        // GIR_Coverage, 466,
12990        GIR_Done,
12991      // Label 682: @31887
12992      GIM_Try, /*On fail goto*//*Label 683*/ 31945, // Rule ID 467 //
12993        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
12994        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd16,
12995        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
12996        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
12997        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
12998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
12999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13001        // (intrinsic_wo_chain:{ *:[i32] } 1196:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13002        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD16,
13003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13006        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13007        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13008        GIR_EraseFromParent, /*InsnID*/0,
13009        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13010        // GIR_Coverage, 467,
13011        GIR_Done,
13012      // Label 683: @31945
13013      GIM_Try, /*On fail goto*//*Label 684*/ 32003, // Rule ID 468 //
13014        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13015        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhadd8,
13016        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13017        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13018        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13022        // (intrinsic_wo_chain:{ *:[i32] } 1197:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13023        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHADD8,
13024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13027        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13028        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13029        GIR_EraseFromParent, /*InsnID*/0,
13030        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13031        // GIR_Coverage, 468,
13032        GIR_Done,
13033      // Label 684: @32003
13034      GIM_Try, /*On fail goto*//*Label 685*/ 32061, // Rule ID 469 //
13035        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13036        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsax,
13037        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13038        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13039        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13043        // (intrinsic_wo_chain:{ *:[i32] } 1199:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13044        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSAX,
13045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13048        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13049        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13050        GIR_EraseFromParent, /*InsnID*/0,
13051        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13052        // GIR_Coverage, 469,
13053        GIR_Done,
13054      // Label 685: @32061
13055      GIM_Try, /*On fail goto*//*Label 686*/ 32119, // Rule ID 470 //
13056        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13057        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub16,
13058        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13059        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13060        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13064        // (intrinsic_wo_chain:{ *:[i32] } 1200:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13065        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB16,
13066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13069        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13070        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13071        GIR_EraseFromParent, /*InsnID*/0,
13072        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13073        // GIR_Coverage, 470,
13074        GIR_Done,
13075      // Label 686: @32119
13076      GIM_Try, /*On fail goto*//*Label 687*/ 32177, // Rule ID 471 //
13077        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13078        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uhsub8,
13079        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13080        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13081        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13085        // (intrinsic_wo_chain:{ *:[i32] } 1201:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13086        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UHSUB8,
13087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13090        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13091        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13092        GIR_EraseFromParent, /*InsnID*/0,
13093        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13094        // GIR_Coverage, 471,
13095        GIR_Done,
13096      // Label 687: @32177
13097      GIM_Try, /*On fail goto*//*Label 688*/ 32235, // Rule ID 472 //
13098        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13099        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usad8,
13100        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13101        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13102        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13104        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13105        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13106        // (intrinsic_wo_chain:{ *:[i32] } 1209:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13107        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAD8,
13108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13111        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13112        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13113        GIR_EraseFromParent, /*InsnID*/0,
13114        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13115        // GIR_Coverage, 472,
13116        GIR_Done,
13117      // Label 688: @32235
13118      GIM_Try, /*On fail goto*//*Label 689*/ 32293, // Rule ID 528 //
13119        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13120        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad,
13121        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13122        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13123        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13127        // (intrinsic_wo_chain:{ *:[i32] } 1167:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13128        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUAD,
13129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13132        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13133        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13134        GIR_EraseFromParent, /*InsnID*/0,
13135        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13136        // GIR_Coverage, 528,
13137        GIR_Done,
13138      // Label 689: @32293
13139      GIM_Try, /*On fail goto*//*Label 690*/ 32351, // Rule ID 529 //
13140        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13141        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx,
13142        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13143        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13144        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13148        // (intrinsic_wo_chain:{ *:[i32] } 1168:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13149        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUADX,
13150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13153        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13154        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13155        GIR_EraseFromParent, /*InsnID*/0,
13156        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13157        // GIR_Coverage, 529,
13158        GIR_Done,
13159      // Label 690: @32351
13160      GIM_Try, /*On fail goto*//*Label 691*/ 32409, // Rule ID 530 //
13161        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13162        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd,
13163        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13164        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13165        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13168        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13169        // (intrinsic_wo_chain:{ *:[i32] } 1175:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13170        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSD,
13171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13174        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13175        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13176        GIR_EraseFromParent, /*InsnID*/0,
13177        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13178        // GIR_Coverage, 530,
13179        GIR_Done,
13180      // Label 691: @32409
13181      GIM_Try, /*On fail goto*//*Label 692*/ 32467, // Rule ID 531 //
13182        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
13183        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx,
13184        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13185        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13186        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13190        // (intrinsic_wo_chain:{ *:[i32] } 1176:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13191        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMUSDX,
13192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13195        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13196        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13197        GIR_EraseFromParent, /*InsnID*/0,
13198        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13199        // GIR_Coverage, 531,
13200        GIR_Done,
13201      // Label 692: @32467
13202      GIM_Try, /*On fail goto*//*Label 693*/ 32519, // Rule ID 545 //
13203        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
13204        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32b,
13205        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13206        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13207        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13211        // (intrinsic_wo_chain:{ *:[i32] } 972:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13212        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32B,
13213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13216        GIR_EraseFromParent, /*InsnID*/0,
13217        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13218        // GIR_Coverage, 545,
13219        GIR_Done,
13220      // Label 693: @32519
13221      GIM_Try, /*On fail goto*//*Label 694*/ 32571, // Rule ID 546 //
13222        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
13223        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cb,
13224        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13225        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13226        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13230        // (intrinsic_wo_chain:{ *:[i32] } 973:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13231        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CB,
13232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13235        GIR_EraseFromParent, /*InsnID*/0,
13236        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13237        // GIR_Coverage, 546,
13238        GIR_Done,
13239      // Label 694: @32571
13240      GIM_Try, /*On fail goto*//*Label 695*/ 32623, // Rule ID 547 //
13241        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
13242        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32h,
13243        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13244        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13245        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13249        // (intrinsic_wo_chain:{ *:[i32] } 976:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13250        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32H,
13251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13254        GIR_EraseFromParent, /*InsnID*/0,
13255        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13256        // GIR_Coverage, 547,
13257        GIR_Done,
13258      // Label 695: @32623
13259      GIM_Try, /*On fail goto*//*Label 696*/ 32675, // Rule ID 548 //
13260        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
13261        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32ch,
13262        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13263        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13264        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13265        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13266        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13268        // (intrinsic_wo_chain:{ *:[i32] } 974:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13269        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CH,
13270        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13271        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13273        GIR_EraseFromParent, /*InsnID*/0,
13274        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13275        // GIR_Coverage, 548,
13276        GIR_Done,
13277      // Label 696: @32675
13278      GIM_Try, /*On fail goto*//*Label 697*/ 32727, // Rule ID 549 //
13279        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
13280        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32w,
13281        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13282        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13283        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13286        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13287        // (intrinsic_wo_chain:{ *:[i32] } 977:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13288        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32W,
13289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13291        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13292        GIR_EraseFromParent, /*InsnID*/0,
13293        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13294        // GIR_Coverage, 549,
13295        GIR_Done,
13296      // Label 697: @32727
13297      GIM_Try, /*On fail goto*//*Label 698*/ 32779, // Rule ID 550 //
13298        GIM_CheckFeatures, GIFBS_HasCRC_HasV8_IsThumb2,
13299        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_crc32cw,
13300        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
13301        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
13302        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
13303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
13304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
13305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
13306        // (intrinsic_wo_chain:{ *:[i32] } 975:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
13307        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CRC32CW,
13308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
13309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
13310        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
13311        GIR_EraseFromParent, /*InsnID*/0,
13312        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13313        // GIR_Coverage, 550,
13314        GIR_Done,
13315      // Label 698: @32779
13316      GIM_Try, /*On fail goto*//*Label 699*/ 32837, // Rule ID 778 //
13317        GIM_CheckFeatures, GIFBS_HasNEON,
13318        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
13319        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13320        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13321        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
13322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13324        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13325        // (intrinsic_wo_chain:{ *:[v4i16] } 1037:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
13326        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i16,
13327        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13330        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13331        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13332        GIR_EraseFromParent, /*InsnID*/0,
13333        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13334        // GIR_Coverage, 778,
13335        GIR_Done,
13336      // Label 699: @32837
13337      GIM_Try, /*On fail goto*//*Label 700*/ 32895, // Rule ID 779 //
13338        GIM_CheckFeatures, GIFBS_HasNEON,
13339        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
13340        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13341        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13342        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
13343        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13344        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13345        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13346        // (intrinsic_wo_chain:{ *:[v2i32] } 1037:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
13347        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv2i32,
13348        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13351        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13352        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13353        GIR_EraseFromParent, /*InsnID*/0,
13354        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13355        // GIR_Coverage, 779,
13356        GIR_Done,
13357      // Label 700: @32895
13358      GIM_Try, /*On fail goto*//*Label 701*/ 32953, // Rule ID 780 //
13359        GIM_CheckFeatures, GIFBS_HasNEON,
13360        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
13361        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13362        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13363        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
13364        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13367        // (intrinsic_wo_chain:{ *:[v8i16] } 1037:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
13368        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i16,
13369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13372        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13373        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13374        GIR_EraseFromParent, /*InsnID*/0,
13375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13376        // GIR_Coverage, 780,
13377        GIR_Done,
13378      // Label 701: @32953
13379      GIM_Try, /*On fail goto*//*Label 702*/ 33011, // Rule ID 781 //
13380        GIM_CheckFeatures, GIFBS_HasNEON,
13381        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
13382        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13383        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13384        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
13385        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13388        // (intrinsic_wo_chain:{ *:[v4i32] } 1037:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
13389        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv4i32,
13390        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13393        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13394        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13395        GIR_EraseFromParent, /*InsnID*/0,
13396        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13397        // GIR_Coverage, 781,
13398        GIR_Done,
13399      // Label 702: @33011
13400      GIM_Try, /*On fail goto*//*Label 703*/ 33069, // Rule ID 782 //
13401        GIM_CheckFeatures, GIFBS_HasNEON,
13402        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
13403        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
13404        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
13405        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
13406        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13409        // (intrinsic_wo_chain:{ *:[v8i8] } 1037:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
13410        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv8i8,
13411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13414        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13415        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13416        GIR_EraseFromParent, /*InsnID*/0,
13417        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13418        // GIR_Coverage, 782,
13419        GIR_Done,
13420      // Label 703: @33069
13421      GIM_Try, /*On fail goto*//*Label 704*/ 33127, // Rule ID 783 //
13422        GIM_CheckFeatures, GIFBS_HasNEON,
13423        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhadds,
13424        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
13425        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13426        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
13427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13430        // (intrinsic_wo_chain:{ *:[v16i8] } 1037:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
13431        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDsv16i8,
13432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13435        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13436        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13437        GIR_EraseFromParent, /*InsnID*/0,
13438        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13439        // GIR_Coverage, 783,
13440        GIR_Done,
13441      // Label 704: @33127
13442      GIM_Try, /*On fail goto*//*Label 705*/ 33185, // Rule ID 784 //
13443        GIM_CheckFeatures, GIFBS_HasNEON,
13444        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
13445        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13446        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13447        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
13448        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13451        // (intrinsic_wo_chain:{ *:[v4i16] } 1038:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
13452        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i16,
13453        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13456        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13457        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13458        GIR_EraseFromParent, /*InsnID*/0,
13459        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13460        // GIR_Coverage, 784,
13461        GIR_Done,
13462      // Label 705: @33185
13463      GIM_Try, /*On fail goto*//*Label 706*/ 33243, // Rule ID 785 //
13464        GIM_CheckFeatures, GIFBS_HasNEON,
13465        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
13466        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13467        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13468        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
13469        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13472        // (intrinsic_wo_chain:{ *:[v2i32] } 1038:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
13473        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv2i32,
13474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13476        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13477        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13478        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13479        GIR_EraseFromParent, /*InsnID*/0,
13480        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13481        // GIR_Coverage, 785,
13482        GIR_Done,
13483      // Label 706: @33243
13484      GIM_Try, /*On fail goto*//*Label 707*/ 33301, // Rule ID 786 //
13485        GIM_CheckFeatures, GIFBS_HasNEON,
13486        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
13487        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13488        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13489        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
13490        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13493        // (intrinsic_wo_chain:{ *:[v8i16] } 1038:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
13494        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i16,
13495        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13498        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13499        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13500        GIR_EraseFromParent, /*InsnID*/0,
13501        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13502        // GIR_Coverage, 786,
13503        GIR_Done,
13504      // Label 707: @33301
13505      GIM_Try, /*On fail goto*//*Label 708*/ 33359, // Rule ID 787 //
13506        GIM_CheckFeatures, GIFBS_HasNEON,
13507        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
13508        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13509        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13510        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
13511        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13514        // (intrinsic_wo_chain:{ *:[v4i32] } 1038:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
13515        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv4i32,
13516        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13519        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13520        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13521        GIR_EraseFromParent, /*InsnID*/0,
13522        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13523        // GIR_Coverage, 787,
13524        GIR_Done,
13525      // Label 708: @33359
13526      GIM_Try, /*On fail goto*//*Label 709*/ 33417, // Rule ID 788 //
13527        GIM_CheckFeatures, GIFBS_HasNEON,
13528        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
13529        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
13530        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
13531        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
13532        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13535        // (intrinsic_wo_chain:{ *:[v8i8] } 1038:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
13536        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv8i8,
13537        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13540        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13541        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13542        GIR_EraseFromParent, /*InsnID*/0,
13543        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13544        // GIR_Coverage, 788,
13545        GIR_Done,
13546      // Label 709: @33417
13547      GIM_Try, /*On fail goto*//*Label 710*/ 33475, // Rule ID 789 //
13548        GIM_CheckFeatures, GIFBS_HasNEON,
13549        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhaddu,
13550        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
13551        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13552        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
13553        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13556        // (intrinsic_wo_chain:{ *:[v16i8] } 1038:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
13557        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHADDuv16i8,
13558        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13561        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13562        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13563        GIR_EraseFromParent, /*InsnID*/0,
13564        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13565        // GIR_Coverage, 789,
13566        GIR_Done,
13567      // Label 710: @33475
13568      GIM_Try, /*On fail goto*//*Label 711*/ 33533, // Rule ID 790 //
13569        GIM_CheckFeatures, GIFBS_HasNEON,
13570        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
13571        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13572        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13573        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
13574        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13577        // (intrinsic_wo_chain:{ *:[v4i16] } 1099:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
13578        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i16,
13579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13582        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13583        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13584        GIR_EraseFromParent, /*InsnID*/0,
13585        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13586        // GIR_Coverage, 790,
13587        GIR_Done,
13588      // Label 711: @33533
13589      GIM_Try, /*On fail goto*//*Label 712*/ 33591, // Rule ID 791 //
13590        GIM_CheckFeatures, GIFBS_HasNEON,
13591        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
13592        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13593        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13594        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
13595        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13598        // (intrinsic_wo_chain:{ *:[v2i32] } 1099:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
13599        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv2i32,
13600        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13603        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13604        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13605        GIR_EraseFromParent, /*InsnID*/0,
13606        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13607        // GIR_Coverage, 791,
13608        GIR_Done,
13609      // Label 712: @33591
13610      GIM_Try, /*On fail goto*//*Label 713*/ 33649, // Rule ID 792 //
13611        GIM_CheckFeatures, GIFBS_HasNEON,
13612        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
13613        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13614        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13615        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
13616        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13619        // (intrinsic_wo_chain:{ *:[v8i16] } 1099:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
13620        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i16,
13621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13624        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13625        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13626        GIR_EraseFromParent, /*InsnID*/0,
13627        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13628        // GIR_Coverage, 792,
13629        GIR_Done,
13630      // Label 713: @33649
13631      GIM_Try, /*On fail goto*//*Label 714*/ 33707, // Rule ID 793 //
13632        GIM_CheckFeatures, GIFBS_HasNEON,
13633        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
13634        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13635        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13636        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
13637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13640        // (intrinsic_wo_chain:{ *:[v4i32] } 1099:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
13641        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv4i32,
13642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13645        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13646        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13647        GIR_EraseFromParent, /*InsnID*/0,
13648        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13649        // GIR_Coverage, 793,
13650        GIR_Done,
13651      // Label 714: @33707
13652      GIM_Try, /*On fail goto*//*Label 715*/ 33765, // Rule ID 794 //
13653        GIM_CheckFeatures, GIFBS_HasNEON,
13654        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
13655        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
13656        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
13657        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
13658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13661        // (intrinsic_wo_chain:{ *:[v8i8] } 1099:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
13662        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv8i8,
13663        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13666        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13667        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13668        GIR_EraseFromParent, /*InsnID*/0,
13669        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13670        // GIR_Coverage, 794,
13671        GIR_Done,
13672      // Label 715: @33765
13673      GIM_Try, /*On fail goto*//*Label 716*/ 33823, // Rule ID 795 //
13674        GIM_CheckFeatures, GIFBS_HasNEON,
13675        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhadds,
13676        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
13677        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13678        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
13679        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13682        // (intrinsic_wo_chain:{ *:[v16i8] } 1099:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
13683        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDsv16i8,
13684        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13687        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13688        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13689        GIR_EraseFromParent, /*InsnID*/0,
13690        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13691        // GIR_Coverage, 795,
13692        GIR_Done,
13693      // Label 716: @33823
13694      GIM_Try, /*On fail goto*//*Label 717*/ 33881, // Rule ID 796 //
13695        GIM_CheckFeatures, GIFBS_HasNEON,
13696        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
13697        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13698        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13699        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
13700        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13703        // (intrinsic_wo_chain:{ *:[v4i16] } 1100:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
13704        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i16,
13705        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13708        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13709        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13710        GIR_EraseFromParent, /*InsnID*/0,
13711        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13712        // GIR_Coverage, 796,
13713        GIR_Done,
13714      // Label 717: @33881
13715      GIM_Try, /*On fail goto*//*Label 718*/ 33939, // Rule ID 797 //
13716        GIM_CheckFeatures, GIFBS_HasNEON,
13717        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
13718        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13719        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13720        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
13721        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13724        // (intrinsic_wo_chain:{ *:[v2i32] } 1100:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
13725        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv2i32,
13726        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13729        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13730        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13731        GIR_EraseFromParent, /*InsnID*/0,
13732        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13733        // GIR_Coverage, 797,
13734        GIR_Done,
13735      // Label 718: @33939
13736      GIM_Try, /*On fail goto*//*Label 719*/ 33997, // Rule ID 798 //
13737        GIM_CheckFeatures, GIFBS_HasNEON,
13738        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
13739        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13740        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13741        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
13742        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13745        // (intrinsic_wo_chain:{ *:[v8i16] } 1100:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
13746        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i16,
13747        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13748        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13750        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13751        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13752        GIR_EraseFromParent, /*InsnID*/0,
13753        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13754        // GIR_Coverage, 798,
13755        GIR_Done,
13756      // Label 719: @33997
13757      GIM_Try, /*On fail goto*//*Label 720*/ 34055, // Rule ID 799 //
13758        GIM_CheckFeatures, GIFBS_HasNEON,
13759        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
13760        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13761        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13762        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
13763        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13766        // (intrinsic_wo_chain:{ *:[v4i32] } 1100:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
13767        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv4i32,
13768        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13771        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13772        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13773        GIR_EraseFromParent, /*InsnID*/0,
13774        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13775        // GIR_Coverage, 799,
13776        GIR_Done,
13777      // Label 720: @34055
13778      GIM_Try, /*On fail goto*//*Label 721*/ 34113, // Rule ID 800 //
13779        GIM_CheckFeatures, GIFBS_HasNEON,
13780        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
13781        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
13782        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
13783        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
13784        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13787        // (intrinsic_wo_chain:{ *:[v8i8] } 1100:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
13788        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv8i8,
13789        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13792        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13793        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13794        GIR_EraseFromParent, /*InsnID*/0,
13795        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13796        // GIR_Coverage, 800,
13797        GIR_Done,
13798      // Label 721: @34113
13799      GIM_Try, /*On fail goto*//*Label 722*/ 34171, // Rule ID 801 //
13800        GIM_CheckFeatures, GIFBS_HasNEON,
13801        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrhaddu,
13802        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
13803        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13804        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
13805        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13808        // (intrinsic_wo_chain:{ *:[v16i8] } 1100:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
13809        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRHADDuv16i8,
13810        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13813        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13814        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13815        GIR_EraseFromParent, /*InsnID*/0,
13816        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13817        // GIR_Coverage, 801,
13818        GIR_Done,
13819      // Label 722: @34171
13820      GIM_Try, /*On fail goto*//*Label 723*/ 34229, // Rule ID 802 //
13821        GIM_CheckFeatures, GIFBS_HasNEON,
13822        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
13823        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13824        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13825        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
13826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13829        // (intrinsic_wo_chain:{ *:[v4i16] } 1074:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
13830        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i16,
13831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13834        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13835        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13836        GIR_EraseFromParent, /*InsnID*/0,
13837        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13838        // GIR_Coverage, 802,
13839        GIR_Done,
13840      // Label 723: @34229
13841      GIM_Try, /*On fail goto*//*Label 724*/ 34287, // Rule ID 803 //
13842        GIM_CheckFeatures, GIFBS_HasNEON,
13843        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
13844        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
13845        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
13846        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
13847        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13850        // (intrinsic_wo_chain:{ *:[v2i32] } 1074:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
13851        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i32,
13852        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13855        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13856        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13857        GIR_EraseFromParent, /*InsnID*/0,
13858        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13859        // GIR_Coverage, 803,
13860        GIR_Done,
13861      // Label 724: @34287
13862      GIM_Try, /*On fail goto*//*Label 725*/ 34345, // Rule ID 804 //
13863        GIM_CheckFeatures, GIFBS_HasNEON,
13864        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
13865        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
13866        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
13867        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
13868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13871        // (intrinsic_wo_chain:{ *:[v8i16] } 1074:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
13872        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i16,
13873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13875        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13876        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13877        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13878        GIR_EraseFromParent, /*InsnID*/0,
13879        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13880        // GIR_Coverage, 804,
13881        GIR_Done,
13882      // Label 725: @34345
13883      GIM_Try, /*On fail goto*//*Label 726*/ 34403, // Rule ID 805 //
13884        GIM_CheckFeatures, GIFBS_HasNEON,
13885        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
13886        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
13887        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
13888        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
13889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13892        // (intrinsic_wo_chain:{ *:[v4i32] } 1074:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
13893        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv4i32,
13894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13897        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13898        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13899        GIR_EraseFromParent, /*InsnID*/0,
13900        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13901        // GIR_Coverage, 805,
13902        GIR_Done,
13903      // Label 726: @34403
13904      GIM_Try, /*On fail goto*//*Label 727*/ 34461, // Rule ID 806 //
13905        GIM_CheckFeatures, GIFBS_HasNEON,
13906        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
13907        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
13908        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
13909        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
13910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13913        // (intrinsic_wo_chain:{ *:[v8i8] } 1074:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
13914        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv8i8,
13915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13918        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13919        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13920        GIR_EraseFromParent, /*InsnID*/0,
13921        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13922        // GIR_Coverage, 806,
13923        GIR_Done,
13924      // Label 727: @34461
13925      GIM_Try, /*On fail goto*//*Label 728*/ 34519, // Rule ID 807 //
13926        GIM_CheckFeatures, GIFBS_HasNEON,
13927        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
13928        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
13929        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
13930        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
13931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13934        // (intrinsic_wo_chain:{ *:[v16i8] } 1074:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
13935        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv16i8,
13936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13939        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13940        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13941        GIR_EraseFromParent, /*InsnID*/0,
13942        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13943        // GIR_Coverage, 807,
13944        GIR_Done,
13945      // Label 728: @34519
13946      GIM_Try, /*On fail goto*//*Label 729*/ 34577, // Rule ID 808 //
13947        GIM_CheckFeatures, GIFBS_HasNEON,
13948        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
13949        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
13950        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
13951        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
13952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13955        // (intrinsic_wo_chain:{ *:[v1i64] } 1074:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
13956        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv1i64,
13957        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13960        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13961        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13962        GIR_EraseFromParent, /*InsnID*/0,
13963        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13964        // GIR_Coverage, 808,
13965        GIR_Done,
13966      // Label 729: @34577
13967      GIM_Try, /*On fail goto*//*Label 730*/ 34635, // Rule ID 809 //
13968        GIM_CheckFeatures, GIFBS_HasNEON,
13969        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqadds,
13970        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
13971        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
13972        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
13973        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
13974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
13975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
13976        // (intrinsic_wo_chain:{ *:[v2i64] } 1074:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
13977        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDsv2i64,
13978        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
13979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
13980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
13981        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
13982        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
13983        GIR_EraseFromParent, /*InsnID*/0,
13984        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
13985        // GIR_Coverage, 809,
13986        GIR_Done,
13987      // Label 730: @34635
13988      GIM_Try, /*On fail goto*//*Label 731*/ 34693, // Rule ID 810 //
13989        GIM_CheckFeatures, GIFBS_HasNEON,
13990        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
13991        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
13992        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
13993        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
13994        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
13995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
13996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
13997        // (intrinsic_wo_chain:{ *:[v4i16] } 1075:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
13998        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i16,
13999        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14002        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14003        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14004        GIR_EraseFromParent, /*InsnID*/0,
14005        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14006        // GIR_Coverage, 810,
14007        GIR_Done,
14008      // Label 731: @34693
14009      GIM_Try, /*On fail goto*//*Label 732*/ 34751, // Rule ID 811 //
14010        GIM_CheckFeatures, GIFBS_HasNEON,
14011        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
14012        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14013        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14014        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
14015        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14018        // (intrinsic_wo_chain:{ *:[v2i32] } 1075:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
14019        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i32,
14020        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14023        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14024        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14025        GIR_EraseFromParent, /*InsnID*/0,
14026        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14027        // GIR_Coverage, 811,
14028        GIR_Done,
14029      // Label 732: @34751
14030      GIM_Try, /*On fail goto*//*Label 733*/ 34809, // Rule ID 812 //
14031        GIM_CheckFeatures, GIFBS_HasNEON,
14032        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
14033        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14034        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14035        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
14036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14039        // (intrinsic_wo_chain:{ *:[v8i16] } 1075:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
14040        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i16,
14041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14044        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14045        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14046        GIR_EraseFromParent, /*InsnID*/0,
14047        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14048        // GIR_Coverage, 812,
14049        GIR_Done,
14050      // Label 733: @34809
14051      GIM_Try, /*On fail goto*//*Label 734*/ 34867, // Rule ID 813 //
14052        GIM_CheckFeatures, GIFBS_HasNEON,
14053        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
14054        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14055        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14056        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
14057        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14060        // (intrinsic_wo_chain:{ *:[v4i32] } 1075:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
14061        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv4i32,
14062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14065        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14066        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14067        GIR_EraseFromParent, /*InsnID*/0,
14068        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14069        // GIR_Coverage, 813,
14070        GIR_Done,
14071      // Label 734: @34867
14072      GIM_Try, /*On fail goto*//*Label 735*/ 34925, // Rule ID 814 //
14073        GIM_CheckFeatures, GIFBS_HasNEON,
14074        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
14075        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14076        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14077        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
14078        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14081        // (intrinsic_wo_chain:{ *:[v8i8] } 1075:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
14082        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv8i8,
14083        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14086        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14087        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14088        GIR_EraseFromParent, /*InsnID*/0,
14089        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14090        // GIR_Coverage, 814,
14091        GIR_Done,
14092      // Label 735: @34925
14093      GIM_Try, /*On fail goto*//*Label 736*/ 34983, // Rule ID 815 //
14094        GIM_CheckFeatures, GIFBS_HasNEON,
14095        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
14096        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14097        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14098        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
14099        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14102        // (intrinsic_wo_chain:{ *:[v16i8] } 1075:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
14103        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv16i8,
14104        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14107        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14108        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14109        GIR_EraseFromParent, /*InsnID*/0,
14110        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14111        // GIR_Coverage, 815,
14112        GIR_Done,
14113      // Label 736: @34983
14114      GIM_Try, /*On fail goto*//*Label 737*/ 35041, // Rule ID 816 //
14115        GIM_CheckFeatures, GIFBS_HasNEON,
14116        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
14117        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
14118        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14119        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
14120        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14123        // (intrinsic_wo_chain:{ *:[v1i64] } 1075:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
14124        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv1i64,
14125        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14128        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14129        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14130        GIR_EraseFromParent, /*InsnID*/0,
14131        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14132        // GIR_Coverage, 816,
14133        GIR_Done,
14134      // Label 737: @35041
14135      GIM_Try, /*On fail goto*//*Label 738*/ 35099, // Rule ID 817 //
14136        GIM_CheckFeatures, GIFBS_HasNEON,
14137        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqaddu,
14138        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
14139        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14140        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
14141        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14144        // (intrinsic_wo_chain:{ *:[v2i64] } 1075:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
14145        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQADDuv2i64,
14146        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14149        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14150        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14151        GIR_EraseFromParent, /*InsnID*/0,
14152        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14153        // GIR_Coverage, 817,
14154        GIR_Done,
14155      // Label 738: @35099
14156      GIM_Try, /*On fail goto*//*Label 739*/ 35157, // Rule ID 818 //
14157        GIM_CheckFeatures, GIFBS_HasNEON,
14158        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
14159        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14160        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14161        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
14162        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14165        // (intrinsic_wo_chain:{ *:[v8i8] } 1096:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
14166        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv8i8,
14167        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14170        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14171        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14172        GIR_EraseFromParent, /*InsnID*/0,
14173        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14174        // GIR_Coverage, 818,
14175        GIR_Done,
14176      // Label 739: @35157
14177      GIM_Try, /*On fail goto*//*Label 740*/ 35215, // Rule ID 819 //
14178        GIM_CheckFeatures, GIFBS_HasNEON,
14179        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
14180        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14181        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14182        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
14183        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14186        // (intrinsic_wo_chain:{ *:[v4i16] } 1096:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
14187        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv4i16,
14188        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14191        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14192        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14193        GIR_EraseFromParent, /*InsnID*/0,
14194        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14195        // GIR_Coverage, 819,
14196        GIR_Done,
14197      // Label 740: @35215
14198      GIM_Try, /*On fail goto*//*Label 741*/ 35273, // Rule ID 820 //
14199        GIM_CheckFeatures, GIFBS_HasNEON,
14200        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vraddhn,
14201        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14202        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14203        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
14204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14207        // (intrinsic_wo_chain:{ *:[v2i32] } 1096:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
14208        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRADDHNv2i32,
14209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14212        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14213        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14214        GIR_EraseFromParent, /*InsnID*/0,
14215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14216        // GIR_Coverage, 820,
14217        GIR_Done,
14218      // Label 741: @35273
14219      GIM_Try, /*On fail goto*//*Label 742*/ 35331, // Rule ID 827 //
14220        GIM_CheckFeatures, GIFBS_HasNEON,
14221        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
14222        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14223        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14224        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
14225        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14228        // (intrinsic_wo_chain:{ *:[v8i8] } 1063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
14229        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpd,
14230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14233        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14234        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14235        GIR_EraseFromParent, /*InsnID*/0,
14236        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14237        // GIR_Coverage, 827,
14238        GIR_Done,
14239      // Label 742: @35331
14240      GIM_Try, /*On fail goto*//*Label 743*/ 35389, // Rule ID 828 //
14241        GIM_CheckFeatures, GIFBS_HasNEON,
14242        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmulp,
14243        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14244        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14245        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
14246        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14249        // (intrinsic_wo_chain:{ *:[v16i8] } 1063:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
14250        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULpq,
14251        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14254        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14255        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14256        GIR_EraseFromParent, /*InsnID*/0,
14257        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14258        // GIR_Coverage, 828,
14259        GIR_Done,
14260      // Label 743: @35389
14261      GIM_Try, /*On fail goto*//*Label 744*/ 35447, // Rule ID 841 //
14262        GIM_CheckFeatures, GIFBS_HasNEON,
14263        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
14264        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14265        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14266        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
14267        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14270        // (intrinsic_wo_chain:{ *:[v4i16] } 1076:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
14271        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i16,
14272        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14275        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14276        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14277        GIR_EraseFromParent, /*InsnID*/0,
14278        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14279        // GIR_Coverage, 841,
14280        GIR_Done,
14281      // Label 744: @35447
14282      GIM_Try, /*On fail goto*//*Label 745*/ 35505, // Rule ID 842 //
14283        GIM_CheckFeatures, GIFBS_HasNEON,
14284        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
14285        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14286        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14287        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
14288        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14291        // (intrinsic_wo_chain:{ *:[v2i32] } 1076:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
14292        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv2i32,
14293        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14296        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14297        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14298        GIR_EraseFromParent, /*InsnID*/0,
14299        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14300        // GIR_Coverage, 842,
14301        GIR_Done,
14302      // Label 745: @35505
14303      GIM_Try, /*On fail goto*//*Label 746*/ 35563, // Rule ID 843 //
14304        GIM_CheckFeatures, GIFBS_HasNEON,
14305        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
14306        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14307        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14308        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
14309        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14311        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14312        // (intrinsic_wo_chain:{ *:[v8i16] } 1076:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
14313        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv8i16,
14314        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14317        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14318        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14319        GIR_EraseFromParent, /*InsnID*/0,
14320        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14321        // GIR_Coverage, 843,
14322        GIR_Done,
14323      // Label 746: @35563
14324      GIM_Try, /*On fail goto*//*Label 747*/ 35621, // Rule ID 844 //
14325        GIM_CheckFeatures, GIFBS_HasNEON,
14326        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmulh,
14327        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14328        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14329        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
14330        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14333        // (intrinsic_wo_chain:{ *:[v4i32] } 1076:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
14334        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULHv4i32,
14335        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14338        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14339        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14340        GIR_EraseFromParent, /*InsnID*/0,
14341        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14342        // GIR_Coverage, 844,
14343        GIR_Done,
14344      // Label 747: @35621
14345      GIM_Try, /*On fail goto*//*Label 748*/ 35679, // Rule ID 849 //
14346        GIM_CheckFeatures, GIFBS_HasNEON,
14347        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
14348        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14349        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14350        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
14351        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14354        // (intrinsic_wo_chain:{ *:[v4i16] } 1082:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
14355        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i16,
14356        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14359        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14360        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14361        GIR_EraseFromParent, /*InsnID*/0,
14362        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14363        // GIR_Coverage, 849,
14364        GIR_Done,
14365      // Label 748: @35679
14366      GIM_Try, /*On fail goto*//*Label 749*/ 35737, // Rule ID 850 //
14367        GIM_CheckFeatures, GIFBS_HasNEON,
14368        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
14369        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14370        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14371        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
14372        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14375        // (intrinsic_wo_chain:{ *:[v2i32] } 1082:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
14376        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv2i32,
14377        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14380        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14381        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14382        GIR_EraseFromParent, /*InsnID*/0,
14383        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14384        // GIR_Coverage, 850,
14385        GIR_Done,
14386      // Label 749: @35737
14387      GIM_Try, /*On fail goto*//*Label 750*/ 35795, // Rule ID 851 //
14388        GIM_CheckFeatures, GIFBS_HasNEON,
14389        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
14390        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14391        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14392        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
14393        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14395        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14396        // (intrinsic_wo_chain:{ *:[v8i16] } 1082:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
14397        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv8i16,
14398        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14401        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14402        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14403        GIR_EraseFromParent, /*InsnID*/0,
14404        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14405        // GIR_Coverage, 851,
14406        GIR_Done,
14407      // Label 750: @35795
14408      GIM_Try, /*On fail goto*//*Label 751*/ 35853, // Rule ID 852 //
14409        GIM_CheckFeatures, GIFBS_HasNEON,
14410        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrdmulh,
14411        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14412        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14413        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
14414        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14417        // (intrinsic_wo_chain:{ *:[v4i32] } 1082:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
14418        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRDMULHv4i32,
14419        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14422        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14423        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14424        GIR_EraseFromParent, /*InsnID*/0,
14425        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14426        // GIR_Coverage, 852,
14427        GIR_Done,
14428      // Label 751: @35853
14429      GIM_Try, /*On fail goto*//*Label 752*/ 35911, // Rule ID 863 //
14430        GIM_CheckFeatures, GIFBS_HasNEON,
14431        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
14432        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14433        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14434        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
14435        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14438        // (intrinsic_wo_chain:{ *:[v8i16] } 1060:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
14439        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp8,
14440        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14443        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14444        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14445        GIR_EraseFromParent, /*InsnID*/0,
14446        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14447        // GIR_Coverage, 863,
14448        GIR_Done,
14449      // Label 752: @35911
14450      GIM_Try, /*On fail goto*//*Label 753*/ 35963, // Rule ID 864 //
14451        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
14452        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vmullp,
14453        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
14454        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14455        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
14456        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14458        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14459        // (intrinsic_wo_chain:{ *:[v2i64] } 1060:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
14460        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULLp64,
14461        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14463        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14464        GIR_EraseFromParent, /*InsnID*/0,
14465        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14466        // GIR_Coverage, 864,
14467        GIR_Done,
14468      // Label 753: @35963
14469      GIM_Try, /*On fail goto*//*Label 754*/ 36021, // Rule ID 869 //
14470        GIM_CheckFeatures, GIFBS_HasNEON,
14471        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
14472        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14473        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14474        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
14475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14478        // (intrinsic_wo_chain:{ *:[v4i32] } 1077:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
14479        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv4i32,
14480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14483        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14484        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14485        GIR_EraseFromParent, /*InsnID*/0,
14486        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14487        // GIR_Coverage, 869,
14488        GIR_Done,
14489      // Label 754: @36021
14490      GIM_Try, /*On fail goto*//*Label 755*/ 36079, // Rule ID 870 //
14491        GIM_CheckFeatures, GIFBS_HasNEON,
14492        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqdmull,
14493        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
14494        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14495        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
14496        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14497        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14499        // (intrinsic_wo_chain:{ *:[v2i64] } 1077:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
14500        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQDMULLv2i64,
14501        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14502        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14503        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14504        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14505        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14506        GIR_EraseFromParent, /*InsnID*/0,
14507        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14508        // GIR_Coverage, 870,
14509        GIR_Done,
14510      // Label 755: @36079
14511      GIM_Try, /*On fail goto*//*Label 756*/ 36137, // Rule ID 965 //
14512        GIM_CheckFeatures, GIFBS_HasNEON,
14513        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
14514        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14515        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14516        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
14517        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14518        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14519        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14520        // (intrinsic_wo_chain:{ *:[v4i16] } 1039:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
14521        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i16,
14522        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14523        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14524        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14525        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14526        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14527        GIR_EraseFromParent, /*InsnID*/0,
14528        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14529        // GIR_Coverage, 965,
14530        GIR_Done,
14531      // Label 756: @36137
14532      GIM_Try, /*On fail goto*//*Label 757*/ 36195, // Rule ID 966 //
14533        GIM_CheckFeatures, GIFBS_HasNEON,
14534        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
14535        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14536        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14537        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
14538        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14539        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14540        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14541        // (intrinsic_wo_chain:{ *:[v2i32] } 1039:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
14542        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv2i32,
14543        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14544        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14545        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14546        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14547        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14548        GIR_EraseFromParent, /*InsnID*/0,
14549        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14550        // GIR_Coverage, 966,
14551        GIR_Done,
14552      // Label 757: @36195
14553      GIM_Try, /*On fail goto*//*Label 758*/ 36253, // Rule ID 967 //
14554        GIM_CheckFeatures, GIFBS_HasNEON,
14555        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
14556        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14557        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14558        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
14559        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14560        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14561        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14562        // (intrinsic_wo_chain:{ *:[v8i16] } 1039:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
14563        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i16,
14564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14565        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14566        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14567        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14568        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14569        GIR_EraseFromParent, /*InsnID*/0,
14570        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14571        // GIR_Coverage, 967,
14572        GIR_Done,
14573      // Label 758: @36253
14574      GIM_Try, /*On fail goto*//*Label 759*/ 36311, // Rule ID 968 //
14575        GIM_CheckFeatures, GIFBS_HasNEON,
14576        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
14577        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14578        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14579        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
14580        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14581        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14582        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14583        // (intrinsic_wo_chain:{ *:[v4i32] } 1039:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
14584        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv4i32,
14585        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14586        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14587        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14588        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14589        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14590        GIR_EraseFromParent, /*InsnID*/0,
14591        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14592        // GIR_Coverage, 968,
14593        GIR_Done,
14594      // Label 759: @36311
14595      GIM_Try, /*On fail goto*//*Label 760*/ 36369, // Rule ID 969 //
14596        GIM_CheckFeatures, GIFBS_HasNEON,
14597        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
14598        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14599        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14600        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
14601        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14602        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14603        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14604        // (intrinsic_wo_chain:{ *:[v8i8] } 1039:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
14605        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv8i8,
14606        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14607        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14608        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14609        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14610        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14611        GIR_EraseFromParent, /*InsnID*/0,
14612        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14613        // GIR_Coverage, 969,
14614        GIR_Done,
14615      // Label 760: @36369
14616      GIM_Try, /*On fail goto*//*Label 761*/ 36427, // Rule ID 970 //
14617        GIM_CheckFeatures, GIFBS_HasNEON,
14618        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubs,
14619        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14620        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14621        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
14622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14623        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14624        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14625        // (intrinsic_wo_chain:{ *:[v16i8] } 1039:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
14626        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBsv16i8,
14627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14628        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14629        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14630        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14631        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14632        GIR_EraseFromParent, /*InsnID*/0,
14633        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14634        // GIR_Coverage, 970,
14635        GIR_Done,
14636      // Label 761: @36427
14637      GIM_Try, /*On fail goto*//*Label 762*/ 36485, // Rule ID 971 //
14638        GIM_CheckFeatures, GIFBS_HasNEON,
14639        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
14640        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14641        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14642        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
14643        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14644        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14645        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14646        // (intrinsic_wo_chain:{ *:[v4i16] } 1040:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
14647        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i16,
14648        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14649        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14651        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14652        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14653        GIR_EraseFromParent, /*InsnID*/0,
14654        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14655        // GIR_Coverage, 971,
14656        GIR_Done,
14657      // Label 762: @36485
14658      GIM_Try, /*On fail goto*//*Label 763*/ 36543, // Rule ID 972 //
14659        GIM_CheckFeatures, GIFBS_HasNEON,
14660        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
14661        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14662        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14663        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
14664        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14667        // (intrinsic_wo_chain:{ *:[v2i32] } 1040:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
14668        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv2i32,
14669        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14670        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14671        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14672        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14673        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14674        GIR_EraseFromParent, /*InsnID*/0,
14675        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14676        // GIR_Coverage, 972,
14677        GIR_Done,
14678      // Label 763: @36543
14679      GIM_Try, /*On fail goto*//*Label 764*/ 36601, // Rule ID 973 //
14680        GIM_CheckFeatures, GIFBS_HasNEON,
14681        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
14682        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14683        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14684        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
14685        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14686        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14687        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14688        // (intrinsic_wo_chain:{ *:[v8i16] } 1040:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
14689        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i16,
14690        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14691        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14693        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14694        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14695        GIR_EraseFromParent, /*InsnID*/0,
14696        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14697        // GIR_Coverage, 973,
14698        GIR_Done,
14699      // Label 764: @36601
14700      GIM_Try, /*On fail goto*//*Label 765*/ 36659, // Rule ID 974 //
14701        GIM_CheckFeatures, GIFBS_HasNEON,
14702        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
14703        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14704        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14705        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
14706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14707        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14709        // (intrinsic_wo_chain:{ *:[v4i32] } 1040:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
14710        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv4i32,
14711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14712        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14714        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14715        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14716        GIR_EraseFromParent, /*InsnID*/0,
14717        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14718        // GIR_Coverage, 974,
14719        GIR_Done,
14720      // Label 765: @36659
14721      GIM_Try, /*On fail goto*//*Label 766*/ 36717, // Rule ID 975 //
14722        GIM_CheckFeatures, GIFBS_HasNEON,
14723        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
14724        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14725        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14726        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
14727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14729        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14730        // (intrinsic_wo_chain:{ *:[v8i8] } 1040:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
14731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv8i8,
14732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14735        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14736        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14737        GIR_EraseFromParent, /*InsnID*/0,
14738        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14739        // GIR_Coverage, 975,
14740        GIR_Done,
14741      // Label 766: @36717
14742      GIM_Try, /*On fail goto*//*Label 767*/ 36775, // Rule ID 976 //
14743        GIM_CheckFeatures, GIFBS_HasNEON,
14744        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vhsubu,
14745        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14746        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14747        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
14748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14749        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14750        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14751        // (intrinsic_wo_chain:{ *:[v16i8] } 1040:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
14752        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VHSUBuv16i8,
14753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14756        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14757        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14758        GIR_EraseFromParent, /*InsnID*/0,
14759        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14760        // GIR_Coverage, 976,
14761        GIR_Done,
14762      // Label 767: @36775
14763      GIM_Try, /*On fail goto*//*Label 768*/ 36833, // Rule ID 977 //
14764        GIM_CheckFeatures, GIFBS_HasNEON,
14765        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
14766        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14767        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14768        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
14769        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14772        // (intrinsic_wo_chain:{ *:[v4i16] } 1094:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
14773        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i16,
14774        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14775        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14777        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14778        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14779        GIR_EraseFromParent, /*InsnID*/0,
14780        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14781        // GIR_Coverage, 977,
14782        GIR_Done,
14783      // Label 768: @36833
14784      GIM_Try, /*On fail goto*//*Label 769*/ 36891, // Rule ID 978 //
14785        GIM_CheckFeatures, GIFBS_HasNEON,
14786        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
14787        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14788        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14789        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
14790        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14791        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14792        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14793        // (intrinsic_wo_chain:{ *:[v2i32] } 1094:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
14794        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i32,
14795        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14796        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14797        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14798        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14799        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14800        GIR_EraseFromParent, /*InsnID*/0,
14801        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14802        // GIR_Coverage, 978,
14803        GIR_Done,
14804      // Label 769: @36891
14805      GIM_Try, /*On fail goto*//*Label 770*/ 36949, // Rule ID 979 //
14806        GIM_CheckFeatures, GIFBS_HasNEON,
14807        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
14808        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14809        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14810        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
14811        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14812        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14813        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14814        // (intrinsic_wo_chain:{ *:[v8i16] } 1094:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
14815        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i16,
14816        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14817        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14818        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14819        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14820        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14821        GIR_EraseFromParent, /*InsnID*/0,
14822        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14823        // GIR_Coverage, 979,
14824        GIR_Done,
14825      // Label 770: @36949
14826      GIM_Try, /*On fail goto*//*Label 771*/ 37007, // Rule ID 980 //
14827        GIM_CheckFeatures, GIFBS_HasNEON,
14828        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
14829        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14830        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14831        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
14832        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14833        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14834        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14835        // (intrinsic_wo_chain:{ *:[v4i32] } 1094:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
14836        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv4i32,
14837        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14838        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14839        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14840        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14841        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14842        GIR_EraseFromParent, /*InsnID*/0,
14843        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14844        // GIR_Coverage, 980,
14845        GIR_Done,
14846      // Label 771: @37007
14847      GIM_Try, /*On fail goto*//*Label 772*/ 37065, // Rule ID 981 //
14848        GIM_CheckFeatures, GIFBS_HasNEON,
14849        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
14850        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
14851        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
14852        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
14853        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14854        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14855        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14856        // (intrinsic_wo_chain:{ *:[v8i8] } 1094:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
14857        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv8i8,
14858        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14859        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14861        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14862        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14863        GIR_EraseFromParent, /*InsnID*/0,
14864        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14865        // GIR_Coverage, 981,
14866        GIR_Done,
14867      // Label 772: @37065
14868      GIM_Try, /*On fail goto*//*Label 773*/ 37123, // Rule ID 982 //
14869        GIM_CheckFeatures, GIFBS_HasNEON,
14870        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
14871        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
14872        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
14873        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
14874        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14875        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14876        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14877        // (intrinsic_wo_chain:{ *:[v16i8] } 1094:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
14878        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv16i8,
14879        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14880        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14881        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14882        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14883        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14884        GIR_EraseFromParent, /*InsnID*/0,
14885        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14886        // GIR_Coverage, 982,
14887        GIR_Done,
14888      // Label 773: @37123
14889      GIM_Try, /*On fail goto*//*Label 774*/ 37181, // Rule ID 983 //
14890        GIM_CheckFeatures, GIFBS_HasNEON,
14891        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
14892        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
14893        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
14894        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
14895        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14898        // (intrinsic_wo_chain:{ *:[v1i64] } 1094:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
14899        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv1i64,
14900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14903        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14904        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14905        GIR_EraseFromParent, /*InsnID*/0,
14906        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14907        // GIR_Coverage, 983,
14908        GIR_Done,
14909      // Label 774: @37181
14910      GIM_Try, /*On fail goto*//*Label 775*/ 37239, // Rule ID 984 //
14911        GIM_CheckFeatures, GIFBS_HasNEON,
14912        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubs,
14913        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
14914        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
14915        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
14916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14918        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14919        // (intrinsic_wo_chain:{ *:[v2i64] } 1094:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
14920        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBsv2i64,
14921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14924        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14925        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14926        GIR_EraseFromParent, /*InsnID*/0,
14927        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14928        // GIR_Coverage, 984,
14929        GIR_Done,
14930      // Label 775: @37239
14931      GIM_Try, /*On fail goto*//*Label 776*/ 37297, // Rule ID 985 //
14932        GIM_CheckFeatures, GIFBS_HasNEON,
14933        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
14934        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
14935        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
14936        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
14937        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14938        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14939        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14940        // (intrinsic_wo_chain:{ *:[v4i16] } 1095:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
14941        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i16,
14942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14943        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14945        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14946        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14947        GIR_EraseFromParent, /*InsnID*/0,
14948        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14949        // GIR_Coverage, 985,
14950        GIR_Done,
14951      // Label 776: @37297
14952      GIM_Try, /*On fail goto*//*Label 777*/ 37355, // Rule ID 986 //
14953        GIM_CheckFeatures, GIFBS_HasNEON,
14954        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
14955        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
14956        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
14957        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
14958        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
14959        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
14960        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
14961        // (intrinsic_wo_chain:{ *:[v2i32] } 1095:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
14962        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i32,
14963        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14964        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14965        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14966        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14967        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14968        GIR_EraseFromParent, /*InsnID*/0,
14969        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14970        // GIR_Coverage, 986,
14971        GIR_Done,
14972      // Label 777: @37355
14973      GIM_Try, /*On fail goto*//*Label 778*/ 37413, // Rule ID 987 //
14974        GIM_CheckFeatures, GIFBS_HasNEON,
14975        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
14976        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
14977        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
14978        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
14979        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
14980        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
14981        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
14982        // (intrinsic_wo_chain:{ *:[v8i16] } 1095:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
14983        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i16,
14984        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
14985        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
14986        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
14987        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
14988        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
14989        GIR_EraseFromParent, /*InsnID*/0,
14990        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
14991        // GIR_Coverage, 987,
14992        GIR_Done,
14993      // Label 778: @37413
14994      GIM_Try, /*On fail goto*//*Label 779*/ 37471, // Rule ID 988 //
14995        GIM_CheckFeatures, GIFBS_HasNEON,
14996        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
14997        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
14998        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
14999        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
15000        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15001        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15002        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15003        // (intrinsic_wo_chain:{ *:[v4i32] } 1095:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
15004        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv4i32,
15005        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15006        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15007        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15008        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15009        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15010        GIR_EraseFromParent, /*InsnID*/0,
15011        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15012        // GIR_Coverage, 988,
15013        GIR_Done,
15014      // Label 779: @37471
15015      GIM_Try, /*On fail goto*//*Label 780*/ 37529, // Rule ID 989 //
15016        GIM_CheckFeatures, GIFBS_HasNEON,
15017        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
15018        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
15019        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
15020        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
15021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15022        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15023        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15024        // (intrinsic_wo_chain:{ *:[v8i8] } 1095:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
15025        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv8i8,
15026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15027        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15028        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15029        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15030        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15031        GIR_EraseFromParent, /*InsnID*/0,
15032        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15033        // GIR_Coverage, 989,
15034        GIR_Done,
15035      // Label 780: @37529
15036      GIM_Try, /*On fail goto*//*Label 781*/ 37587, // Rule ID 990 //
15037        GIM_CheckFeatures, GIFBS_HasNEON,
15038        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
15039        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
15040        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15041        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
15042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15044        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15045        // (intrinsic_wo_chain:{ *:[v16i8] } 1095:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
15046        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv16i8,
15047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15049        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15050        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15051        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15052        GIR_EraseFromParent, /*InsnID*/0,
15053        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15054        // GIR_Coverage, 990,
15055        GIR_Done,
15056      // Label 781: @37587
15057      GIM_Try, /*On fail goto*//*Label 782*/ 37645, // Rule ID 991 //
15058        GIM_CheckFeatures, GIFBS_HasNEON,
15059        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
15060        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
15061        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
15062        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
15063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15066        // (intrinsic_wo_chain:{ *:[v1i64] } 1095:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
15067        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv1i64,
15068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15071        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15072        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15073        GIR_EraseFromParent, /*InsnID*/0,
15074        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15075        // GIR_Coverage, 991,
15076        GIR_Done,
15077      // Label 782: @37645
15078      GIM_Try, /*On fail goto*//*Label 783*/ 37703, // Rule ID 992 //
15079        GIM_CheckFeatures, GIFBS_HasNEON,
15080        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqsubu,
15081        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
15082        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
15083        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
15084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15087        // (intrinsic_wo_chain:{ *:[v2i64] } 1095:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
15088        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSUBuv2i64,
15089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15092        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15093        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15094        GIR_EraseFromParent, /*InsnID*/0,
15095        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15096        // GIR_Coverage, 992,
15097        GIR_Done,
15098      // Label 783: @37703
15099      GIM_Try, /*On fail goto*//*Label 784*/ 37761, // Rule ID 993 //
15100        GIM_CheckFeatures, GIFBS_HasNEON,
15101        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
15102        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
15103        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15104        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
15105        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15108        // (intrinsic_wo_chain:{ *:[v8i8] } 1112:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
15109        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv8i8,
15110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15113        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15114        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15115        GIR_EraseFromParent, /*InsnID*/0,
15116        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15117        // GIR_Coverage, 993,
15118        GIR_Done,
15119      // Label 784: @37761
15120      GIM_Try, /*On fail goto*//*Label 785*/ 37819, // Rule ID 994 //
15121        GIM_CheckFeatures, GIFBS_HasNEON,
15122        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
15123        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15124        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15125        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
15126        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15127        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15128        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15129        // (intrinsic_wo_chain:{ *:[v4i16] } 1112:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
15130        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv4i16,
15131        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15132        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15133        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15134        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15135        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15136        GIR_EraseFromParent, /*InsnID*/0,
15137        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15138        // GIR_Coverage, 994,
15139        GIR_Done,
15140      // Label 785: @37819
15141      GIM_Try, /*On fail goto*//*Label 786*/ 37877, // Rule ID 995 //
15142        GIM_CheckFeatures, GIFBS_HasNEON,
15143        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsubhn,
15144        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15145        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
15146        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
15147        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15148        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15149        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15150        // (intrinsic_wo_chain:{ *:[v2i32] } 1112:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
15151        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSUBHNv2i32,
15152        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15153        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15155        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15156        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15157        GIR_EraseFromParent, /*InsnID*/0,
15158        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15159        // GIR_Coverage, 995,
15160        GIR_Done,
15161      // Label 786: @37877
15162      GIM_Try, /*On fail goto*//*Label 787*/ 37935, // Rule ID 1088 //
15163        GIM_CheckFeatures, GIFBS_HasNEON,
15164        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
15165        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15166        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15167        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
15168        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15169        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15170        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15171        // (intrinsic_wo_chain:{ *:[v2i32] } 1019:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
15172        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfd,
15173        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15174        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15175        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15176        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15177        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15178        GIR_EraseFromParent, /*InsnID*/0,
15179        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15180        // GIR_Coverage, 1088,
15181        GIR_Done,
15182      // Label 787: @37935
15183      GIM_Try, /*On fail goto*//*Label 788*/ 37993, // Rule ID 1089 //
15184        GIM_CheckFeatures, GIFBS_HasNEON,
15185        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
15186        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15187        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15188        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
15189        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15190        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15191        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15192        // (intrinsic_wo_chain:{ *:[v4i32] } 1019:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
15193        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEfq,
15194        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15195        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15196        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15197        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15198        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15199        GIR_EraseFromParent, /*InsnID*/0,
15200        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15201        // GIR_Coverage, 1089,
15202        GIR_Done,
15203      // Label 788: @37993
15204      GIM_Try, /*On fail goto*//*Label 789*/ 38051, // Rule ID 1090 //
15205        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
15206        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
15207        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15208        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15209        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
15210        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15211        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15212        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15213        // (intrinsic_wo_chain:{ *:[v4i16] } 1019:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
15214        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhd,
15215        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15216        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15217        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15218        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15219        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15220        GIR_EraseFromParent, /*InsnID*/0,
15221        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15222        // GIR_Coverage, 1090,
15223        GIR_Done,
15224      // Label 789: @38051
15225      GIM_Try, /*On fail goto*//*Label 790*/ 38109, // Rule ID 1091 //
15226        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
15227        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacge,
15228        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15229        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15230        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
15231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15232        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15233        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15234        // (intrinsic_wo_chain:{ *:[v8i16] } 1019:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
15235        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGEhq,
15236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15237        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15238        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15239        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15240        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15241        GIR_EraseFromParent, /*InsnID*/0,
15242        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15243        // GIR_Coverage, 1091,
15244        GIR_Done,
15245      // Label 790: @38109
15246      GIM_Try, /*On fail goto*//*Label 791*/ 38167, // Rule ID 1092 //
15247        GIM_CheckFeatures, GIFBS_HasNEON,
15248        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
15249        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15250        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15251        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
15252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15254        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15255        // (intrinsic_wo_chain:{ *:[v2i32] } 1020:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
15256        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfd,
15257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15260        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15261        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15262        GIR_EraseFromParent, /*InsnID*/0,
15263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15264        // GIR_Coverage, 1092,
15265        GIR_Done,
15266      // Label 791: @38167
15267      GIM_Try, /*On fail goto*//*Label 792*/ 38225, // Rule ID 1093 //
15268        GIM_CheckFeatures, GIFBS_HasNEON,
15269        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
15270        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15271        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15272        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
15273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15274        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15276        // (intrinsic_wo_chain:{ *:[v4i32] } 1020:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
15277        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGTfq,
15278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15279        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15281        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15282        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15283        GIR_EraseFromParent, /*InsnID*/0,
15284        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15285        // GIR_Coverage, 1093,
15286        GIR_Done,
15287      // Label 792: @38225
15288      GIM_Try, /*On fail goto*//*Label 793*/ 38283, // Rule ID 1094 //
15289        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
15290        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
15291        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15292        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15293        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
15294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15295        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15296        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15297        // (intrinsic_wo_chain:{ *:[v4i16] } 1020:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
15298        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThd,
15299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15300        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15301        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15302        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15303        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15304        GIR_EraseFromParent, /*InsnID*/0,
15305        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15306        // GIR_Coverage, 1094,
15307        GIR_Done,
15308      // Label 793: @38283
15309      GIM_Try, /*On fail goto*//*Label 794*/ 38341, // Rule ID 1095 //
15310        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
15311        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vacgt,
15312        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15313        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15314        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
15315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15316        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15317        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15318        // (intrinsic_wo_chain:{ *:[v8f16] } 1020:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VACGThq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
15319        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VACGThq,
15320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15321        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15322        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15323        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15324        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15325        GIR_EraseFromParent, /*InsnID*/0,
15326        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15327        // GIR_Coverage, 1095,
15328        GIR_Done,
15329      // Label 794: @38341
15330      GIM_Try, /*On fail goto*//*Label 795*/ 38399, // Rule ID 1128 //
15331        GIM_CheckFeatures, GIFBS_HasNEON,
15332        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15333        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15334        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15335        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
15336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15337        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15338        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15339        // (intrinsic_wo_chain:{ *:[v4i16] } 1016:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
15340        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i16,
15341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15342        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15343        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15344        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15345        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15346        GIR_EraseFromParent, /*InsnID*/0,
15347        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15348        // GIR_Coverage, 1128,
15349        GIR_Done,
15350      // Label 795: @38399
15351      GIM_Try, /*On fail goto*//*Label 796*/ 38457, // Rule ID 1129 //
15352        GIM_CheckFeatures, GIFBS_HasNEON,
15353        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15354        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15355        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15356        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
15357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15358        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15359        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15360        // (intrinsic_wo_chain:{ *:[v2i32] } 1016:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
15361        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv2i32,
15362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15363        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15364        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15365        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15366        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15367        GIR_EraseFromParent, /*InsnID*/0,
15368        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15369        // GIR_Coverage, 1129,
15370        GIR_Done,
15371      // Label 796: @38457
15372      GIM_Try, /*On fail goto*//*Label 797*/ 38515, // Rule ID 1130 //
15373        GIM_CheckFeatures, GIFBS_HasNEON,
15374        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15375        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15376        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15377        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
15378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15380        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15381        // (intrinsic_wo_chain:{ *:[v8i16] } 1016:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
15382        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i16,
15383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15384        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15385        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15386        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15387        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15388        GIR_EraseFromParent, /*InsnID*/0,
15389        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15390        // GIR_Coverage, 1130,
15391        GIR_Done,
15392      // Label 797: @38515
15393      GIM_Try, /*On fail goto*//*Label 798*/ 38573, // Rule ID 1131 //
15394        GIM_CheckFeatures, GIFBS_HasNEON,
15395        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15396        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15397        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15398        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
15399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15401        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15402        // (intrinsic_wo_chain:{ *:[v4i32] } 1016:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
15403        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv4i32,
15404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15405        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15406        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15407        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15408        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15409        GIR_EraseFromParent, /*InsnID*/0,
15410        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15411        // GIR_Coverage, 1131,
15412        GIR_Done,
15413      // Label 798: @38573
15414      GIM_Try, /*On fail goto*//*Label 799*/ 38631, // Rule ID 1132 //
15415        GIM_CheckFeatures, GIFBS_HasNEON,
15416        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15417        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
15418        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
15419        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
15420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15421        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15422        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15423        // (intrinsic_wo_chain:{ *:[v8i8] } 1016:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
15424        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv8i8,
15425        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15426        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15427        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15428        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15429        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15430        GIR_EraseFromParent, /*InsnID*/0,
15431        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15432        // GIR_Coverage, 1132,
15433        GIR_Done,
15434      // Label 799: @38631
15435      GIM_Try, /*On fail goto*//*Label 800*/ 38689, // Rule ID 1133 //
15436        GIM_CheckFeatures, GIFBS_HasNEON,
15437        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15438        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
15439        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15440        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
15441        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15442        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15443        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15444        // (intrinsic_wo_chain:{ *:[v16i8] } 1016:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
15445        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDsv16i8,
15446        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15447        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15448        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15449        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15450        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15451        GIR_EraseFromParent, /*InsnID*/0,
15452        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15453        // GIR_Coverage, 1133,
15454        GIR_Done,
15455      // Label 800: @38689
15456      GIM_Try, /*On fail goto*//*Label 801*/ 38747, // Rule ID 1134 //
15457        GIM_CheckFeatures, GIFBS_HasNEON,
15458        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
15459        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15460        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15461        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
15462        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15463        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15464        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15465        // (intrinsic_wo_chain:{ *:[v4i16] } 1017:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
15466        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i16,
15467        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15468        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15469        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15470        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15471        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15472        GIR_EraseFromParent, /*InsnID*/0,
15473        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15474        // GIR_Coverage, 1134,
15475        GIR_Done,
15476      // Label 801: @38747
15477      GIM_Try, /*On fail goto*//*Label 802*/ 38805, // Rule ID 1135 //
15478        GIM_CheckFeatures, GIFBS_HasNEON,
15479        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
15480        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15481        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15482        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
15483        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15484        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15485        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15486        // (intrinsic_wo_chain:{ *:[v2i32] } 1017:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
15487        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv2i32,
15488        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15489        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15490        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15491        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15492        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15493        GIR_EraseFromParent, /*InsnID*/0,
15494        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15495        // GIR_Coverage, 1135,
15496        GIR_Done,
15497      // Label 802: @38805
15498      GIM_Try, /*On fail goto*//*Label 803*/ 38863, // Rule ID 1136 //
15499        GIM_CheckFeatures, GIFBS_HasNEON,
15500        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
15501        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15502        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15503        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
15504        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15505        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15506        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15507        // (intrinsic_wo_chain:{ *:[v8i16] } 1017:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
15508        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i16,
15509        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15510        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15512        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15513        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15514        GIR_EraseFromParent, /*InsnID*/0,
15515        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15516        // GIR_Coverage, 1136,
15517        GIR_Done,
15518      // Label 803: @38863
15519      GIM_Try, /*On fail goto*//*Label 804*/ 38921, // Rule ID 1137 //
15520        GIM_CheckFeatures, GIFBS_HasNEON,
15521        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
15522        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15523        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15524        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
15525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15526        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15527        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15528        // (intrinsic_wo_chain:{ *:[v4i32] } 1017:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
15529        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv4i32,
15530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15533        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15534        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15535        GIR_EraseFromParent, /*InsnID*/0,
15536        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15537        // GIR_Coverage, 1137,
15538        GIR_Done,
15539      // Label 804: @38921
15540      GIM_Try, /*On fail goto*//*Label 805*/ 38979, // Rule ID 1138 //
15541        GIM_CheckFeatures, GIFBS_HasNEON,
15542        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
15543        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
15544        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
15545        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
15546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15549        // (intrinsic_wo_chain:{ *:[v8i8] } 1017:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
15550        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv8i8,
15551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15554        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15555        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15556        GIR_EraseFromParent, /*InsnID*/0,
15557        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15558        // GIR_Coverage, 1138,
15559        GIR_Done,
15560      // Label 805: @38979
15561      GIM_Try, /*On fail goto*//*Label 806*/ 39037, // Rule ID 1139 //
15562        GIM_CheckFeatures, GIFBS_HasNEON,
15563        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabdu,
15564        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
15565        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
15566        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
15567        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15570        // (intrinsic_wo_chain:{ *:[v16i8] } 1017:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
15571        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDuv16i8,
15572        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15575        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15576        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15577        GIR_EraseFromParent, /*InsnID*/0,
15578        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15579        // GIR_Coverage, 1139,
15580        GIR_Done,
15581      // Label 806: @39037
15582      GIM_Try, /*On fail goto*//*Label 807*/ 39095, // Rule ID 1140 //
15583        GIM_CheckFeatures, GIFBS_HasNEON,
15584        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15585        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15586        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15587        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
15588        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15589        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15591        // (intrinsic_wo_chain:{ *:[v2f32] } 1016:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
15592        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfd,
15593        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15594        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15596        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15597        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15598        GIR_EraseFromParent, /*InsnID*/0,
15599        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15600        // GIR_Coverage, 1140,
15601        GIR_Done,
15602      // Label 807: @39095
15603      GIM_Try, /*On fail goto*//*Label 808*/ 39153, // Rule ID 1141 //
15604        GIM_CheckFeatures, GIFBS_HasNEON,
15605        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15606        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15607        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15608        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
15609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15611        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15612        // (intrinsic_wo_chain:{ *:[v4f32] } 1016:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
15613        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDfq,
15614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15617        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15618        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15619        GIR_EraseFromParent, /*InsnID*/0,
15620        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15621        // GIR_Coverage, 1141,
15622        GIR_Done,
15623      // Label 808: @39153
15624      GIM_Try, /*On fail goto*//*Label 809*/ 39211, // Rule ID 1142 //
15625        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
15626        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15627        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15628        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15629        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
15630        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15631        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15632        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15633        // (intrinsic_wo_chain:{ *:[v4f16] } 1016:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
15634        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhd,
15635        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15636        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15637        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15638        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15639        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15640        GIR_EraseFromParent, /*InsnID*/0,
15641        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15642        // GIR_Coverage, 1142,
15643        GIR_Done,
15644      // Label 809: @39211
15645      GIM_Try, /*On fail goto*//*Label 810*/ 39269, // Rule ID 1143 //
15646        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
15647        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vabds,
15648        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15649        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15650        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
15651        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15652        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15653        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15654        // (intrinsic_wo_chain:{ *:[v8f16] } 1016:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
15655        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDhq,
15656        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15657        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15658        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15659        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15660        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15661        GIR_EraseFromParent, /*InsnID*/0,
15662        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15663        // GIR_Coverage, 1143,
15664        GIR_Done,
15665      // Label 810: @39269
15666      GIM_Try, /*On fail goto*//*Label 811*/ 39327, // Rule ID 1208 //
15667        GIM_CheckFeatures, GIFBS_HasNEON,
15668        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
15669        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
15670        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
15671        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
15672        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15673        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15674        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15675        // (intrinsic_wo_chain:{ *:[v8i8] } 1066:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
15676        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi8,
15677        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15680        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15681        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15682        GIR_EraseFromParent, /*InsnID*/0,
15683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15684        // GIR_Coverage, 1208,
15685        GIR_Done,
15686      // Label 811: @39327
15687      GIM_Try, /*On fail goto*//*Label 812*/ 39385, // Rule ID 1209 //
15688        GIM_CheckFeatures, GIFBS_HasNEON,
15689        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
15690        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15691        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15692        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
15693        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15695        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15696        // (intrinsic_wo_chain:{ *:[v4i16] } 1066:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
15697        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi16,
15698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15700        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15701        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15702        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15703        GIR_EraseFromParent, /*InsnID*/0,
15704        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15705        // GIR_Coverage, 1209,
15706        GIR_Done,
15707      // Label 812: @39385
15708      GIM_Try, /*On fail goto*//*Label 813*/ 39443, // Rule ID 1210 //
15709        GIM_CheckFeatures, GIFBS_HasNEON,
15710        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
15711        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15712        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15713        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
15714        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15715        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15716        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15717        // (intrinsic_wo_chain:{ *:[v2i32] } 1066:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
15718        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDi32,
15719        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15720        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15721        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15722        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15723        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15724        GIR_EraseFromParent, /*InsnID*/0,
15725        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15726        // GIR_Coverage, 1210,
15727        GIR_Done,
15728      // Label 813: @39443
15729      GIM_Try, /*On fail goto*//*Label 814*/ 39501, // Rule ID 1211 //
15730        GIM_CheckFeatures, GIFBS_HasNEON,
15731        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
15732        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15733        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15734        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
15735        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15736        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15737        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15738        // (intrinsic_wo_chain:{ *:[v2f32] } 1066:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
15739        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDf,
15740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15741        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15743        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15744        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15745        GIR_EraseFromParent, /*InsnID*/0,
15746        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15747        // GIR_Coverage, 1211,
15748        GIR_Done,
15749      // Label 814: @39501
15750      GIM_Try, /*On fail goto*//*Label 815*/ 39559, // Rule ID 1212 //
15751        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
15752        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadd,
15753        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15754        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15755        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
15756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15759        // (intrinsic_wo_chain:{ *:[v4f16] } 1066:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
15760        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADDh,
15761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
15763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15764        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15765        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15766        GIR_EraseFromParent, /*InsnID*/0,
15767        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15768        // GIR_Coverage, 1212,
15769        GIR_Done,
15770      // Label 815: @39559
15771      GIM_Try, /*On fail goto*//*Label 816*/ 39617, // Rule ID 1225 //
15772        GIM_CheckFeatures, GIFBS_HasNEON,
15773        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
15774        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15775        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15776        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
15777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15780        // (intrinsic_wo_chain:{ *:[v4i16] } 1064:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
15781        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i8,
15782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15785        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15786        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15787        GIR_EraseFromParent, /*InsnID*/0,
15788        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15789        // GIR_Coverage, 1225,
15790        GIR_Done,
15791      // Label 816: @39617
15792      GIM_Try, /*On fail goto*//*Label 817*/ 39675, // Rule ID 1226 //
15793        GIM_CheckFeatures, GIFBS_HasNEON,
15794        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
15795        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15796        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15797        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
15798        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15801        // (intrinsic_wo_chain:{ *:[v2i32] } 1064:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
15802        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i16,
15803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15806        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15807        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15808        GIR_EraseFromParent, /*InsnID*/0,
15809        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15810        // GIR_Coverage, 1226,
15811        GIR_Done,
15812      // Label 817: @39675
15813      GIM_Try, /*On fail goto*//*Label 818*/ 39733, // Rule ID 1227 //
15814        GIM_CheckFeatures, GIFBS_HasNEON,
15815        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
15816        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
15817        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
15818        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
15819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15822        // (intrinsic_wo_chain:{ *:[v1i64] } 1064:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
15823        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv2i32,
15824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15827        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15828        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15829        GIR_EraseFromParent, /*InsnID*/0,
15830        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15831        // GIR_Coverage, 1227,
15832        GIR_Done,
15833      // Label 818: @39733
15834      GIM_Try, /*On fail goto*//*Label 819*/ 39791, // Rule ID 1228 //
15835        GIM_CheckFeatures, GIFBS_HasNEON,
15836        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
15837        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15838        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15839        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
15840        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15841        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15843        // (intrinsic_wo_chain:{ *:[v8i16] } 1064:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
15844        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv16i8,
15845        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15846        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15847        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15848        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15849        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15850        GIR_EraseFromParent, /*InsnID*/0,
15851        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15852        // GIR_Coverage, 1228,
15853        GIR_Done,
15854      // Label 819: @39791
15855      GIM_Try, /*On fail goto*//*Label 820*/ 39849, // Rule ID 1229 //
15856        GIM_CheckFeatures, GIFBS_HasNEON,
15857        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
15858        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15859        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15860        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
15861        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15862        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15863        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15864        // (intrinsic_wo_chain:{ *:[v4i32] } 1064:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
15865        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv8i16,
15866        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15867        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15868        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15869        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15870        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15871        GIR_EraseFromParent, /*InsnID*/0,
15872        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15873        // GIR_Coverage, 1229,
15874        GIR_Done,
15875      // Label 820: @39849
15876      GIM_Try, /*On fail goto*//*Label 821*/ 39907, // Rule ID 1230 //
15877        GIM_CheckFeatures, GIFBS_HasNEON,
15878        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadals,
15879        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
15880        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
15881        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
15882        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15883        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15884        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15885        // (intrinsic_wo_chain:{ *:[v2i64] } 1064:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
15886        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALsv4i32,
15887        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15888        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15889        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15890        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15891        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15892        GIR_EraseFromParent, /*InsnID*/0,
15893        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15894        // GIR_Coverage, 1230,
15895        GIR_Done,
15896      // Label 821: @39907
15897      GIM_Try, /*On fail goto*//*Label 822*/ 39965, // Rule ID 1231 //
15898        GIM_CheckFeatures, GIFBS_HasNEON,
15899        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
15900        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
15901        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
15902        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
15903        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15904        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15905        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15906        // (intrinsic_wo_chain:{ *:[v4i16] } 1065:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)  =>  (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
15907        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i8,
15908        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15909        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15910        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15911        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15912        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15913        GIR_EraseFromParent, /*InsnID*/0,
15914        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15915        // GIR_Coverage, 1231,
15916        GIR_Done,
15917      // Label 822: @39965
15918      GIM_Try, /*On fail goto*//*Label 823*/ 40023, // Rule ID 1232 //
15919        GIM_CheckFeatures, GIFBS_HasNEON,
15920        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
15921        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
15922        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
15923        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
15924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15925        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15926        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15927        // (intrinsic_wo_chain:{ *:[v2i32] } 1065:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)  =>  (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
15928        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i16,
15929        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15930        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15931        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15932        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15933        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15934        GIR_EraseFromParent, /*InsnID*/0,
15935        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15936        // GIR_Coverage, 1232,
15937        GIR_Done,
15938      // Label 823: @40023
15939      GIM_Try, /*On fail goto*//*Label 824*/ 40081, // Rule ID 1233 //
15940        GIM_CheckFeatures, GIFBS_HasNEON,
15941        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
15942        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
15943        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
15944        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
15945        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
15946        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
15947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
15948        // (intrinsic_wo_chain:{ *:[v1i64] } 1065:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)  =>  (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
15949        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv2i32,
15950        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15953        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15954        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15955        GIR_EraseFromParent, /*InsnID*/0,
15956        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15957        // GIR_Coverage, 1233,
15958        GIR_Done,
15959      // Label 824: @40081
15960      GIM_Try, /*On fail goto*//*Label 825*/ 40139, // Rule ID 1234 //
15961        GIM_CheckFeatures, GIFBS_HasNEON,
15962        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
15963        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
15964        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
15965        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
15966        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15967        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15968        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15969        // (intrinsic_wo_chain:{ *:[v8i16] } 1065:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)  =>  (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
15970        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv16i8,
15971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15972        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15973        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15974        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15975        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15976        GIR_EraseFromParent, /*InsnID*/0,
15977        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15978        // GIR_Coverage, 1234,
15979        GIR_Done,
15980      // Label 825: @40139
15981      GIM_Try, /*On fail goto*//*Label 826*/ 40197, // Rule ID 1235 //
15982        GIM_CheckFeatures, GIFBS_HasNEON,
15983        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
15984        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
15985        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
15986        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
15987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
15988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
15989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
15990        // (intrinsic_wo_chain:{ *:[v4i32] } 1065:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)  =>  (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
15991        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv8i16,
15992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
15993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
15994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
15995        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
15996        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
15997        GIR_EraseFromParent, /*InsnID*/0,
15998        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
15999        // GIR_Coverage, 1235,
16000        GIR_Done,
16001      // Label 826: @40197
16002      GIM_Try, /*On fail goto*//*Label 827*/ 40255, // Rule ID 1236 //
16003        GIM_CheckFeatures, GIFBS_HasNEON,
16004        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpadalu,
16005        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
16006        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
16007        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16008        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16009        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16011        // (intrinsic_wo_chain:{ *:[v2i64] } 1065:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)  =>  (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
16012        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPADALuv4i32,
16013        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16014        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
16015        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16016        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16017        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16018        GIR_EraseFromParent, /*InsnID*/0,
16019        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16020        // GIR_Coverage, 1236,
16021        GIR_Done,
16022      // Label 827: @40255
16023      GIM_Try, /*On fail goto*//*Label 828*/ 40313, // Rule ID 1237 //
16024        GIM_CheckFeatures, GIFBS_HasNEON,
16025        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
16026        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16027        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16028        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16029        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16030        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16031        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16032        // (intrinsic_wo_chain:{ *:[v8i8] } 1069:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
16033        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs8,
16034        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16035        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16036        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16037        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16038        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16039        GIR_EraseFromParent, /*InsnID*/0,
16040        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16041        // GIR_Coverage, 1237,
16042        GIR_Done,
16043      // Label 828: @40313
16044      GIM_Try, /*On fail goto*//*Label 829*/ 40371, // Rule ID 1238 //
16045        GIM_CheckFeatures, GIFBS_HasNEON,
16046        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
16047        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16048        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16049        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16050        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16051        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16052        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16053        // (intrinsic_wo_chain:{ *:[v4i16] } 1069:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
16054        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs16,
16055        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16056        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16057        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16058        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16059        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16060        GIR_EraseFromParent, /*InsnID*/0,
16061        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16062        // GIR_Coverage, 1238,
16063        GIR_Done,
16064      // Label 829: @40371
16065      GIM_Try, /*On fail goto*//*Label 830*/ 40429, // Rule ID 1239 //
16066        GIM_CheckFeatures, GIFBS_HasNEON,
16067        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
16068        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16069        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16070        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16071        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16072        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16073        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16074        // (intrinsic_wo_chain:{ *:[v2i32] } 1069:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
16075        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXs32,
16076        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16079        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16080        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16081        GIR_EraseFromParent, /*InsnID*/0,
16082        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16083        // GIR_Coverage, 1239,
16084        GIR_Done,
16085      // Label 830: @40429
16086      GIM_Try, /*On fail goto*//*Label 831*/ 40487, // Rule ID 1240 //
16087        GIM_CheckFeatures, GIFBS_HasNEON,
16088        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
16089        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16090        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16091        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16093        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16094        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16095        // (intrinsic_wo_chain:{ *:[v8i8] } 1070:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
16096        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu8,
16097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16098        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16099        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16100        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16101        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16102        GIR_EraseFromParent, /*InsnID*/0,
16103        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16104        // GIR_Coverage, 1240,
16105        GIR_Done,
16106      // Label 831: @40487
16107      GIM_Try, /*On fail goto*//*Label 832*/ 40545, // Rule ID 1241 //
16108        GIM_CheckFeatures, GIFBS_HasNEON,
16109        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
16110        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16111        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16112        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16113        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16114        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16115        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16116        // (intrinsic_wo_chain:{ *:[v4i16] } 1070:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
16117        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu16,
16118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16120        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16121        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16122        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16123        GIR_EraseFromParent, /*InsnID*/0,
16124        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16125        // GIR_Coverage, 1241,
16126        GIR_Done,
16127      // Label 832: @40545
16128      GIM_Try, /*On fail goto*//*Label 833*/ 40603, // Rule ID 1242 //
16129        GIM_CheckFeatures, GIFBS_HasNEON,
16130        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxu,
16131        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16132        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16133        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16134        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16135        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16136        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16137        // (intrinsic_wo_chain:{ *:[v2i32] } 1070:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
16138        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXu32,
16139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16142        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16143        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16144        GIR_EraseFromParent, /*InsnID*/0,
16145        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16146        // GIR_Coverage, 1242,
16147        GIR_Done,
16148      // Label 833: @40603
16149      GIM_Try, /*On fail goto*//*Label 834*/ 40661, // Rule ID 1243 //
16150        GIM_CheckFeatures, GIFBS_HasNEON,
16151        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
16152        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16153        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16154        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16158        // (intrinsic_wo_chain:{ *:[v2f32] } 1069:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
16159        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXf,
16160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16163        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16164        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16165        GIR_EraseFromParent, /*InsnID*/0,
16166        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16167        // GIR_Coverage, 1243,
16168        GIR_Done,
16169      // Label 834: @40661
16170      GIM_Try, /*On fail goto*//*Label 835*/ 40719, // Rule ID 1244 //
16171        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16172        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmaxs,
16173        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16174        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16175        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16176        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16177        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16179        // (intrinsic_wo_chain:{ *:[v4f16] } 1069:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
16180        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMAXh,
16181        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16182        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16183        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16184        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16185        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16186        GIR_EraseFromParent, /*InsnID*/0,
16187        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16188        // GIR_Coverage, 1244,
16189        GIR_Done,
16190      // Label 835: @40719
16191      GIM_Try, /*On fail goto*//*Label 836*/ 40777, // Rule ID 1245 //
16192        GIM_CheckFeatures, GIFBS_HasNEON,
16193        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
16194        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16195        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16196        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16198        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16199        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16200        // (intrinsic_wo_chain:{ *:[v8i8] } 1071:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
16201        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs8,
16202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16203        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16204        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16205        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16206        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16207        GIR_EraseFromParent, /*InsnID*/0,
16208        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16209        // GIR_Coverage, 1245,
16210        GIR_Done,
16211      // Label 836: @40777
16212      GIM_Try, /*On fail goto*//*Label 837*/ 40835, // Rule ID 1246 //
16213        GIM_CheckFeatures, GIFBS_HasNEON,
16214        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
16215        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16216        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16217        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16220        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16221        // (intrinsic_wo_chain:{ *:[v4i16] } 1071:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
16222        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs16,
16223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16225        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16226        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16227        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16228        GIR_EraseFromParent, /*InsnID*/0,
16229        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16230        // GIR_Coverage, 1246,
16231        GIR_Done,
16232      // Label 837: @40835
16233      GIM_Try, /*On fail goto*//*Label 838*/ 40893, // Rule ID 1247 //
16234        GIM_CheckFeatures, GIFBS_HasNEON,
16235        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
16236        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16237        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16238        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16242        // (intrinsic_wo_chain:{ *:[v2i32] } 1071:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
16243        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINs32,
16244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16247        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16248        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16249        GIR_EraseFromParent, /*InsnID*/0,
16250        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16251        // GIR_Coverage, 1247,
16252        GIR_Done,
16253      // Label 838: @40893
16254      GIM_Try, /*On fail goto*//*Label 839*/ 40951, // Rule ID 1248 //
16255        GIM_CheckFeatures, GIFBS_HasNEON,
16256        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
16257        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16258        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16259        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16260        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16263        // (intrinsic_wo_chain:{ *:[v8i8] } 1072:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
16264        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu8,
16265        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16268        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16269        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16270        GIR_EraseFromParent, /*InsnID*/0,
16271        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16272        // GIR_Coverage, 1248,
16273        GIR_Done,
16274      // Label 839: @40951
16275      GIM_Try, /*On fail goto*//*Label 840*/ 41009, // Rule ID 1249 //
16276        GIM_CheckFeatures, GIFBS_HasNEON,
16277        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
16278        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16279        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16280        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16281        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16282        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16284        // (intrinsic_wo_chain:{ *:[v4i16] } 1072:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
16285        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu16,
16286        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16287        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16289        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16290        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16291        GIR_EraseFromParent, /*InsnID*/0,
16292        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16293        // GIR_Coverage, 1249,
16294        GIR_Done,
16295      // Label 840: @41009
16296      GIM_Try, /*On fail goto*//*Label 841*/ 41067, // Rule ID 1250 //
16297        GIM_CheckFeatures, GIFBS_HasNEON,
16298        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpminu,
16299        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16300        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16301        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16302        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16303        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16304        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16305        // (intrinsic_wo_chain:{ *:[v2i32] } 1072:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
16306        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINu32,
16307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16308        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16309        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16310        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16311        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16312        GIR_EraseFromParent, /*InsnID*/0,
16313        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16314        // GIR_Coverage, 1250,
16315        GIR_Done,
16316      // Label 841: @41067
16317      GIM_Try, /*On fail goto*//*Label 842*/ 41125, // Rule ID 1251 //
16318        GIM_CheckFeatures, GIFBS_HasNEON,
16319        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
16320        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16321        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16322        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16324        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16325        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16326        // (intrinsic_wo_chain:{ *:[v2f32] } 1071:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
16327        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINf,
16328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16330        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16331        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16332        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16333        GIR_EraseFromParent, /*InsnID*/0,
16334        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16335        // GIR_Coverage, 1251,
16336        GIR_Done,
16337      // Label 842: @41125
16338      GIM_Try, /*On fail goto*//*Label 843*/ 41183, // Rule ID 1252 //
16339        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16340        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vpmins,
16341        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16342        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16343        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16344        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16345        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16347        // (intrinsic_wo_chain:{ *:[v4f16] } 1071:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
16348        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VPMINh,
16349        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16350        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16351        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16352        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16353        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16354        GIR_EraseFromParent, /*InsnID*/0,
16355        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16356        // GIR_Coverage, 1252,
16357        GIR_Done,
16358      // Label 843: @41183
16359      GIM_Try, /*On fail goto*//*Label 844*/ 41241, // Rule ID 1259 //
16360        GIM_CheckFeatures, GIFBS_HasNEON,
16361        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
16362        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16363        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16364        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16365        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16366        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16367        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16368        // (intrinsic_wo_chain:{ *:[v2f32] } 1098:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
16369        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfd,
16370        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16371        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16372        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16373        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16374        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16375        GIR_EraseFromParent, /*InsnID*/0,
16376        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16377        // GIR_Coverage, 1259,
16378        GIR_Done,
16379      // Label 844: @41241
16380      GIM_Try, /*On fail goto*//*Label 845*/ 41299, // Rule ID 1260 //
16381        GIM_CheckFeatures, GIFBS_HasNEON,
16382        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
16383        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16384        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16385        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16386        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16387        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16388        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16389        // (intrinsic_wo_chain:{ *:[v4f32] } 1098:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
16390        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPSfq,
16391        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16392        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16393        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16394        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16395        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16396        GIR_EraseFromParent, /*InsnID*/0,
16397        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16398        // GIR_Coverage, 1260,
16399        GIR_Done,
16400      // Label 845: @41299
16401      GIM_Try, /*On fail goto*//*Label 846*/ 41357, // Rule ID 1261 //
16402        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16403        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
16404        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16405        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16406        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16407        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16408        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16409        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16410        // (intrinsic_wo_chain:{ *:[v4f16] } 1098:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
16411        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShd,
16412        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16413        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16414        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16415        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16416        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16417        GIR_EraseFromParent, /*InsnID*/0,
16418        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16419        // GIR_Coverage, 1261,
16420        GIR_Done,
16421      // Label 846: @41357
16422      GIM_Try, /*On fail goto*//*Label 847*/ 41415, // Rule ID 1262 //
16423        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16424        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrecps,
16425        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16426        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16427        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16430        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16431        // (intrinsic_wo_chain:{ *:[v8f16] } 1098:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
16432        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRECPShq,
16433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16436        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16437        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16438        GIR_EraseFromParent, /*InsnID*/0,
16439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16440        // GIR_Coverage, 1262,
16441        GIR_Done,
16442      // Label 847: @41415
16443      GIM_Try, /*On fail goto*//*Label 848*/ 41473, // Rule ID 1269 //
16444        GIM_CheckFeatures, GIFBS_HasNEON,
16445        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
16446        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16449        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16452        // (intrinsic_wo_chain:{ *:[v2f32] } 1111:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
16453        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfd,
16454        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16455        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16457        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16458        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16459        GIR_EraseFromParent, /*InsnID*/0,
16460        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16461        // GIR_Coverage, 1269,
16462        GIR_Done,
16463      // Label 848: @41473
16464      GIM_Try, /*On fail goto*//*Label 849*/ 41531, // Rule ID 1270 //
16465        GIM_CheckFeatures, GIFBS_HasNEON,
16466        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
16467        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16468        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16469        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16470        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16471        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16472        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16473        // (intrinsic_wo_chain:{ *:[v4f32] } 1111:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
16474        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTSfq,
16475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16476        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16477        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16478        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16479        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16480        GIR_EraseFromParent, /*InsnID*/0,
16481        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16482        // GIR_Coverage, 1270,
16483        GIR_Done,
16484      // Label 849: @41531
16485      GIM_Try, /*On fail goto*//*Label 850*/ 41589, // Rule ID 1271 //
16486        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16487        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
16488        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16489        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16490        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16491        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16492        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16493        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16494        // (intrinsic_wo_chain:{ *:[v4f16] } 1111:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
16495        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShd,
16496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16499        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16500        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16501        GIR_EraseFromParent, /*InsnID*/0,
16502        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16503        // GIR_Coverage, 1271,
16504        GIR_Done,
16505      // Label 850: @41589
16506      GIM_Try, /*On fail goto*//*Label 851*/ 41647, // Rule ID 1272 //
16507        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
16508        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrsqrts,
16509        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16510        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16511        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16512        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16513        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16514        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16515        // (intrinsic_wo_chain:{ *:[v8f16] } 1111:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
16516        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSQRTShq,
16517        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16518        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
16519        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
16520        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16521        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16522        GIR_EraseFromParent, /*InsnID*/0,
16523        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16524        // GIR_Coverage, 1272,
16525        GIR_Done,
16526      // Label 851: @41647
16527      GIM_Try, /*On fail goto*//*Label 852*/ 41705, // Rule ID 1273 //
16528        GIM_CheckFeatures, GIFBS_HasNEON,
16529        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
16530        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16531        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16532        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16533        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16534        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16535        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16536        // (intrinsic_wo_chain:{ *:[v4i16] } 1114:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
16537        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i16,
16538        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16539        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16541        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16542        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16543        GIR_EraseFromParent, /*InsnID*/0,
16544        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16545        // GIR_Coverage, 1273,
16546        GIR_Done,
16547      // Label 852: @41705
16548      GIM_Try, /*On fail goto*//*Label 853*/ 41763, // Rule ID 1274 //
16549        GIM_CheckFeatures, GIFBS_HasNEON,
16550        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
16551        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16552        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16553        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16554        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16555        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16556        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16557        // (intrinsic_wo_chain:{ *:[v2i32] } 1114:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
16558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i32,
16559        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16560        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16561        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16562        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16563        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16564        GIR_EraseFromParent, /*InsnID*/0,
16565        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16566        // GIR_Coverage, 1274,
16567        GIR_Done,
16568      // Label 853: @41763
16569      GIM_Try, /*On fail goto*//*Label 854*/ 41821, // Rule ID 1275 //
16570        GIM_CheckFeatures, GIFBS_HasNEON,
16571        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
16572        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16573        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16574        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16576        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16577        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16578        // (intrinsic_wo_chain:{ *:[v8i16] } 1114:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
16579        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i16,
16580        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16581        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16582        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16583        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16584        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16585        GIR_EraseFromParent, /*InsnID*/0,
16586        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16587        // GIR_Coverage, 1275,
16588        GIR_Done,
16589      // Label 854: @41821
16590      GIM_Try, /*On fail goto*//*Label 855*/ 41879, // Rule ID 1276 //
16591        GIM_CheckFeatures, GIFBS_HasNEON,
16592        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
16593        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16594        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16595        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16596        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16597        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16598        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16599        // (intrinsic_wo_chain:{ *:[v4i32] } 1114:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
16600        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv4i32,
16601        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16602        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16603        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16604        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16605        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16606        GIR_EraseFromParent, /*InsnID*/0,
16607        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16608        // GIR_Coverage, 1276,
16609        GIR_Done,
16610      // Label 855: @41879
16611      GIM_Try, /*On fail goto*//*Label 856*/ 41937, // Rule ID 1277 //
16612        GIM_CheckFeatures, GIFBS_HasNEON,
16613        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
16614        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16615        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16616        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16617        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16618        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16619        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16620        // (intrinsic_wo_chain:{ *:[v8i8] } 1114:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
16621        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv8i8,
16622        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16623        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16624        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16625        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16626        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16627        GIR_EraseFromParent, /*InsnID*/0,
16628        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16629        // GIR_Coverage, 1277,
16630        GIR_Done,
16631      // Label 856: @41937
16632      GIM_Try, /*On fail goto*//*Label 857*/ 41995, // Rule ID 1278 //
16633        GIM_CheckFeatures, GIFBS_HasNEON,
16634        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
16635        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16636        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16637        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
16638        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16640        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16641        // (intrinsic_wo_chain:{ *:[v16i8] } 1114:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
16642        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv16i8,
16643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16644        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16645        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16646        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16647        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16648        GIR_EraseFromParent, /*InsnID*/0,
16649        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16650        // GIR_Coverage, 1278,
16651        GIR_Done,
16652      // Label 857: @41995
16653      GIM_Try, /*On fail goto*//*Label 858*/ 42053, // Rule ID 1279 //
16654        GIM_CheckFeatures, GIFBS_HasNEON,
16655        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
16656        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
16657        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
16658        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
16659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16662        // (intrinsic_wo_chain:{ *:[v1i64] } 1114:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
16663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv1i64,
16664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16667        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16668        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16669        GIR_EraseFromParent, /*InsnID*/0,
16670        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16671        // GIR_Coverage, 1279,
16672        GIR_Done,
16673      // Label 858: @42053
16674      GIM_Try, /*On fail goto*//*Label 859*/ 42111, // Rule ID 1280 //
16675        GIM_CheckFeatures, GIFBS_HasNEON,
16676        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshifts,
16677        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
16678        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
16679        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
16680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16683        // (intrinsic_wo_chain:{ *:[v2i64] } 1114:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
16684        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLsv2i64,
16685        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16688        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16689        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16690        GIR_EraseFromParent, /*InsnID*/0,
16691        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16692        // GIR_Coverage, 1280,
16693        GIR_Done,
16694      // Label 859: @42111
16695      GIM_Try, /*On fail goto*//*Label 860*/ 42169, // Rule ID 1281 //
16696        GIM_CheckFeatures, GIFBS_HasNEON,
16697        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
16698        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16699        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16700        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16701        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16704        // (intrinsic_wo_chain:{ *:[v4i16] } 1115:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
16705        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i16,
16706        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16707        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16709        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16710        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16711        GIR_EraseFromParent, /*InsnID*/0,
16712        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16713        // GIR_Coverage, 1281,
16714        GIR_Done,
16715      // Label 860: @42169
16716      GIM_Try, /*On fail goto*//*Label 861*/ 42227, // Rule ID 1282 //
16717        GIM_CheckFeatures, GIFBS_HasNEON,
16718        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
16719        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16720        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16721        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16722        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16723        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16725        // (intrinsic_wo_chain:{ *:[v2i32] } 1115:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
16726        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i32,
16727        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16728        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16729        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16730        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16731        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16732        GIR_EraseFromParent, /*InsnID*/0,
16733        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16734        // GIR_Coverage, 1282,
16735        GIR_Done,
16736      // Label 861: @42227
16737      GIM_Try, /*On fail goto*//*Label 862*/ 42285, // Rule ID 1283 //
16738        GIM_CheckFeatures, GIFBS_HasNEON,
16739        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
16740        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16741        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16742        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16743        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16744        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16745        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16746        // (intrinsic_wo_chain:{ *:[v8i16] } 1115:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
16747        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i16,
16748        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16749        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16750        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16751        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16752        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16753        GIR_EraseFromParent, /*InsnID*/0,
16754        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16755        // GIR_Coverage, 1283,
16756        GIR_Done,
16757      // Label 862: @42285
16758      GIM_Try, /*On fail goto*//*Label 863*/ 42343, // Rule ID 1284 //
16759        GIM_CheckFeatures, GIFBS_HasNEON,
16760        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
16761        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16762        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16763        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16764        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16766        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16767        // (intrinsic_wo_chain:{ *:[v4i32] } 1115:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
16768        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv4i32,
16769        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16770        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16771        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16772        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16773        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16774        GIR_EraseFromParent, /*InsnID*/0,
16775        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16776        // GIR_Coverage, 1284,
16777        GIR_Done,
16778      // Label 863: @42343
16779      GIM_Try, /*On fail goto*//*Label 864*/ 42401, // Rule ID 1285 //
16780        GIM_CheckFeatures, GIFBS_HasNEON,
16781        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
16782        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16783        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16784        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16785        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16786        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16787        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16788        // (intrinsic_wo_chain:{ *:[v8i8] } 1115:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
16789        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv8i8,
16790        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16791        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16792        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16793        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16794        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16795        GIR_EraseFromParent, /*InsnID*/0,
16796        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16797        // GIR_Coverage, 1285,
16798        GIR_Done,
16799      // Label 864: @42401
16800      GIM_Try, /*On fail goto*//*Label 865*/ 42459, // Rule ID 1286 //
16801        GIM_CheckFeatures, GIFBS_HasNEON,
16802        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
16803        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16804        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16805        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
16806        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16809        // (intrinsic_wo_chain:{ *:[v16i8] } 1115:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
16810        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv16i8,
16811        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16814        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16815        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16816        GIR_EraseFromParent, /*InsnID*/0,
16817        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16818        // GIR_Coverage, 1286,
16819        GIR_Done,
16820      // Label 865: @42459
16821      GIM_Try, /*On fail goto*//*Label 866*/ 42517, // Rule ID 1287 //
16822        GIM_CheckFeatures, GIFBS_HasNEON,
16823        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
16824        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
16825        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
16826        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
16827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16828        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16829        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16830        // (intrinsic_wo_chain:{ *:[v1i64] } 1115:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
16831        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv1i64,
16832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16834        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16835        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16836        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16837        GIR_EraseFromParent, /*InsnID*/0,
16838        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16839        // GIR_Coverage, 1287,
16840        GIR_Done,
16841      // Label 866: @42517
16842      GIM_Try, /*On fail goto*//*Label 867*/ 42575, // Rule ID 1288 //
16843        GIM_CheckFeatures, GIFBS_HasNEON,
16844        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vshiftu,
16845        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
16846        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
16847        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
16848        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16849        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16850        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16851        // (intrinsic_wo_chain:{ *:[v2i64] } 1115:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
16852        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSHLuv2i64,
16853        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16854        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16855        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16856        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16857        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16858        GIR_EraseFromParent, /*InsnID*/0,
16859        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16860        // GIR_Coverage, 1288,
16861        GIR_Done,
16862      // Label 867: @42575
16863      GIM_Try, /*On fail goto*//*Label 868*/ 42633, // Rule ID 1322 //
16864        GIM_CheckFeatures, GIFBS_HasNEON,
16865        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
16866        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
16867        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
16868        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
16869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16870        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16871        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16872        // (intrinsic_wo_chain:{ *:[v4i16] } 1108:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
16873        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i16,
16874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16875        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16876        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16877        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16878        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16879        GIR_EraseFromParent, /*InsnID*/0,
16880        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16881        // GIR_Coverage, 1322,
16882        GIR_Done,
16883      // Label 868: @42633
16884      GIM_Try, /*On fail goto*//*Label 869*/ 42691, // Rule ID 1323 //
16885        GIM_CheckFeatures, GIFBS_HasNEON,
16886        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
16887        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
16888        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
16889        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
16890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16893        // (intrinsic_wo_chain:{ *:[v2i32] } 1108:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
16894        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i32,
16895        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16898        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16899        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16900        GIR_EraseFromParent, /*InsnID*/0,
16901        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16902        // GIR_Coverage, 1323,
16903        GIR_Done,
16904      // Label 869: @42691
16905      GIM_Try, /*On fail goto*//*Label 870*/ 42749, // Rule ID 1324 //
16906        GIM_CheckFeatures, GIFBS_HasNEON,
16907        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
16908        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
16909        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
16910        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
16911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16912        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16913        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16914        // (intrinsic_wo_chain:{ *:[v8i16] } 1108:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
16915        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i16,
16916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16917        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16918        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16919        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16920        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16921        GIR_EraseFromParent, /*InsnID*/0,
16922        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16923        // GIR_Coverage, 1324,
16924        GIR_Done,
16925      // Label 870: @42749
16926      GIM_Try, /*On fail goto*//*Label 871*/ 42807, // Rule ID 1325 //
16927        GIM_CheckFeatures, GIFBS_HasNEON,
16928        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
16929        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
16930        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
16931        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
16932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16935        // (intrinsic_wo_chain:{ *:[v4i32] } 1108:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
16936        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv4i32,
16937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16940        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16941        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16942        GIR_EraseFromParent, /*InsnID*/0,
16943        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16944        // GIR_Coverage, 1325,
16945        GIR_Done,
16946      // Label 871: @42807
16947      GIM_Try, /*On fail goto*//*Label 872*/ 42865, // Rule ID 1326 //
16948        GIM_CheckFeatures, GIFBS_HasNEON,
16949        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
16950        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
16951        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
16952        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
16953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16956        // (intrinsic_wo_chain:{ *:[v8i8] } 1108:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
16957        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv8i8,
16958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16961        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16962        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16963        GIR_EraseFromParent, /*InsnID*/0,
16964        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16965        // GIR_Coverage, 1326,
16966        GIR_Done,
16967      // Label 872: @42865
16968      GIM_Try, /*On fail goto*//*Label 873*/ 42923, // Rule ID 1327 //
16969        GIM_CheckFeatures, GIFBS_HasNEON,
16970        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
16971        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
16972        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
16973        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
16974        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
16975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
16976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
16977        // (intrinsic_wo_chain:{ *:[v16i8] } 1108:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
16978        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv16i8,
16979        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
16980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
16981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
16982        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
16983        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
16984        GIR_EraseFromParent, /*InsnID*/0,
16985        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
16986        // GIR_Coverage, 1327,
16987        GIR_Done,
16988      // Label 873: @42923
16989      GIM_Try, /*On fail goto*//*Label 874*/ 42981, // Rule ID 1328 //
16990        GIM_CheckFeatures, GIFBS_HasNEON,
16991        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
16992        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
16993        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
16994        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
16995        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
16996        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
16997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
16998        // (intrinsic_wo_chain:{ *:[v1i64] } 1108:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
16999        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv1i64,
17000        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17001        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17003        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17004        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17005        GIR_EraseFromParent, /*InsnID*/0,
17006        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17007        // GIR_Coverage, 1328,
17008        GIR_Done,
17009      // Label 874: @42981
17010      GIM_Try, /*On fail goto*//*Label 875*/ 43039, // Rule ID 1329 //
17011        GIM_CheckFeatures, GIFBS_HasNEON,
17012        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshifts,
17013        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
17014        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
17015        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
17016        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17017        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17019        // (intrinsic_wo_chain:{ *:[v2i64] } 1108:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
17020        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLsv2i64,
17021        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17022        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17024        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17025        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17026        GIR_EraseFromParent, /*InsnID*/0,
17027        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17028        // GIR_Coverage, 1329,
17029        GIR_Done,
17030      // Label 875: @43039
17031      GIM_Try, /*On fail goto*//*Label 876*/ 43097, // Rule ID 1330 //
17032        GIM_CheckFeatures, GIFBS_HasNEON,
17033        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
17034        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17035        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17036        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17038        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17040        // (intrinsic_wo_chain:{ *:[v4i16] } 1109:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
17041        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i16,
17042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17045        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17046        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17047        GIR_EraseFromParent, /*InsnID*/0,
17048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17049        // GIR_Coverage, 1330,
17050        GIR_Done,
17051      // Label 876: @43097
17052      GIM_Try, /*On fail goto*//*Label 877*/ 43155, // Rule ID 1331 //
17053        GIM_CheckFeatures, GIFBS_HasNEON,
17054        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
17055        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17056        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17057        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17061        // (intrinsic_wo_chain:{ *:[v2i32] } 1109:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
17062        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i32,
17063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17066        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17067        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17068        GIR_EraseFromParent, /*InsnID*/0,
17069        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17070        // GIR_Coverage, 1331,
17071        GIR_Done,
17072      // Label 877: @43155
17073      GIM_Try, /*On fail goto*//*Label 878*/ 43213, // Rule ID 1332 //
17074        GIM_CheckFeatures, GIFBS_HasNEON,
17075        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
17076        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17077        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17078        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17079        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17080        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17082        // (intrinsic_wo_chain:{ *:[v8i16] } 1109:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
17083        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i16,
17084        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17085        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17087        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17088        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17089        GIR_EraseFromParent, /*InsnID*/0,
17090        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17091        // GIR_Coverage, 1332,
17092        GIR_Done,
17093      // Label 878: @43213
17094      GIM_Try, /*On fail goto*//*Label 879*/ 43271, // Rule ID 1333 //
17095        GIM_CheckFeatures, GIFBS_HasNEON,
17096        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
17097        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17098        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17099        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17100        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17101        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17103        // (intrinsic_wo_chain:{ *:[v4i32] } 1109:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
17104        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv4i32,
17105        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17106        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17108        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17109        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17110        GIR_EraseFromParent, /*InsnID*/0,
17111        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17112        // GIR_Coverage, 1333,
17113        GIR_Done,
17114      // Label 879: @43271
17115      GIM_Try, /*On fail goto*//*Label 880*/ 43329, // Rule ID 1334 //
17116        GIM_CheckFeatures, GIFBS_HasNEON,
17117        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
17118        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17119        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17120        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17121        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17122        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17124        // (intrinsic_wo_chain:{ *:[v8i8] } 1109:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
17125        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv8i8,
17126        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17127        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17129        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17130        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17131        GIR_EraseFromParent, /*InsnID*/0,
17132        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17133        // GIR_Coverage, 1334,
17134        GIR_Done,
17135      // Label 880: @43329
17136      GIM_Try, /*On fail goto*//*Label 881*/ 43387, // Rule ID 1335 //
17137        GIM_CheckFeatures, GIFBS_HasNEON,
17138        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
17139        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17140        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17141        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17142        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17143        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17145        // (intrinsic_wo_chain:{ *:[v16i8] } 1109:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
17146        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv16i8,
17147        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17148        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17150        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17151        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17152        GIR_EraseFromParent, /*InsnID*/0,
17153        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17154        // GIR_Coverage, 1335,
17155        GIR_Done,
17156      // Label 881: @43387
17157      GIM_Try, /*On fail goto*//*Label 882*/ 43445, // Rule ID 1336 //
17158        GIM_CheckFeatures, GIFBS_HasNEON,
17159        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
17160        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
17161        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
17162        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17163        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17164        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17166        // (intrinsic_wo_chain:{ *:[v1i64] } 1109:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
17167        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv1i64,
17168        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17169        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17171        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17172        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17173        GIR_EraseFromParent, /*InsnID*/0,
17174        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17175        // GIR_Coverage, 1336,
17176        GIR_Done,
17177      // Label 882: @43445
17178      GIM_Try, /*On fail goto*//*Label 883*/ 43503, // Rule ID 1337 //
17179        GIM_CheckFeatures, GIFBS_HasNEON,
17180        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vrshiftu,
17181        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
17182        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
17183        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
17184        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17185        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17187        // (intrinsic_wo_chain:{ *:[v2i64] } 1109:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
17188        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VRSHLuv2i64,
17189        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17190        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17192        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17193        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17194        GIR_EraseFromParent, /*InsnID*/0,
17195        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17196        // GIR_Coverage, 1337,
17197        GIR_Done,
17198      // Label 883: @43503
17199      GIM_Try, /*On fail goto*//*Label 884*/ 43561, // Rule ID 1357 //
17200        GIM_CheckFeatures, GIFBS_HasNEON,
17201        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
17202        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17203        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17204        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17206        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17208        // (intrinsic_wo_chain:{ *:[v4i16] } 1091:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
17209        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i16,
17210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17213        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17214        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17215        GIR_EraseFromParent, /*InsnID*/0,
17216        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17217        // GIR_Coverage, 1357,
17218        GIR_Done,
17219      // Label 884: @43561
17220      GIM_Try, /*On fail goto*//*Label 885*/ 43619, // Rule ID 1358 //
17221        GIM_CheckFeatures, GIFBS_HasNEON,
17222        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
17223        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17224        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17225        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17229        // (intrinsic_wo_chain:{ *:[v2i32] } 1091:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
17230        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i32,
17231        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17234        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17235        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17236        GIR_EraseFromParent, /*InsnID*/0,
17237        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17238        // GIR_Coverage, 1358,
17239        GIR_Done,
17240      // Label 885: @43619
17241      GIM_Try, /*On fail goto*//*Label 886*/ 43677, // Rule ID 1359 //
17242        GIM_CheckFeatures, GIFBS_HasNEON,
17243        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
17244        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17245        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17246        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17247        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17248        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17249        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17250        // (intrinsic_wo_chain:{ *:[v8i16] } 1091:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
17251        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i16,
17252        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17253        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17254        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17255        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17256        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17257        GIR_EraseFromParent, /*InsnID*/0,
17258        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17259        // GIR_Coverage, 1359,
17260        GIR_Done,
17261      // Label 886: @43677
17262      GIM_Try, /*On fail goto*//*Label 887*/ 43735, // Rule ID 1360 //
17263        GIM_CheckFeatures, GIFBS_HasNEON,
17264        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
17265        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17266        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17267        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17268        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17269        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17270        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17271        // (intrinsic_wo_chain:{ *:[v4i32] } 1091:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
17272        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv4i32,
17273        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17274        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17275        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17276        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17277        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17278        GIR_EraseFromParent, /*InsnID*/0,
17279        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17280        // GIR_Coverage, 1360,
17281        GIR_Done,
17282      // Label 887: @43735
17283      GIM_Try, /*On fail goto*//*Label 888*/ 43793, // Rule ID 1361 //
17284        GIM_CheckFeatures, GIFBS_HasNEON,
17285        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
17286        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17287        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17288        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17289        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17290        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17291        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17292        // (intrinsic_wo_chain:{ *:[v8i8] } 1091:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
17293        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv8i8,
17294        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17295        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17296        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17297        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17298        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17299        GIR_EraseFromParent, /*InsnID*/0,
17300        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17301        // GIR_Coverage, 1361,
17302        GIR_Done,
17303      // Label 888: @43793
17304      GIM_Try, /*On fail goto*//*Label 889*/ 43851, // Rule ID 1362 //
17305        GIM_CheckFeatures, GIFBS_HasNEON,
17306        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
17307        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17308        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17309        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17310        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17311        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17312        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17313        // (intrinsic_wo_chain:{ *:[v16i8] } 1091:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
17314        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv16i8,
17315        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17316        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17317        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17318        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17319        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17320        GIR_EraseFromParent, /*InsnID*/0,
17321        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17322        // GIR_Coverage, 1362,
17323        GIR_Done,
17324      // Label 889: @43851
17325      GIM_Try, /*On fail goto*//*Label 890*/ 43909, // Rule ID 1363 //
17326        GIM_CheckFeatures, GIFBS_HasNEON,
17327        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
17328        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
17329        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
17330        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17331        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17332        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17333        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17334        // (intrinsic_wo_chain:{ *:[v1i64] } 1091:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
17335        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv1i64,
17336        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17337        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17338        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17339        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17340        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17341        GIR_EraseFromParent, /*InsnID*/0,
17342        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17343        // GIR_Coverage, 1363,
17344        GIR_Done,
17345      // Label 890: @43909
17346      GIM_Try, /*On fail goto*//*Label 891*/ 43967, // Rule ID 1364 //
17347        GIM_CheckFeatures, GIFBS_HasNEON,
17348        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshifts,
17349        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
17350        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
17351        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
17352        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17353        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17354        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17355        // (intrinsic_wo_chain:{ *:[v2i64] } 1091:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
17356        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLsv2i64,
17357        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17358        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17359        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17360        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17361        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17362        GIR_EraseFromParent, /*InsnID*/0,
17363        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17364        // GIR_Coverage, 1364,
17365        GIR_Done,
17366      // Label 891: @43967
17367      GIM_Try, /*On fail goto*//*Label 892*/ 44025, // Rule ID 1365 //
17368        GIM_CheckFeatures, GIFBS_HasNEON,
17369        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
17370        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17371        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17372        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17373        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17374        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17375        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17376        // (intrinsic_wo_chain:{ *:[v4i16] } 1093:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
17377        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i16,
17378        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17379        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17380        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17381        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17382        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17383        GIR_EraseFromParent, /*InsnID*/0,
17384        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17385        // GIR_Coverage, 1365,
17386        GIR_Done,
17387      // Label 892: @44025
17388      GIM_Try, /*On fail goto*//*Label 893*/ 44083, // Rule ID 1366 //
17389        GIM_CheckFeatures, GIFBS_HasNEON,
17390        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
17391        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17392        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17393        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17394        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17395        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17396        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17397        // (intrinsic_wo_chain:{ *:[v2i32] } 1093:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
17398        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i32,
17399        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17400        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17401        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17402        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17403        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17404        GIR_EraseFromParent, /*InsnID*/0,
17405        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17406        // GIR_Coverage, 1366,
17407        GIR_Done,
17408      // Label 893: @44083
17409      GIM_Try, /*On fail goto*//*Label 894*/ 44141, // Rule ID 1367 //
17410        GIM_CheckFeatures, GIFBS_HasNEON,
17411        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
17412        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17413        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17414        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17415        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17416        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17417        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17418        // (intrinsic_wo_chain:{ *:[v8i16] } 1093:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
17419        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i16,
17420        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17421        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17422        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17423        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17424        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17425        GIR_EraseFromParent, /*InsnID*/0,
17426        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17427        // GIR_Coverage, 1367,
17428        GIR_Done,
17429      // Label 894: @44141
17430      GIM_Try, /*On fail goto*//*Label 895*/ 44199, // Rule ID 1368 //
17431        GIM_CheckFeatures, GIFBS_HasNEON,
17432        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
17433        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17434        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17435        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17436        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17437        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17438        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17439        // (intrinsic_wo_chain:{ *:[v4i32] } 1093:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
17440        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv4i32,
17441        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17442        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17443        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17444        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17445        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17446        GIR_EraseFromParent, /*InsnID*/0,
17447        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17448        // GIR_Coverage, 1368,
17449        GIR_Done,
17450      // Label 895: @44199
17451      GIM_Try, /*On fail goto*//*Label 896*/ 44257, // Rule ID 1369 //
17452        GIM_CheckFeatures, GIFBS_HasNEON,
17453        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
17454        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17455        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17456        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17457        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17458        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17459        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17460        // (intrinsic_wo_chain:{ *:[v8i8] } 1093:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
17461        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv8i8,
17462        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17463        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17464        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17465        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17466        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17467        GIR_EraseFromParent, /*InsnID*/0,
17468        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17469        // GIR_Coverage, 1369,
17470        GIR_Done,
17471      // Label 896: @44257
17472      GIM_Try, /*On fail goto*//*Label 897*/ 44315, // Rule ID 1370 //
17473        GIM_CheckFeatures, GIFBS_HasNEON,
17474        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
17475        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17476        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17477        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17478        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17479        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17480        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17481        // (intrinsic_wo_chain:{ *:[v16i8] } 1093:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
17482        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv16i8,
17483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17484        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17485        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17486        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17487        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17488        GIR_EraseFromParent, /*InsnID*/0,
17489        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17490        // GIR_Coverage, 1370,
17491        GIR_Done,
17492      // Label 897: @44315
17493      GIM_Try, /*On fail goto*//*Label 898*/ 44373, // Rule ID 1371 //
17494        GIM_CheckFeatures, GIFBS_HasNEON,
17495        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
17496        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
17497        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
17498        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17502        // (intrinsic_wo_chain:{ *:[v1i64] } 1093:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
17503        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv1i64,
17504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17507        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17508        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17509        GIR_EraseFromParent, /*InsnID*/0,
17510        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17511        // GIR_Coverage, 1371,
17512        GIR_Done,
17513      // Label 898: @44373
17514      GIM_Try, /*On fail goto*//*Label 899*/ 44431, // Rule ID 1372 //
17515        GIM_CheckFeatures, GIFBS_HasNEON,
17516        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqshiftu,
17517        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
17518        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
17519        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
17520        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17521        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17522        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17523        // (intrinsic_wo_chain:{ *:[v2i64] } 1093:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
17524        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQSHLuv2i64,
17525        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17526        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17527        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17528        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17529        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17530        GIR_EraseFromParent, /*InsnID*/0,
17531        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17532        // GIR_Coverage, 1372,
17533        GIR_Done,
17534      // Label 899: @44431
17535      GIM_Try, /*On fail goto*//*Label 900*/ 44489, // Rule ID 1406 //
17536        GIM_CheckFeatures, GIFBS_HasNEON,
17537        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
17538        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17539        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17540        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17541        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17542        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17543        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17544        // (intrinsic_wo_chain:{ *:[v4i16] } 1086:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
17545        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i16,
17546        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17547        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17548        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17549        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17550        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17551        GIR_EraseFromParent, /*InsnID*/0,
17552        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17553        // GIR_Coverage, 1406,
17554        GIR_Done,
17555      // Label 900: @44489
17556      GIM_Try, /*On fail goto*//*Label 901*/ 44547, // Rule ID 1407 //
17557        GIM_CheckFeatures, GIFBS_HasNEON,
17558        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
17559        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17560        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17561        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17562        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17563        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17565        // (intrinsic_wo_chain:{ *:[v2i32] } 1086:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
17566        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i32,
17567        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17568        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17569        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17570        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17571        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17572        GIR_EraseFromParent, /*InsnID*/0,
17573        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17574        // GIR_Coverage, 1407,
17575        GIR_Done,
17576      // Label 901: @44547
17577      GIM_Try, /*On fail goto*//*Label 902*/ 44605, // Rule ID 1408 //
17578        GIM_CheckFeatures, GIFBS_HasNEON,
17579        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
17580        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17581        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17582        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17583        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17584        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17585        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17586        // (intrinsic_wo_chain:{ *:[v8i16] } 1086:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
17587        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i16,
17588        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17589        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17590        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17591        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17592        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17593        GIR_EraseFromParent, /*InsnID*/0,
17594        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17595        // GIR_Coverage, 1408,
17596        GIR_Done,
17597      // Label 902: @44605
17598      GIM_Try, /*On fail goto*//*Label 903*/ 44663, // Rule ID 1409 //
17599        GIM_CheckFeatures, GIFBS_HasNEON,
17600        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
17601        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17602        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17603        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17604        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17605        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17606        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17607        // (intrinsic_wo_chain:{ *:[v4i32] } 1086:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
17608        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv4i32,
17609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17611        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17612        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17613        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17614        GIR_EraseFromParent, /*InsnID*/0,
17615        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17616        // GIR_Coverage, 1409,
17617        GIR_Done,
17618      // Label 903: @44663
17619      GIM_Try, /*On fail goto*//*Label 904*/ 44721, // Rule ID 1410 //
17620        GIM_CheckFeatures, GIFBS_HasNEON,
17621        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
17622        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17623        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17624        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17625        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17626        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17627        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17628        // (intrinsic_wo_chain:{ *:[v8i8] } 1086:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
17629        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv8i8,
17630        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17631        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17632        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17633        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17634        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17635        GIR_EraseFromParent, /*InsnID*/0,
17636        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17637        // GIR_Coverage, 1410,
17638        GIR_Done,
17639      // Label 904: @44721
17640      GIM_Try, /*On fail goto*//*Label 905*/ 44779, // Rule ID 1411 //
17641        GIM_CheckFeatures, GIFBS_HasNEON,
17642        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
17643        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17644        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17645        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17646        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17647        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17648        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17649        // (intrinsic_wo_chain:{ *:[v16i8] } 1086:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
17650        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv16i8,
17651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17652        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17653        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17654        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17655        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17656        GIR_EraseFromParent, /*InsnID*/0,
17657        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17658        // GIR_Coverage, 1411,
17659        GIR_Done,
17660      // Label 905: @44779
17661      GIM_Try, /*On fail goto*//*Label 906*/ 44837, // Rule ID 1412 //
17662        GIM_CheckFeatures, GIFBS_HasNEON,
17663        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
17664        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
17665        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
17666        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17667        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17668        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17670        // (intrinsic_wo_chain:{ *:[v1i64] } 1086:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
17671        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv1i64,
17672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17674        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17675        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17676        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17677        GIR_EraseFromParent, /*InsnID*/0,
17678        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17679        // GIR_Coverage, 1412,
17680        GIR_Done,
17681      // Label 906: @44837
17682      GIM_Try, /*On fail goto*//*Label 907*/ 44895, // Rule ID 1413 //
17683        GIM_CheckFeatures, GIFBS_HasNEON,
17684        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshifts,
17685        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
17686        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
17687        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
17688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17690        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17691        // (intrinsic_wo_chain:{ *:[v2i64] } 1086:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
17692        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLsv2i64,
17693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17696        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17697        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17698        GIR_EraseFromParent, /*InsnID*/0,
17699        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17700        // GIR_Coverage, 1413,
17701        GIR_Done,
17702      // Label 907: @44895
17703      GIM_Try, /*On fail goto*//*Label 908*/ 44953, // Rule ID 1414 //
17704        GIM_CheckFeatures, GIFBS_HasNEON,
17705        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
17706        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
17707        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
17708        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
17709        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17711        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17712        // (intrinsic_wo_chain:{ *:[v4i16] } 1087:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)  =>  (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
17713        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i16,
17714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17716        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17717        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17718        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17719        GIR_EraseFromParent, /*InsnID*/0,
17720        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17721        // GIR_Coverage, 1414,
17722        GIR_Done,
17723      // Label 908: @44953
17724      GIM_Try, /*On fail goto*//*Label 909*/ 45011, // Rule ID 1415 //
17725        GIM_CheckFeatures, GIFBS_HasNEON,
17726        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
17727        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
17728        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
17729        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
17730        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17732        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17733        // (intrinsic_wo_chain:{ *:[v2i32] } 1087:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)  =>  (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
17734        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i32,
17735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17736        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17737        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17738        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17739        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17740        GIR_EraseFromParent, /*InsnID*/0,
17741        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17742        // GIR_Coverage, 1415,
17743        GIR_Done,
17744      // Label 909: @45011
17745      GIM_Try, /*On fail goto*//*Label 910*/ 45069, // Rule ID 1416 //
17746        GIM_CheckFeatures, GIFBS_HasNEON,
17747        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
17748        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
17749        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
17750        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
17751        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17752        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17753        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17754        // (intrinsic_wo_chain:{ *:[v8i16] } 1087:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)  =>  (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
17755        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i16,
17756        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17757        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17758        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17759        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17760        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17761        GIR_EraseFromParent, /*InsnID*/0,
17762        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17763        // GIR_Coverage, 1416,
17764        GIR_Done,
17765      // Label 910: @45069
17766      GIM_Try, /*On fail goto*//*Label 911*/ 45127, // Rule ID 1417 //
17767        GIM_CheckFeatures, GIFBS_HasNEON,
17768        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
17769        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17770        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17771        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17774        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17775        // (intrinsic_wo_chain:{ *:[v4i32] } 1087:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)  =>  (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
17776        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv4i32,
17777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17778        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17780        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17781        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17782        GIR_EraseFromParent, /*InsnID*/0,
17783        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17784        // GIR_Coverage, 1417,
17785        GIR_Done,
17786      // Label 911: @45127
17787      GIM_Try, /*On fail goto*//*Label 912*/ 45185, // Rule ID 1418 //
17788        GIM_CheckFeatures, GIFBS_HasNEON,
17789        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
17790        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
17791        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
17792        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
17793        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17796        // (intrinsic_wo_chain:{ *:[v8i8] } 1087:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)  =>  (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
17797        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv8i8,
17798        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17799        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17801        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17802        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17803        GIR_EraseFromParent, /*InsnID*/0,
17804        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17805        // GIR_Coverage, 1418,
17806        GIR_Done,
17807      // Label 912: @45185
17808      GIM_Try, /*On fail goto*//*Label 913*/ 45243, // Rule ID 1419 //
17809        GIM_CheckFeatures, GIFBS_HasNEON,
17810        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
17811        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17812        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17813        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17815        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17816        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17817        // (intrinsic_wo_chain:{ *:[v16i8] } 1087:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)  =>  (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
17818        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv16i8,
17819        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17820        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17821        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17822        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17823        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17824        GIR_EraseFromParent, /*InsnID*/0,
17825        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17826        // GIR_Coverage, 1419,
17827        GIR_Done,
17828      // Label 913: @45243
17829      GIM_Try, /*On fail goto*//*Label 914*/ 45301, // Rule ID 1420 //
17830        GIM_CheckFeatures, GIFBS_HasNEON,
17831        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
17832        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
17833        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
17834        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
17835        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
17836        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
17837        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
17838        // (intrinsic_wo_chain:{ *:[v1i64] } 1087:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)  =>  (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
17839        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv1i64,
17840        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17841        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17843        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17844        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17845        GIR_EraseFromParent, /*InsnID*/0,
17846        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17847        // GIR_Coverage, 1420,
17848        GIR_Done,
17849      // Label 914: @45301
17850      GIM_Try, /*On fail goto*//*Label 915*/ 45359, // Rule ID 1421 //
17851        GIM_CheckFeatures, GIFBS_HasNEON,
17852        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vqrshiftu,
17853        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
17854        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
17855        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
17856        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17857        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17858        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17859        // (intrinsic_wo_chain:{ *:[v2i64] } 1087:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)  =>  (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
17860        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VQRSHLuv2i64,
17861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
17863        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
17864        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17865        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17866        GIR_EraseFromParent, /*InsnID*/0,
17867        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17868        // GIR_Coverage, 1421,
17869        GIR_Done,
17870      // Label 915: @45359
17871      GIM_Try, /*On fail goto*//*Label 916*/ 45411, // Rule ID 1686 //
17872        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
17873        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aesd,
17874        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17875        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17876        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17877        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17878        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17879        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17880        // (intrinsic_wo_chain:{ *:[v16i8] } 1000:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)  =>  (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
17881        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESD,
17882        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17885        GIR_EraseFromParent, /*InsnID*/0,
17886        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17887        // GIR_Coverage, 1686,
17888        GIR_Done,
17889      // Label 916: @45411
17890      GIM_Try, /*On fail goto*//*Label 917*/ 45463, // Rule ID 1687 //
17891        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
17892        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_aese,
17893        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
17894        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
17895        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
17896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17898        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17899        // (intrinsic_wo_chain:{ *:[v16i8] } 1001:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)  =>  (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
17900        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::AESE,
17901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17903        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17904        GIR_EraseFromParent, /*InsnID*/0,
17905        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17906        // GIR_Coverage, 1687,
17907        GIR_Done,
17908      // Label 917: @45463
17909      GIM_Try, /*On fail goto*//*Label 918*/ 45515, // Rule ID 1690 //
17910        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
17911        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su1,
17912        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17913        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17914        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17918        // (intrinsic_wo_chain:{ *:[v4i32] } 1010:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
17919        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU1,
17920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17923        GIR_EraseFromParent, /*InsnID*/0,
17924        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17925        // GIR_Coverage, 1690,
17926        GIR_Done,
17927      // Label 918: @45515
17928      GIM_Try, /*On fail goto*//*Label 919*/ 45567, // Rule ID 1691 //
17929        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
17930        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su0,
17931        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
17932        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
17933        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
17934        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
17935        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
17936        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
17937        // (intrinsic_wo_chain:{ *:[v4i32] } 1013:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
17938        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU0,
17939        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
17940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
17941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vm
17942        GIR_EraseFromParent, /*InsnID*/0,
17943        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17944        // GIR_Coverage, 1691,
17945        GIR_Done,
17946      // Label 919: @45567
17947      GIM_Try, /*On fail goto*//*Label 920*/ 45628, // Rule ID 1706 //
17948        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
17949        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16,
17950        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17951        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17952        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
17955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
17956        // (intrinsic_wo_chain:{ *:[i32] } 1191:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS)  =>  (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
17957        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SXTAB16,
17958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
17960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
17961        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17962        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17963        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17964        GIR_EraseFromParent, /*InsnID*/0,
17965        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17966        // GIR_Coverage, 1706,
17967        GIR_Done,
17968      // Label 920: @45628
17969      GIM_Try, /*On fail goto*//*Label 921*/ 45689, // Rule ID 1711 //
17970        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
17971        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uxtab16,
17972        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17973        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17974        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
17977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
17978        // (intrinsic_wo_chain:{ *:[i32] } 1216:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS)  =>  (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
17979        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB16,
17980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
17981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // LHS
17982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // RHS
17983        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
17984        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
17985        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
17986        GIR_EraseFromParent, /*InsnID*/0,
17987        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
17988        // GIR_Coverage, 1711,
17989        GIR_Done,
17990      // Label 921: @45689
17991      GIM_Try, /*On fail goto*//*Label 922*/ 45747, // Rule ID 1737 //
17992        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
17993        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuad,
17994        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
17995        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
17996        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
17997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
17998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
17999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18000        // (intrinsic_wo_chain:{ *:[i32] } 1167:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18001        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUAD,
18002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18005        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18006        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18007        GIR_EraseFromParent, /*InsnID*/0,
18008        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18009        // GIR_Coverage, 1737,
18010        GIR_Done,
18011      // Label 922: @45747
18012      GIM_Try, /*On fail goto*//*Label 923*/ 45805, // Rule ID 1738 //
18013        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
18014        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smuadx,
18015        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18016        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18017        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18018        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18021        // (intrinsic_wo_chain:{ *:[i32] } 1168:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18022        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUADX,
18023        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18026        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18027        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18028        GIR_EraseFromParent, /*InsnID*/0,
18029        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18030        // GIR_Coverage, 1738,
18031        GIR_Done,
18032      // Label 923: @45805
18033      GIM_Try, /*On fail goto*//*Label 924*/ 45863, // Rule ID 1739 //
18034        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
18035        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusd,
18036        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18037        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18038        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18039        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18040        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18042        // (intrinsic_wo_chain:{ *:[i32] } 1175:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18043        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSD,
18044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18045        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18047        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18048        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18049        GIR_EraseFromParent, /*InsnID*/0,
18050        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18051        // GIR_Coverage, 1739,
18052        GIR_Done,
18053      // Label 924: @45863
18054      GIM_Try, /*On fail goto*//*Label 925*/ 45921, // Rule ID 1740 //
18055        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
18056        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smusdx,
18057        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18058        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18059        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18063        // (intrinsic_wo_chain:{ *:[i32] } 1176:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18064        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMUSDX,
18065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18068        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18069        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18070        GIR_EraseFromParent, /*InsnID*/0,
18071        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18072        // GIR_Coverage, 1740,
18073        GIR_Done,
18074      // Label 925: @45921
18075      GIM_Try, /*On fail goto*//*Label 926*/ 45979, // Rule ID 1797 //
18076        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18077        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb,
18078        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18079        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18080        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18081        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
18082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18084        // (intrinsic_wo_chain:{ *:[i32] } 1169:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
18085        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBB,
18086        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18087        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18089        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18090        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18091        GIR_EraseFromParent, /*InsnID*/0,
18092        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18093        // GIR_Coverage, 1797,
18094        GIR_Done,
18095      // Label 926: @45979
18096      GIM_Try, /*On fail goto*//*Label 927*/ 46037, // Rule ID 1798 //
18097        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18098        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt,
18099        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18100        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18101        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18102        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
18103        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18104        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18105        // (intrinsic_wo_chain:{ *:[i32] } 1170:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
18106        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULBT,
18107        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18108        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18109        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18110        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18111        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18112        GIR_EraseFromParent, /*InsnID*/0,
18113        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18114        // GIR_Coverage, 1798,
18115        GIR_Done,
18116      // Label 927: @46037
18117      GIM_Try, /*On fail goto*//*Label 928*/ 46095, // Rule ID 1799 //
18118        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18119        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb,
18120        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18121        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18122        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18123        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
18124        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18125        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18126        // (intrinsic_wo_chain:{ *:[i32] } 1171:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
18127        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTB,
18128        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18129        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18130        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18131        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18132        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18133        GIR_EraseFromParent, /*InsnID*/0,
18134        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18135        // GIR_Coverage, 1799,
18136        GIR_Done,
18137      // Label 928: @46095
18138      GIM_Try, /*On fail goto*//*Label 929*/ 46153, // Rule ID 1800 //
18139        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18140        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt,
18141        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18142        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18143        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18144        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
18145        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18146        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18147        // (intrinsic_wo_chain:{ *:[i32] } 1172:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
18148        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULTT,
18149        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18150        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18151        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18152        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18153        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18154        GIR_EraseFromParent, /*InsnID*/0,
18155        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18156        // GIR_Coverage, 1800,
18157        GIR_Done,
18158      // Label 929: @46153
18159      GIM_Try, /*On fail goto*//*Label 930*/ 46211, // Rule ID 1801 //
18160        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18161        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb,
18162        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18163        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18164        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18165        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
18166        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18167        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18168        // (intrinsic_wo_chain:{ *:[i32] } 1173:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
18169        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWB,
18170        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18171        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18172        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18173        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18174        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18175        GIR_EraseFromParent, /*InsnID*/0,
18176        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18177        // GIR_Coverage, 1801,
18178        GIR_Done,
18179      // Label 930: @46211
18180      GIM_Try, /*On fail goto*//*Label 931*/ 46269, // Rule ID 1802 //
18181        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18182        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt,
18183        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18184        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18185        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18186        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
18187        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18188        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18189        // (intrinsic_wo_chain:{ *:[i32] } 1174:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)  =>  (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
18190        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMULWT,
18191        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18192        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18193        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18194        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18195        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18196        GIR_EraseFromParent, /*InsnID*/0,
18197        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18198        // GIR_Coverage, 1802,
18199        GIR_Done,
18200      // Label 931: @46269
18201      GIM_Try, /*On fail goto*//*Label 932*/ 46330, // Rule ID 1900 //
18202        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18203        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sxtab16,
18204        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18205        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18206        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18207        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18208        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18209        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18210        // (intrinsic_wo_chain:{ *:[i32] } 1191:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
18211        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SXTAB16,
18212        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18213        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18214        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18215        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
18216        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18217        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18218        GIR_EraseFromParent, /*InsnID*/0,
18219        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18220        // GIR_Coverage, 1900,
18221        GIR_Done,
18222      // Label 932: @46330
18223      GIM_Try, /*On fail goto*//*Label 933*/ 46388, // Rule ID 1925 //
18224        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18225        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qadd,
18226        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18227        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18228        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18230        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18231        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18232        // (intrinsic_wo_chain:{ *:[i32] } 1134:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
18233        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QADD,
18234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18235        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
18236        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
18237        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18238        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18239        GIR_EraseFromParent, /*InsnID*/0,
18240        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18241        // GIR_Coverage, 1925,
18242        GIR_Done,
18243      // Label 933: @46388
18244      GIM_Try, /*On fail goto*//*Label 934*/ 46446, // Rule ID 1926 //
18245        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18246        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_qsub,
18247        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18248        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18249        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18250        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18251        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18253        // (intrinsic_wo_chain:{ *:[i32] } 1139:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)  =>  (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
18254        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2QSUB,
18255        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18256        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
18257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
18258        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18259        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18260        GIR_EraseFromParent, /*InsnID*/0,
18261        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18262        // GIR_Coverage, 1926,
18263        GIR_Done,
18264      // Label 934: @46446
18265      GIM_Try, /*On fail goto*//*Label 935*/ 46504, // Rule ID 1946 //
18266        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18267        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbb,
18268        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18269        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18270        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18271        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18272        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18273        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18274        // (intrinsic_wo_chain:{ *:[i32] } 1169:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18275        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBB,
18276        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18277        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18278        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18279        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18280        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18281        GIR_EraseFromParent, /*InsnID*/0,
18282        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18283        // GIR_Coverage, 1946,
18284        GIR_Done,
18285      // Label 935: @46504
18286      GIM_Try, /*On fail goto*//*Label 936*/ 46562, // Rule ID 1947 //
18287        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18288        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulbt,
18289        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18290        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18291        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18292        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18293        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18294        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18295        // (intrinsic_wo_chain:{ *:[i32] } 1170:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18296        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULBT,
18297        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18298        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18299        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18300        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18301        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18302        GIR_EraseFromParent, /*InsnID*/0,
18303        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18304        // GIR_Coverage, 1947,
18305        GIR_Done,
18306      // Label 936: @46562
18307      GIM_Try, /*On fail goto*//*Label 937*/ 46620, // Rule ID 1948 //
18308        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18309        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultb,
18310        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18311        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18312        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18313        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18314        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18316        // (intrinsic_wo_chain:{ *:[i32] } 1171:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18317        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTB,
18318        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18319        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18320        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18321        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18322        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18323        GIR_EraseFromParent, /*InsnID*/0,
18324        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18325        // GIR_Coverage, 1948,
18326        GIR_Done,
18327      // Label 937: @46620
18328      GIM_Try, /*On fail goto*//*Label 938*/ 46678, // Rule ID 1949 //
18329        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18330        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smultt,
18331        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18332        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18333        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18334        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18337        // (intrinsic_wo_chain:{ *:[i32] } 1172:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18338        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULTT,
18339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18342        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18343        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18344        GIR_EraseFromParent, /*InsnID*/0,
18345        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18346        // GIR_Coverage, 1949,
18347        GIR_Done,
18348      // Label 938: @46678
18349      GIM_Try, /*On fail goto*//*Label 939*/ 46736, // Rule ID 1950 //
18350        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18351        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwb,
18352        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18353        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18354        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18355        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18356        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18357        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18358        // (intrinsic_wo_chain:{ *:[i32] } 1173:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18359        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWB,
18360        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18361        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18362        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18363        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18364        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18365        GIR_EraseFromParent, /*InsnID*/0,
18366        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18367        // GIR_Coverage, 1950,
18368        GIR_Done,
18369      // Label 939: @46736
18370      GIM_Try, /*On fail goto*//*Label 940*/ 46794, // Rule ID 1951 //
18371        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18372        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smulwt,
18373        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18374        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18375        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18376        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18377        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18378        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18379        // (intrinsic_wo_chain:{ *:[i32] } 1174:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18380        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMULWT,
18381        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18382        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18383        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18384        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18385        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18386        GIR_EraseFromParent, /*InsnID*/0,
18387        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18388        // GIR_Coverage, 1951,
18389        GIR_Done,
18390      // Label 940: @46794
18391      GIM_Reject,
18392    // Label 585: @46795
18393    GIM_Try, /*On fail goto*//*Label 941*/ 49623,
18394      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
18395      GIM_Try, /*On fail goto*//*Label 942*/ 46870, // Rule ID 148 //
18396        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
18397        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
18398        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18399        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18400        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18401        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18402        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
18403        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18404        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18405        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18406        // (intrinsic_wo_chain:{ *:[i32] } 1210:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
18407        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USADA8,
18408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18409        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18410        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18411        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18412        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18413        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18414        GIR_EraseFromParent, /*InsnID*/0,
18415        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18416        // GIR_Coverage, 148,
18417        GIR_Done,
18418      // Label 942: @46870
18419      GIM_Try, /*On fail goto*//*Label 943*/ 46940, // Rule ID 473 //
18420        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18421        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usada8,
18422        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18423        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18424        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18425        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18426        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18427        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18428        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18429        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
18430        // (intrinsic_wo_chain:{ *:[i32] } 1210:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
18431        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USADA8,
18432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18434        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18435        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18436        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18437        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18438        GIR_EraseFromParent, /*InsnID*/0,
18439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18440        // GIR_Coverage, 473,
18441        GIR_Done,
18442      // Label 943: @46940
18443      GIM_Try, /*On fail goto*//*Label 944*/ 47010, // Rule ID 532 //
18444        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18445        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
18446        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18449        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18450        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18451        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18452        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18453        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
18454        // (intrinsic_wo_chain:{ *:[i32] } 1155:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
18455        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAD,
18456        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18457        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18458        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18459        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18460        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18461        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18462        GIR_EraseFromParent, /*InsnID*/0,
18463        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18464        // GIR_Coverage, 532,
18465        GIR_Done,
18466      // Label 944: @47010
18467      GIM_Try, /*On fail goto*//*Label 945*/ 47080, // Rule ID 533 //
18468        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18469        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
18470        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18471        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18472        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18473        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18474        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18475        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18476        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18477        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
18478        // (intrinsic_wo_chain:{ *:[i32] } 1156:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
18479        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLADX,
18480        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18481        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18482        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18483        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18484        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18485        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18486        GIR_EraseFromParent, /*InsnID*/0,
18487        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18488        // GIR_Coverage, 533,
18489        GIR_Done,
18490      // Label 945: @47080
18491      GIM_Try, /*On fail goto*//*Label 946*/ 47150, // Rule ID 534 //
18492        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18493        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
18494        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18495        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18496        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18497        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18498        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18499        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18500        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18501        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
18502        // (intrinsic_wo_chain:{ *:[i32] } 1163:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
18503        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSD,
18504        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18505        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18506        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18507        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18508        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18509        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18510        GIR_EraseFromParent, /*InsnID*/0,
18511        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18512        // GIR_Coverage, 534,
18513        GIR_Done,
18514      // Label 946: @47150
18515      GIM_Try, /*On fail goto*//*Label 947*/ 47220, // Rule ID 535 //
18516        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18517        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
18518        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18519        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18520        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18521        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18522        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18523        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
18524        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
18525        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::rGPRRegClassID,
18526        // (intrinsic_wo_chain:{ *:[i32] } 1164:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)  =>  (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
18527        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLSDX,
18528        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18532        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18533        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18534        GIR_EraseFromParent, /*InsnID*/0,
18535        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18536        // GIR_Coverage, 535,
18537        GIR_Done,
18538      // Label 947: @47220
18539      GIM_Try, /*On fail goto*//*Label 948*/ 47284, // Rule ID 937 //
18540        GIM_CheckFeatures, GIFBS_HasDotProd,
18541        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot,
18542        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18543        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18544        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18545        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
18546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18548        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18549        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
18550        // (intrinsic_wo_chain:{ *:[v2i32] } 1015:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18551        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTD,
18552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
18553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
18554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18555        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
18556        GIR_EraseFromParent, /*InsnID*/0,
18557        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18558        // GIR_Coverage, 937,
18559        GIR_Done,
18560      // Label 948: @47284
18561      GIM_Try, /*On fail goto*//*Label 949*/ 47348, // Rule ID 938 //
18562        GIM_CheckFeatures, GIFBS_HasDotProd,
18563        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot,
18564        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
18565        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
18566        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18567        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
18568        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18570        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18571        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
18572        // (intrinsic_wo_chain:{ *:[v2i32] } 1004:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18573        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTD,
18574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
18575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
18576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18577        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
18578        GIR_EraseFromParent, /*InsnID*/0,
18579        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18580        // GIR_Coverage, 938,
18581        GIR_Done,
18582      // Label 949: @47348
18583      GIM_Try, /*On fail goto*//*Label 950*/ 47412, // Rule ID 939 //
18584        GIM_CheckFeatures, GIFBS_HasDotProd,
18585        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_udot,
18586        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18587        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18588        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
18589        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
18590        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18591        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18592        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18593        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
18594        // (intrinsic_wo_chain:{ *:[v4i32] } 1015:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
18595        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUDOTQ,
18596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
18597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
18598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18599        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
18600        GIR_EraseFromParent, /*InsnID*/0,
18601        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18602        // GIR_Coverage, 939,
18603        GIR_Done,
18604      // Label 950: @47412
18605      GIM_Try, /*On fail goto*//*Label 951*/ 47476, // Rule ID 940 //
18606        GIM_CheckFeatures, GIFBS_HasDotProd,
18607        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sdot,
18608        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18609        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18610        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
18611        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
18612        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18613        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18614        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18615        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
18616        // (intrinsic_wo_chain:{ *:[v4i32] } 1004:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
18617        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSDOTQ,
18618        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
18619        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vd
18620        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18621        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
18622        GIR_EraseFromParent, /*InsnID*/0,
18623        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18624        // GIR_Coverage, 940,
18625        GIR_Done,
18626      // Label 951: @47476
18627      GIM_Try, /*On fail goto*//*Label 952*/ 47546, // Rule ID 1661 //
18628        GIM_CheckFeatures, GIFBS_HasNEON,
18629        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vtbx1,
18630        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
18631        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
18632        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
18633        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
18634        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
18635        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
18636        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
18637        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
18638        // (intrinsic_wo_chain:{ *:[v8i8] } 1130:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
18639        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VTBX1,
18640        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18641        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // orig
18642        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18643        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
18644        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18645        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18646        GIR_EraseFromParent, /*InsnID*/0,
18647        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18648        // GIR_Coverage, 1661,
18649        GIR_Done,
18650      // Label 952: @47546
18651      GIM_Try, /*On fail goto*//*Label 953*/ 47610, // Rule ID 1692 //
18652        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
18653        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha1su0,
18654        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18655        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18656        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18657        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
18658        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18659        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18660        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18661        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
18662        // (intrinsic_wo_chain:{ *:[v4i32] } 1009:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
18663        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA1SU0,
18664        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18665        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
18666        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18667        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
18668        GIR_EraseFromParent, /*InsnID*/0,
18669        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18670        // GIR_Coverage, 1692,
18671        GIR_Done,
18672      // Label 953: @47610
18673      GIM_Try, /*On fail goto*//*Label 954*/ 47674, // Rule ID 1693 //
18674        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
18675        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h,
18676        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18677        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18678        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18679        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
18680        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18681        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18682        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18683        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
18684        // (intrinsic_wo_chain:{ *:[v4i32] } 1011:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
18685        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H,
18686        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18687        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
18688        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18689        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
18690        GIR_EraseFromParent, /*InsnID*/0,
18691        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18692        // GIR_Coverage, 1693,
18693        GIR_Done,
18694      // Label 954: @47674
18695      GIM_Try, /*On fail goto*//*Label 955*/ 47738, // Rule ID 1694 //
18696        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
18697        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256h2,
18698        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18699        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18700        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18701        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
18702        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18703        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18704        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18705        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
18706        // (intrinsic_wo_chain:{ *:[v4i32] } 1012:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
18707        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256H2,
18708        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18709        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
18710        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18711        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
18712        GIR_EraseFromParent, /*InsnID*/0,
18713        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18714        // GIR_Coverage, 1694,
18715        GIR_Done,
18716      // Label 955: @47738
18717      GIM_Try, /*On fail goto*//*Label 956*/ 47802, // Rule ID 1695 //
18718        GIM_CheckFeatures, GIFBS_HasCrypto_HasV8,
18719        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_sha256su1,
18720        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
18721        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
18722        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
18723        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
18724        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
18725        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
18726        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
18727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
18728        // (intrinsic_wo_chain:{ *:[v4i32] } 1014:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
18729        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SHA256SU1,
18730        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
18731        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
18732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
18733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
18734        GIR_EraseFromParent, /*InsnID*/0,
18735        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18736        // GIR_Coverage, 1695,
18737        GIR_Done,
18738      // Label 956: @47802
18739      GIM_Try, /*On fail goto*//*Label 957*/ 47872, // Rule ID 1729 //
18740        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
18741        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlad,
18742        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18743        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18744        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18745        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18746        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18747        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18748        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18749        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18750        // (intrinsic_wo_chain:{ *:[i32] } 1155:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
18751        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAD,
18752        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18753        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18754        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18755        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18756        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18757        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18758        GIR_EraseFromParent, /*InsnID*/0,
18759        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18760        // GIR_Coverage, 1729,
18761        GIR_Done,
18762      // Label 957: @47872
18763      GIM_Try, /*On fail goto*//*Label 958*/ 47942, // Rule ID 1730 //
18764        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
18765        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smladx,
18766        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18767        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18768        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18769        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18770        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18771        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18772        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18773        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18774        // (intrinsic_wo_chain:{ *:[i32] } 1156:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
18775        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLADX,
18776        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18777        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18778        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18779        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18780        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18781        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18782        GIR_EraseFromParent, /*InsnID*/0,
18783        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18784        // GIR_Coverage, 1730,
18785        GIR_Done,
18786      // Label 958: @47942
18787      GIM_Try, /*On fail goto*//*Label 959*/ 48012, // Rule ID 1731 //
18788        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
18789        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsd,
18790        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18791        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18792        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18793        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18794        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18795        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18796        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18797        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18798        // (intrinsic_wo_chain:{ *:[i32] } 1163:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
18799        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSD,
18800        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18801        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18802        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18803        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18804        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18805        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18806        GIR_EraseFromParent, /*InsnID*/0,
18807        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18808        // GIR_Coverage, 1731,
18809        GIR_Done,
18810      // Label 959: @48012
18811      GIM_Try, /*On fail goto*//*Label 960*/ 48082, // Rule ID 1732 //
18812        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
18813        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlsdx,
18814        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18815        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18816        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18817        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18818        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18819        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
18820        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
18821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18822        // (intrinsic_wo_chain:{ *:[i32] } 1164:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)  =>  (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
18823        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLSDX,
18824        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18825        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
18826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
18827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Ra
18828        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18829        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18830        GIR_EraseFromParent, /*InsnID*/0,
18831        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18832        // GIR_Coverage, 1732,
18833        GIR_Done,
18834      // Label 960: @48082
18835      GIM_Try, /*On fail goto*//*Label 961*/ 48152, // Rule ID 1803 //
18836        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18837        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
18838        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18839        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18840        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18841        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18842        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18846        // (intrinsic_wo_chain:{ *:[i32] } 1153:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
18847        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABB,
18848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18851        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
18852        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18853        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18854        GIR_EraseFromParent, /*InsnID*/0,
18855        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18856        // GIR_Coverage, 1803,
18857        GIR_Done,
18858      // Label 961: @48152
18859      GIM_Try, /*On fail goto*//*Label 962*/ 48222, // Rule ID 1804 //
18860        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18861        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
18862        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18863        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18864        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18865        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18868        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18869        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18870        // (intrinsic_wo_chain:{ *:[i32] } 1154:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
18871        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLABT,
18872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18873        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18874        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18875        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
18876        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18877        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18878        GIR_EraseFromParent, /*InsnID*/0,
18879        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18880        // GIR_Coverage, 1804,
18881        GIR_Done,
18882      // Label 962: @48222
18883      GIM_Try, /*On fail goto*//*Label 963*/ 48292, // Rule ID 1805 //
18884        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18885        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
18886        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18887        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18888        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18889        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18890        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18891        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18892        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18893        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18894        // (intrinsic_wo_chain:{ *:[i32] } 1159:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
18895        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATB,
18896        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18897        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18898        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18899        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
18900        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18901        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18902        GIR_EraseFromParent, /*InsnID*/0,
18903        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18904        // GIR_Coverage, 1805,
18905        GIR_Done,
18906      // Label 963: @48292
18907      GIM_Try, /*On fail goto*//*Label 964*/ 48362, // Rule ID 1806 //
18908        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18909        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
18910        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18911        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18912        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18913        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18914        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18915        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18916        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18917        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18918        // (intrinsic_wo_chain:{ *:[i32] } 1160:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
18919        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
18920        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18921        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18922        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18923        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
18924        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18925        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18926        GIR_EraseFromParent, /*InsnID*/0,
18927        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18928        // GIR_Coverage, 1806,
18929        GIR_Done,
18930      // Label 964: @48362
18931      GIM_Try, /*On fail goto*//*Label 965*/ 48432, // Rule ID 1807 //
18932        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18933        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
18934        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18935        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18936        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18937        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18938        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18939        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18940        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18941        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18942        // (intrinsic_wo_chain:{ *:[i32] } 1161:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
18943        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWB,
18944        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18945        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18947        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
18948        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18949        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18950        GIR_EraseFromParent, /*InsnID*/0,
18951        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18952        // GIR_Coverage, 1807,
18953        GIR_Done,
18954      // Label 965: @48432
18955      GIM_Try, /*On fail goto*//*Label 966*/ 48502, // Rule ID 1808 //
18956        GIM_CheckFeatures, GIFBS_HasV5TE_IsARM,
18957        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
18958        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18959        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18960        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18961        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18962        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
18963        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18965        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18966        // (intrinsic_wo_chain:{ *:[i32] } 1162:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
18967        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLAWT,
18968        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18969        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18970        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18971        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
18972        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18973        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18974        GIR_EraseFromParent, /*InsnID*/0,
18975        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
18976        // GIR_Coverage, 1808,
18977        GIR_Done,
18978      // Label 966: @48502
18979      GIM_Try, /*On fail goto*//*Label 967*/ 48572, // Rule ID 1955 //
18980        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
18981        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabb,
18982        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
18983        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
18984        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
18985        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
18986        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
18987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
18988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
18989        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
18990        // (intrinsic_wo_chain:{ *:[i32] } 1153:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
18991        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABB,
18992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
18993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
18994        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
18995        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
18996        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
18997        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
18998        GIR_EraseFromParent, /*InsnID*/0,
18999        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19000        // GIR_Coverage, 1955,
19001        GIR_Done,
19002      // Label 967: @48572
19003      GIM_Try, /*On fail goto*//*Label 968*/ 48642, // Rule ID 1956 //
19004        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
19005        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlabt,
19006        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19007        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19008        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19009        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
19010        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19011        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
19012        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
19013        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
19014        // (intrinsic_wo_chain:{ *:[i32] } 1154:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
19015        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLABT,
19016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
19018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
19019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
19020        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19021        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19022        GIR_EraseFromParent, /*InsnID*/0,
19023        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19024        // GIR_Coverage, 1956,
19025        GIR_Done,
19026      // Label 968: @48642
19027      GIM_Try, /*On fail goto*//*Label 969*/ 48712, // Rule ID 1957 //
19028        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
19029        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatb,
19030        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19031        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19032        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19033        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
19034        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19035        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
19036        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
19037        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
19038        // (intrinsic_wo_chain:{ *:[i32] } 1159:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
19039        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATB,
19040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
19042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
19043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
19044        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19045        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19046        GIR_EraseFromParent, /*InsnID*/0,
19047        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19048        // GIR_Coverage, 1957,
19049        GIR_Done,
19050      // Label 969: @48712
19051      GIM_Try, /*On fail goto*//*Label 970*/ 48782, // Rule ID 1958 //
19052        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
19053        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlatt,
19054        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19055        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19056        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19057        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
19058        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19059        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
19060        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
19061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
19062        // (intrinsic_wo_chain:{ *:[i32] } 1160:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
19063        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
19064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
19066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
19067        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
19068        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19069        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19070        GIR_EraseFromParent, /*InsnID*/0,
19071        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19072        // GIR_Coverage, 1958,
19073        GIR_Done,
19074      // Label 970: @48782
19075      GIM_Try, /*On fail goto*//*Label 971*/ 48852, // Rule ID 1959 //
19076        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
19077        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawb,
19078        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19079        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19080        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19081        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
19082        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19083        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
19084        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
19085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
19086        // (intrinsic_wo_chain:{ *:[i32] } 1161:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
19087        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWB,
19088        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19089        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
19090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
19091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
19092        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19093        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19094        GIR_EraseFromParent, /*InsnID*/0,
19095        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19096        // GIR_Coverage, 1959,
19097        GIR_Done,
19098      // Label 971: @48852
19099      GIM_Try, /*On fail goto*//*Label 972*/ 48922, // Rule ID 1960 //
19100        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
19101        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_smlawt,
19102        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19103        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19104        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19105        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
19106        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
19107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
19108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
19109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
19110        // (intrinsic_wo_chain:{ *:[i32] } 1162:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)  =>  (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
19111        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLAWT,
19112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
19114        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
19115        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // acc
19116        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19117        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19118        GIR_EraseFromParent, /*InsnID*/0,
19119        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19120        // GIR_Coverage, 1960,
19121        GIR_Done,
19122      // Label 972: @48922
19123      GIM_Try, /*On fail goto*//*Label 973*/ 48992, // Rule ID 2204 //
19124        GIM_CheckFeatures, GIFBS_HasNEON,
19125        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19126        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s8,
19127        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s8,
19128        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s8,
19129        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s8,
19130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19131        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19132        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19133        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
19134        // (intrinsic_wo_chain:{ *:[v8i8] } 1021:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)  =>  (VBSLd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19135        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
19136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19137        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19138        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19140        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19141        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19142        GIR_EraseFromParent, /*InsnID*/0,
19143        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19144        // GIR_Coverage, 2204,
19145        GIR_Done,
19146      // Label 973: @48992
19147      GIM_Try, /*On fail goto*//*Label 974*/ 49062, // Rule ID 2205 //
19148        GIM_CheckFeatures, GIFBS_HasNEON,
19149        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19150        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
19151        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
19152        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
19153        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
19154        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19155        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19156        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19157        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
19158        // (intrinsic_wo_chain:{ *:[v4i16] } 1021:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)  =>  (VBSLd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19159        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
19160        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19161        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19164        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19165        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19166        GIR_EraseFromParent, /*InsnID*/0,
19167        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19168        // GIR_Coverage, 2205,
19169        GIR_Done,
19170      // Label 974: @49062
19171      GIM_Try, /*On fail goto*//*Label 975*/ 49132, // Rule ID 2206 //
19172        GIM_CheckFeatures, GIFBS_HasNEON,
19173        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19174        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19175        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19176        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19177        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
19178        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19179        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19180        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19181        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
19182        // (intrinsic_wo_chain:{ *:[v2i32] } 1021:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)  =>  (VBSLd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19183        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
19184        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19187        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19188        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19189        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19190        GIR_EraseFromParent, /*InsnID*/0,
19191        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19192        // GIR_Coverage, 2206,
19193        GIR_Done,
19194      // Label 975: @49132
19195      GIM_Try, /*On fail goto*//*Label 976*/ 49202, // Rule ID 2207 //
19196        GIM_CheckFeatures, GIFBS_HasNEON,
19197        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19198        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
19199        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
19200        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
19201        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s32,
19202        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19203        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19204        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19205        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
19206        // (intrinsic_wo_chain:{ *:[v2f32] } 1021:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VBSLd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
19207        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
19208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19209        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19210        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19211        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19212        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19213        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19214        GIR_EraseFromParent, /*InsnID*/0,
19215        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19216        // GIR_Coverage, 2207,
19217        GIR_Done,
19218      // Label 976: @49202
19219      GIM_Try, /*On fail goto*//*Label 977*/ 49272, // Rule ID 2208 //
19220        GIM_CheckFeatures, GIFBS_HasNEON,
19221        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19222        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
19223        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
19224        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
19225        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
19226        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
19227        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
19228        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
19229        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::DPRRegClassID,
19230        // (intrinsic_wo_chain:{ *:[v1i64] } 1021:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)  =>  (VBSLd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
19231        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
19232        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19233        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19234        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19235        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19236        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19237        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19238        GIR_EraseFromParent, /*InsnID*/0,
19239        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19240        // GIR_Coverage, 2208,
19241        GIR_Done,
19242      // Label 977: @49272
19243      GIM_Try, /*On fail goto*//*Label 978*/ 49342, // Rule ID 2211 //
19244        GIM_CheckFeatures, GIFBS_HasNEON,
19245        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19246        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
19247        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
19248        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
19249        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
19250        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19251        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19252        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19253        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
19254        // (intrinsic_wo_chain:{ *:[v16i8] } 1021:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)  =>  (VBSLq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19255        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
19256        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19257        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19258        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19259        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19260        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19261        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19262        GIR_EraseFromParent, /*InsnID*/0,
19263        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19264        // GIR_Coverage, 2211,
19265        GIR_Done,
19266      // Label 978: @49342
19267      GIM_Try, /*On fail goto*//*Label 979*/ 49412, // Rule ID 2212 //
19268        GIM_CheckFeatures, GIFBS_HasNEON,
19269        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19270        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
19271        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
19272        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
19273        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
19274        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19275        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19276        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19277        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
19278        // (intrinsic_wo_chain:{ *:[v8i16] } 1021:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)  =>  (VBSLq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19279        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
19280        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19281        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19282        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19283        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19284        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19285        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19286        GIR_EraseFromParent, /*InsnID*/0,
19287        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19288        // GIR_Coverage, 2212,
19289        GIR_Done,
19290      // Label 979: @49412
19291      GIM_Try, /*On fail goto*//*Label 980*/ 49482, // Rule ID 2213 //
19292        GIM_CheckFeatures, GIFBS_HasNEON,
19293        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19294        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19295        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19296        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19297        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
19298        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19299        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19300        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19301        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
19302        // (intrinsic_wo_chain:{ *:[v4i32] } 1021:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)  =>  (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19303        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
19304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19306        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19307        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19308        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19309        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19310        GIR_EraseFromParent, /*InsnID*/0,
19311        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19312        // GIR_Coverage, 2213,
19313        GIR_Done,
19314      // Label 980: @49482
19315      GIM_Try, /*On fail goto*//*Label 981*/ 49552, // Rule ID 2214 //
19316        GIM_CheckFeatures, GIFBS_HasNEON,
19317        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19318        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
19319        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
19320        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
19321        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
19322        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19323        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19324        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19325        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
19326        // (intrinsic_wo_chain:{ *:[v4f32] } 1021:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VBSLq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
19327        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
19328        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19329        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19330        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19331        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19332        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19333        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19334        GIR_EraseFromParent, /*InsnID*/0,
19335        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19336        // GIR_Coverage, 2214,
19337        GIR_Done,
19338      // Label 981: @49552
19339      GIM_Try, /*On fail goto*//*Label 982*/ 49622, // Rule ID 2215 //
19340        GIM_CheckFeatures, GIFBS_HasNEON,
19341        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_neon_vbsl,
19342        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
19343        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
19344        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
19345        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
19346        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
19347        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
19348        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
19349        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::QPRRegClassID,
19350        // (intrinsic_wo_chain:{ *:[v2i64] } 1021:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)  =>  (VBSLq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
19351        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
19352        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
19353        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
19354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Vn
19355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Vm
19356        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19357        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19358        GIR_EraseFromParent, /*InsnID*/0,
19359        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19360        // GIR_Coverage, 2215,
19361        GIR_Done,
19362      // Label 982: @49622
19363      GIM_Reject,
19364    // Label 941: @49623
19365    GIM_Reject,
19366    // Label 10: @49624
19367    GIM_Try, /*On fail goto*//*Label 983*/ 49669,
19368      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_clrex,
19369      GIM_Try, /*On fail goto*//*Label 984*/ 49646, // Rule ID 254 //
19370        GIM_CheckFeatures, GIFBS_HasV6K_IsARM,
19371        // (intrinsic_void 971:{ *:[iPTR] })  =>  (CLREX)
19372        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CLREX,
19373        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19374        GIR_EraseFromParent, /*InsnID*/0,
19375        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19376        // GIR_Coverage, 254,
19377        GIR_Done,
19378      // Label 984: @49646
19379      GIM_Try, /*On fail goto*//*Label 985*/ 49668, // Rule ID 587 //
19380        GIM_CheckFeatures, GIFBS_HasV7Clrex_IsThumb,
19381        // (intrinsic_void 971:{ *:[iPTR] })  =>  (t2CLREX)
19382        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CLREX,
19383        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19384        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19385        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19386        GIR_EraseFromParent, /*InsnID*/0,
19387        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19388        // GIR_Coverage, 587,
19389        GIR_Done,
19390      // Label 985: @49668
19391      GIM_Reject,
19392    // Label 983: @49669
19393    GIM_Try, /*On fail goto*//*Label 986*/ 50387,
19394      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
19395      GIM_Try, /*On fail goto*//*Label 987*/ 49702, // Rule ID 350 //
19396        GIM_CheckFeatures, GIFBS_IsThumb_IsWindows,
19397        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
19398        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19399        GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 249,
19400        // (intrinsic_void 1202:{ *:[iPTR] }, 249:{ *:[i32] })  =>  (t__brkdiv0)
19401        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t__brkdiv0,
19402        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19403        GIR_EraseFromParent, /*InsnID*/0,
19404        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19405        // GIR_Coverage, 350,
19406        GIR_Done,
19407      // Label 987: @49702
19408      GIM_Try, /*On fail goto*//*Label 988*/ 49748, // Rule ID 2 //
19409        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
19410        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
19411        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19412        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19413        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19414        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239,
19415        // MIs[1] Operand 1
19416        // No operand predicates
19417        GIM_CheckIsSafeToFold, /*InsnID*/1,
19418        // (intrinsic_void 982:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm)  =>  (HINT (imm:{ *:[i32] }):$imm)
19419        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::HINT,
19420        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
19421        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19422        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19423        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19424        GIR_EraseFromParent, /*InsnID*/0,
19425        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19426        // GIR_Coverage, 2,
19427        GIR_Done,
19428      // Label 988: @49748
19429      GIM_Try, /*On fail goto*//*Label 989*/ 49794, // Rule ID 10 //
19430        GIM_CheckFeatures, GIFBS_HasV7_IsARM,
19431        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg,
19432        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19433        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19434        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19435        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
19436        // MIs[1] Operand 1
19437        // No operand predicates
19438        GIM_CheckIsSafeToFold, /*InsnID*/1,
19439        // (intrinsic_void 978:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DBG (imm:{ *:[i32] }):$opt)
19440        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DBG,
19441        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
19442        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19443        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19444        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19445        GIR_EraseFromParent, /*InsnID*/0,
19446        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19447        // GIR_Coverage, 10,
19448        GIR_Done,
19449      // Label 989: @49794
19450      GIM_Try, /*On fail goto*//*Label 990*/ 49834, // Rule ID 11 //
19451        GIM_CheckFeatures, GIFBS_IsARM,
19452        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
19453        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19454        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19455        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19456        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
19457        // MIs[1] Operand 1
19458        // No operand predicates
19459        GIM_CheckIsSafeToFold, /*InsnID*/1,
19460        // (intrinsic_void 1202:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16)  =>  (UDF (imm:{ *:[i32] }):$imm16)
19461        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UDF,
19462        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
19463        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19464        GIR_EraseFromParent, /*InsnID*/0,
19465        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19466        // GIR_Coverage, 11,
19467        GIR_Done,
19468      // Label 990: @49834
19469      GIM_Try, /*On fail goto*//*Label 991*/ 49874, // Rule ID 237 //
19470        GIM_CheckFeatures, GIFBS_HasDB_IsARM,
19471        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb,
19472        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19473        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19474        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19475        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
19476        // MIs[1] Operand 1
19477        // No operand predicates
19478        GIM_CheckIsSafeToFold, /*InsnID*/1,
19479        // (intrinsic_void 979:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DMB (imm:{ *:[i32] }):$opt)
19480        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DMB,
19481        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
19482        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19483        GIR_EraseFromParent, /*InsnID*/0,
19484        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19485        // GIR_Coverage, 237,
19486        GIR_Done,
19487      // Label 991: @49874
19488      GIM_Try, /*On fail goto*//*Label 992*/ 49914, // Rule ID 238 //
19489        GIM_CheckFeatures, GIFBS_HasDB_IsARM,
19490        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb,
19491        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19492        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19493        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19494        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
19495        // MIs[1] Operand 1
19496        // No operand predicates
19497        GIM_CheckIsSafeToFold, /*InsnID*/1,
19498        // (intrinsic_void 980:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (DSB (imm:{ *:[i32] }):$opt)
19499        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::DSB,
19500        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
19501        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19502        GIR_EraseFromParent, /*InsnID*/0,
19503        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19504        // GIR_Coverage, 238,
19505        GIR_Done,
19506      // Label 992: @49914
19507      GIM_Try, /*On fail goto*//*Label 993*/ 49954, // Rule ID 239 //
19508        GIM_CheckFeatures, GIFBS_HasDB_IsARM,
19509        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb,
19510        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19511        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19512        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19513        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
19514        // MIs[1] Operand 1
19515        // No operand predicates
19516        GIM_CheckIsSafeToFold, /*InsnID*/1,
19517        // (intrinsic_void 983:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (ISB (imm:{ *:[i32] }):$opt)
19518        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ISB,
19519        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
19520        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19521        GIR_EraseFromParent, /*InsnID*/0,
19522        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19523        // GIR_Coverage, 239,
19524        GIR_Done,
19525      // Label 993: @49954
19526      GIM_Try, /*On fail goto*//*Label 994*/ 50000, // Rule ID 285 //
19527        GIM_CheckFeatures, GIFBS_HasV6M_IsThumb,
19528        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
19529        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19530        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19531        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19532        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
19533        // MIs[1] Operand 1
19534        // No operand predicates
19535        GIM_CheckIsSafeToFold, /*InsnID*/1,
19536        // (intrinsic_void 982:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)  =>  (tHINT (imm:{ *:[i32] }):$imm)
19537        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tHINT,
19538        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
19539        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19540        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19541        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19542        GIR_EraseFromParent, /*InsnID*/0,
19543        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19544        // GIR_Coverage, 285,
19545        GIR_Done,
19546      // Label 994: @50000
19547      GIM_Try, /*On fail goto*//*Label 995*/ 50040, // Rule ID 349 //
19548        GIM_CheckFeatures, GIFBS_IsThumb,
19549        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
19550        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19551        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19552        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19553        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_255,
19554        // MIs[1] Operand 1
19555        // No operand predicates
19556        GIM_CheckIsSafeToFold, /*InsnID*/1,
19557        // (intrinsic_void 1202:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8)  =>  (tUDF (imm:{ *:[i32] }):$imm8)
19558        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tUDF,
19559        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
19560        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19561        GIR_EraseFromParent, /*InsnID*/0,
19562        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19563        // GIR_Coverage, 349,
19564        GIR_Done,
19565      // Label 995: @50040
19566      GIM_Try, /*On fail goto*//*Label 996*/ 50080, // Rule ID 498 //
19567        GIM_CheckFeatures, GIFBS_IsThumb2,
19568        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_undefined,
19569        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19570        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19571        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19572        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
19573        // MIs[1] Operand 1
19574        // No operand predicates
19575        GIM_CheckIsSafeToFold, /*InsnID*/1,
19576        // (intrinsic_void 1202:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16)  =>  (t2UDF (imm:{ *:[i32] }):$imm16)
19577        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UDF,
19578        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
19579        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19580        GIR_EraseFromParent, /*InsnID*/0,
19581        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19582        // GIR_Coverage, 498,
19583        GIR_Done,
19584      // Label 996: @50080
19585      GIM_Try, /*On fail goto*//*Label 997*/ 50126, // Rule ID 572 //
19586        GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
19587        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dmb,
19588        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19589        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19590        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19591        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
19592        // MIs[1] Operand 1
19593        // No operand predicates
19594        GIM_CheckIsSafeToFold, /*InsnID*/1,
19595        // (intrinsic_void 979:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DMB (imm:{ *:[i32] }):$opt)
19596        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DMB,
19597        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
19598        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19599        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19600        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19601        GIR_EraseFromParent, /*InsnID*/0,
19602        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19603        // GIR_Coverage, 572,
19604        GIR_Done,
19605      // Label 997: @50126
19606      GIM_Try, /*On fail goto*//*Label 998*/ 50172, // Rule ID 573 //
19607        GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
19608        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dsb,
19609        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19610        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19611        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19612        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
19613        // MIs[1] Operand 1
19614        // No operand predicates
19615        GIM_CheckIsSafeToFold, /*InsnID*/1,
19616        // (intrinsic_void 980:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DSB (imm:{ *:[i32] }):$opt)
19617        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DSB,
19618        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
19619        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19620        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19621        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19622        GIR_EraseFromParent, /*InsnID*/0,
19623        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19624        // GIR_Coverage, 573,
19625        GIR_Done,
19626      // Label 998: @50172
19627      GIM_Try, /*On fail goto*//*Label 999*/ 50218, // Rule ID 574 //
19628        GIM_CheckFeatures, GIFBS_HasDB_IsThumb,
19629        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_isb,
19630        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19631        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19632        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19633        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
19634        // MIs[1] Operand 1
19635        // No operand predicates
19636        GIM_CheckIsSafeToFold, /*InsnID*/1,
19637        // (intrinsic_void 983:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2ISB (imm:{ *:[i32] }):$opt)
19638        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ISB,
19639        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
19640        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19641        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19642        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19643        GIR_EraseFromParent, /*InsnID*/0,
19644        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19645        // GIR_Coverage, 574,
19646        GIR_Done,
19647      // Label 999: @50218
19648      GIM_Try, /*On fail goto*//*Label 1000*/ 50264, // Rule ID 592 //
19649        GIM_CheckFeatures, GIFBS_IsThumb2,
19650        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_hint,
19651        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19652        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19653        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19654        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_239,
19655        // MIs[1] Operand 1
19656        // No operand predicates
19657        GIM_CheckIsSafeToFold, /*InsnID*/1,
19658        // (intrinsic_void 982:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm)  =>  (t2HINT (imm:{ *:[i32] }):$imm)
19659        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2HINT,
19660        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
19661        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19662        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19663        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19664        GIR_EraseFromParent, /*InsnID*/0,
19665        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19666        // GIR_Coverage, 592,
19667        GIR_Done,
19668      // Label 1000: @50264
19669      GIM_Try, /*On fail goto*//*Label 1001*/ 50310, // Rule ID 593 //
19670        GIM_CheckFeatures, GIFBS_IsThumb2,
19671        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_dbg,
19672        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19673        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19674        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19675        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_15,
19676        // MIs[1] Operand 1
19677        // No operand predicates
19678        GIM_CheckIsSafeToFold, /*InsnID*/1,
19679        // (intrinsic_void 978:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt)  =>  (t2DBG (imm:{ *:[i32] }):$opt)
19680        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2DBG,
19681        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
19682        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19683        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19684        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19685        GIR_EraseFromParent, /*InsnID*/0,
19686        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19687        // GIR_Coverage, 593,
19688        GIR_Done,
19689      // Label 1001: @50310
19690      GIM_Try, /*On fail goto*//*Label 1002*/ 50348, // Rule ID 723 //
19691        GIM_CheckFeatures, GIFBS_HasVFP2,
19692        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_get_fpscr,
19693        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19694        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19695        // (intrinsic_w_chain:{ *:[i32] } 981:{ *:[iPTR] })  =>  (VMRS:{ *:[i32] })
19696        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMRS,
19697        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
19698        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19699        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19700        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19701        GIR_EraseFromParent, /*InsnID*/0,
19702        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19703        // GIR_Coverage, 723,
19704        GIR_Done,
19705      // Label 1002: @50348
19706      GIM_Try, /*On fail goto*//*Label 1003*/ 50386, // Rule ID 724 //
19707        GIM_CheckFeatures, GIFBS_HasVFP2,
19708        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_set_fpscr,
19709        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
19710        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
19711        // (intrinsic_void 1146:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$src)  =>  (VMSR GPRnopc:{ *:[i32] }:$src)
19712        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMSR,
19713        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
19714        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19715        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19716        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19717        GIR_EraseFromParent, /*InsnID*/0,
19718        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19719        // GIR_Coverage, 724,
19720        GIR_Done,
19721      // Label 1003: @50386
19722      GIM_Reject,
19723    // Label 986: @50387
19724    GIM_Try, /*On fail goto*//*Label 1004*/ 52064,
19725      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
19726      GIM_Try, /*On fail goto*//*Label 1005*/ 50451, // Rule ID 1696 //
19727        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_space,
19728        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19729        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19730        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19731        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
19732        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
19733        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
19734        // MIs[1] Operand 1
19735        // No operand predicates
19736        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
19737        GIM_CheckIsSafeToFold, /*InsnID*/1,
19738        // (intrinsic_w_chain:{ *:[i32] } 1177:{ *:[iPTR] }, (imm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)  =>  (SPACE:{ *:[i32] } (imm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)
19739        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SPACE,
19740        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19741        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // size
19742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rn
19743        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
19744        GIR_EraseFromParent, /*InsnID*/0,
19745        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19746        // GIR_Coverage, 1696,
19747        GIR_Done,
19748      // Label 1005: @50451
19749      GIM_Try, /*On fail goto*//*Label 1006*/ 50513, // Rule ID 3 //
19750        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
19751        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel,
19752        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19753        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19754        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19755        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
19756        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
19757        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
19758        // (intrinsic_w_chain:{ *:[i32] } 1145:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
19759        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SEL,
19760        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19761        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19762        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19763        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19764        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19765        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19766        GIR_EraseFromParent, /*InsnID*/0,
19767        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19768        // GIR_Coverage, 3,
19769        GIR_Done,
19770      // Label 1006: @50513
19771      GIM_Try, /*On fail goto*//*Label 1007*/ 50575, // Rule ID 123 //
19772        GIM_CheckFeatures, GIFBS_IsARM,
19773        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx,
19774        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19775        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19776        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19779        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19780        // (intrinsic_w_chain:{ *:[i32] } 1144:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19781        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SASX,
19782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19785        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19786        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19787        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19788        GIR_EraseFromParent, /*InsnID*/0,
19789        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19790        // GIR_Coverage, 123,
19791        GIR_Done,
19792      // Label 1007: @50575
19793      GIM_Try, /*On fail goto*//*Label 1008*/ 50637, // Rule ID 124 //
19794        GIM_CheckFeatures, GIFBS_IsARM,
19795        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16,
19796        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19797        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19798        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19799        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19800        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19801        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19802        // (intrinsic_w_chain:{ *:[i32] } 1142:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19803        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD16,
19804        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19805        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19806        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19807        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19808        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19809        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19810        GIR_EraseFromParent, /*InsnID*/0,
19811        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19812        // GIR_Coverage, 124,
19813        GIR_Done,
19814      // Label 1008: @50637
19815      GIM_Try, /*On fail goto*//*Label 1009*/ 50699, // Rule ID 125 //
19816        GIM_CheckFeatures, GIFBS_IsARM,
19817        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8,
19818        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19819        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19820        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19821        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19822        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19823        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19824        // (intrinsic_w_chain:{ *:[i32] } 1143:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19825        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SADD8,
19826        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19827        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19828        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19829        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19830        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19831        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19832        GIR_EraseFromParent, /*InsnID*/0,
19833        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19834        // GIR_Coverage, 125,
19835        GIR_Done,
19836      // Label 1009: @50699
19837      GIM_Try, /*On fail goto*//*Label 1010*/ 50761, // Rule ID 126 //
19838        GIM_CheckFeatures, GIFBS_IsARM,
19839        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax,
19840        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19841        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19842        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19843        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19844        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19845        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19846        // (intrinsic_w_chain:{ *:[i32] } 1180:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19847        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSAX,
19848        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19849        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19850        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19851        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19852        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19853        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19854        GIR_EraseFromParent, /*InsnID*/0,
19855        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19856        // GIR_Coverage, 126,
19857        GIR_Done,
19858      // Label 1010: @50761
19859      GIM_Try, /*On fail goto*//*Label 1011*/ 50823, // Rule ID 127 //
19860        GIM_CheckFeatures, GIFBS_IsARM,
19861        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16,
19862        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19863        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19864        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19865        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19866        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19867        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19868        // (intrinsic_w_chain:{ *:[i32] } 1181:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19869        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB16,
19870        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19871        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19872        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19873        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19874        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19875        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19876        GIR_EraseFromParent, /*InsnID*/0,
19877        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19878        // GIR_Coverage, 127,
19879        GIR_Done,
19880      // Label 1011: @50823
19881      GIM_Try, /*On fail goto*//*Label 1012*/ 50885, // Rule ID 128 //
19882        GIM_CheckFeatures, GIFBS_IsARM,
19883        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8,
19884        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19885        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19886        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19887        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19888        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19889        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19890        // (intrinsic_w_chain:{ *:[i32] } 1182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19891        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SSUB8,
19892        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19894        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19895        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19896        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19897        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19898        GIR_EraseFromParent, /*InsnID*/0,
19899        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19900        // GIR_Coverage, 128,
19901        GIR_Done,
19902      // Label 1012: @50885
19903      GIM_Try, /*On fail goto*//*Label 1013*/ 50947, // Rule ID 129 //
19904        GIM_CheckFeatures, GIFBS_IsARM,
19905        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx,
19906        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19907        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19908        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19909        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19910        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19911        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19912        // (intrinsic_w_chain:{ *:[i32] } 1195:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19913        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UASX,
19914        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19915        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19916        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19917        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19918        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19919        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19920        GIR_EraseFromParent, /*InsnID*/0,
19921        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19922        // GIR_Coverage, 129,
19923        GIR_Done,
19924      // Label 1013: @50947
19925      GIM_Try, /*On fail goto*//*Label 1014*/ 51009, // Rule ID 130 //
19926        GIM_CheckFeatures, GIFBS_IsARM,
19927        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16,
19928        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19929        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19930        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19931        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19932        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19933        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19934        // (intrinsic_w_chain:{ *:[i32] } 1193:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19935        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD16,
19936        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19937        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19938        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19939        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19940        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19941        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19942        GIR_EraseFromParent, /*InsnID*/0,
19943        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19944        // GIR_Coverage, 130,
19945        GIR_Done,
19946      // Label 1014: @51009
19947      GIM_Try, /*On fail goto*//*Label 1015*/ 51071, // Rule ID 131 //
19948        GIM_CheckFeatures, GIFBS_IsARM,
19949        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8,
19950        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19951        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19952        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19953        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19954        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19955        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19956        // (intrinsic_w_chain:{ *:[i32] } 1194:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19957        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UADD8,
19958        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19959        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19960        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19961        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19962        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19963        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19964        GIR_EraseFromParent, /*InsnID*/0,
19965        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19966        // GIR_Coverage, 131,
19967        GIR_Done,
19968      // Label 1015: @51071
19969      GIM_Try, /*On fail goto*//*Label 1016*/ 51133, // Rule ID 132 //
19970        GIM_CheckFeatures, GIFBS_IsARM,
19971        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax,
19972        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19973        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19974        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19976        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19977        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
19978        // (intrinsic_w_chain:{ *:[i32] } 1213:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19979        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USAX,
19980        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
19981        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
19982        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
19983        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
19984        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
19985        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
19986        GIR_EraseFromParent, /*InsnID*/0,
19987        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
19988        // GIR_Coverage, 132,
19989        GIR_Done,
19990      // Label 1016: @51133
19991      GIM_Try, /*On fail goto*//*Label 1017*/ 51195, // Rule ID 133 //
19992        GIM_CheckFeatures, GIFBS_IsARM,
19993        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16,
19994        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
19995        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
19996        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
19997        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
19998        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
19999        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
20000        // (intrinsic_w_chain:{ *:[i32] } 1214:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
20001        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB16,
20002        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20003        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20004        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20005        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20006        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20007        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20008        GIR_EraseFromParent, /*InsnID*/0,
20009        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20010        // GIR_Coverage, 133,
20011        GIR_Done,
20012      // Label 1017: @51195
20013      GIM_Try, /*On fail goto*//*Label 1018*/ 51257, // Rule ID 134 //
20014        GIM_CheckFeatures, GIFBS_IsARM,
20015        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8,
20016        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20017        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20018        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20019        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
20020        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
20021        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
20022        // (intrinsic_w_chain:{ *:[i32] } 1215:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)  =>  (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
20023        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::USUB8,
20024        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20025        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20026        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20027        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20028        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20029        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20030        GIR_EraseFromParent, /*InsnID*/0,
20031        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20032        // GIR_Coverage, 134,
20033        GIR_Done,
20034      // Label 1018: @51257
20035      GIM_Try, /*On fail goto*//*Label 1019*/ 51319, // Rule ID 435 //
20036        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20037        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sel,
20038        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20039        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20040        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20041        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
20042        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
20043        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20044        // (intrinsic_w_chain:{ *:[i32] } 1145:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)  =>  (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
20045        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SEL,
20046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20047        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20048        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20049        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20050        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20051        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20052        GIR_EraseFromParent, /*InsnID*/0,
20053        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20054        // GIR_Coverage, 435,
20055        GIR_Done,
20056      // Label 1019: @51319
20057      GIM_Try, /*On fail goto*//*Label 1020*/ 51381, // Rule ID 448 //
20058        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20059        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sasx,
20060        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20061        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20062        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20063        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20064        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20065        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20066        // (intrinsic_w_chain:{ *:[i32] } 1144:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20067        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SASX,
20068        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20069        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20070        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20071        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20072        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20073        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20074        GIR_EraseFromParent, /*InsnID*/0,
20075        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20076        // GIR_Coverage, 448,
20077        GIR_Done,
20078      // Label 1020: @51381
20079      GIM_Try, /*On fail goto*//*Label 1021*/ 51443, // Rule ID 449 //
20080        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20081        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd16,
20082        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20083        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20084        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20085        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20086        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20087        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20088        // (intrinsic_w_chain:{ *:[i32] } 1142:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20089        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD16,
20090        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20091        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20092        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20093        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20094        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20095        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20096        GIR_EraseFromParent, /*InsnID*/0,
20097        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20098        // GIR_Coverage, 449,
20099        GIR_Done,
20100      // Label 1021: @51443
20101      GIM_Try, /*On fail goto*//*Label 1022*/ 51505, // Rule ID 450 //
20102        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20103        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_sadd8,
20104        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20105        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20106        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20107        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20108        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20109        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20110        // (intrinsic_w_chain:{ *:[i32] } 1143:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20111        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SADD8,
20112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20114        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20115        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20116        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20117        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20118        GIR_EraseFromParent, /*InsnID*/0,
20119        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20120        // GIR_Coverage, 450,
20121        GIR_Done,
20122      // Label 1022: @51505
20123      GIM_Try, /*On fail goto*//*Label 1023*/ 51567, // Rule ID 451 //
20124        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20125        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssax,
20126        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20127        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20128        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20129        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20130        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20131        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20132        // (intrinsic_w_chain:{ *:[i32] } 1180:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20133        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSAX,
20134        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20135        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20136        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20137        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20138        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20139        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20140        GIR_EraseFromParent, /*InsnID*/0,
20141        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20142        // GIR_Coverage, 451,
20143        GIR_Done,
20144      // Label 1023: @51567
20145      GIM_Try, /*On fail goto*//*Label 1024*/ 51629, // Rule ID 452 //
20146        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20147        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub16,
20148        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20149        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20150        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20152        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20153        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20154        // (intrinsic_w_chain:{ *:[i32] } 1181:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20155        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB16,
20156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20157        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20158        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20159        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20160        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20161        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20162        GIR_EraseFromParent, /*InsnID*/0,
20163        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20164        // GIR_Coverage, 452,
20165        GIR_Done,
20166      // Label 1024: @51629
20167      GIM_Try, /*On fail goto*//*Label 1025*/ 51691, // Rule ID 453 //
20168        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20169        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_ssub8,
20170        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20171        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20172        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20173        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20174        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20175        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20176        // (intrinsic_w_chain:{ *:[i32] } 1182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20177        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SSUB8,
20178        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20179        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20180        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20181        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20182        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20183        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20184        GIR_EraseFromParent, /*InsnID*/0,
20185        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20186        // GIR_Coverage, 453,
20187        GIR_Done,
20188      // Label 1025: @51691
20189      GIM_Try, /*On fail goto*//*Label 1026*/ 51753, // Rule ID 454 //
20190        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20191        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uasx,
20192        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20193        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20194        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20195        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20197        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20198        // (intrinsic_w_chain:{ *:[i32] } 1195:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20199        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UASX,
20200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20201        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20202        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20203        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20204        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20205        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20206        GIR_EraseFromParent, /*InsnID*/0,
20207        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20208        // GIR_Coverage, 454,
20209        GIR_Done,
20210      // Label 1026: @51753
20211      GIM_Try, /*On fail goto*//*Label 1027*/ 51815, // Rule ID 455 //
20212        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20213        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd16,
20214        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20215        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20216        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20217        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20218        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20219        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20220        // (intrinsic_w_chain:{ *:[i32] } 1193:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20221        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD16,
20222        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20223        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20224        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20225        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20226        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20227        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20228        GIR_EraseFromParent, /*InsnID*/0,
20229        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20230        // GIR_Coverage, 455,
20231        GIR_Done,
20232      // Label 1027: @51815
20233      GIM_Try, /*On fail goto*//*Label 1028*/ 51877, // Rule ID 456 //
20234        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20235        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_uadd8,
20236        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20237        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20238        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20239        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20241        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20242        // (intrinsic_w_chain:{ *:[i32] } 1194:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20243        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UADD8,
20244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20246        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20247        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20248        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20249        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20250        GIR_EraseFromParent, /*InsnID*/0,
20251        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20252        // GIR_Coverage, 456,
20253        GIR_Done,
20254      // Label 1028: @51877
20255      GIM_Try, /*On fail goto*//*Label 1029*/ 51939, // Rule ID 457 //
20256        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20257        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usax,
20258        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20259        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20260        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20261        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20262        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20263        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20264        // (intrinsic_w_chain:{ *:[i32] } 1213:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20265        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USAX,
20266        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20267        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20268        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20269        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20270        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20271        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20272        GIR_EraseFromParent, /*InsnID*/0,
20273        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20274        // GIR_Coverage, 457,
20275        GIR_Done,
20276      // Label 1029: @51939
20277      GIM_Try, /*On fail goto*//*Label 1030*/ 52001, // Rule ID 458 //
20278        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20279        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub16,
20280        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20281        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20282        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20283        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20284        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20285        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20286        // (intrinsic_w_chain:{ *:[i32] } 1214:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20287        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB16,
20288        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20289        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20290        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20291        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20292        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20293        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20294        GIR_EraseFromParent, /*InsnID*/0,
20295        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20296        // GIR_Coverage, 458,
20297        GIR_Done,
20298      // Label 1030: @52001
20299      GIM_Try, /*On fail goto*//*Label 1031*/ 52063, // Rule ID 459 //
20300        GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
20301        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_usub8,
20302        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20303        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20304        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20305        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
20306        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
20307        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::rGPRRegClassID,
20308        // (intrinsic_w_chain:{ *:[i32] } 1215:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20309        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2USUB8,
20310        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
20311        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
20312        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rm
20313        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20314        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20315        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
20316        GIR_EraseFromParent, /*InsnID*/0,
20317        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20318        // GIR_Coverage, 459,
20319        GIR_Done,
20320      // Label 1031: @52063
20321      GIM_Reject,
20322    // Label 1004: @52064
20323    GIM_Try, /*On fail goto*//*Label 1032*/ 52468,
20324      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
20325      GIM_Try, /*On fail goto*//*Label 1033*/ 52170, // Rule ID 267 //
20326        GIM_CheckFeatures, GIFBS_IsARM,
20327        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr,
20328        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20329        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20330        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20331        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20332        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20333        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20334        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20335        // MIs[1] Operand 1
20336        // No operand predicates
20337        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20338        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20339        // MIs[2] Operand 1
20340        // No operand predicates
20341        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
20342        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
20343        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/5, // MIs[3]
20344        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20345        // MIs[3] Operand 1
20346        // No operand predicates
20347        GIM_CheckIsSafeToFold, /*InsnID*/1,
20348        GIM_CheckIsSafeToFold, /*InsnID*/2,
20349        GIM_CheckIsSafeToFold, /*InsnID*/3,
20350        // (intrinsic_void 994:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm)  =>  (MCRR (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm)
20351        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR,
20352        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20353        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20354        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
20355        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
20356        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRm
20357        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20358        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20359        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, GIU_MergeMemOperands_EndOfList,
20360        GIR_EraseFromParent, /*InsnID*/0,
20361        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20362        // GIR_Coverage, 267,
20363        GIR_Done,
20364      // Label 1033: @52170
20365      GIM_Try, /*On fail goto*//*Label 1034*/ 52265, // Rule ID 268 //
20366        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
20367        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2,
20368        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20369        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20370        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20371        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20372        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20373        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20374        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20375        // MIs[1] Operand 1
20376        // No operand predicates
20377        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20378        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20379        // MIs[2] Operand 1
20380        // No operand predicates
20381        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRnopcRegClassID,
20382        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRnopcRegClassID,
20383        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/5, // MIs[3]
20384        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20385        // MIs[3] Operand 1
20386        // No operand predicates
20387        GIM_CheckIsSafeToFold, /*InsnID*/1,
20388        GIM_CheckIsSafeToFold, /*InsnID*/2,
20389        GIM_CheckIsSafeToFold, /*InsnID*/3,
20390        // (intrinsic_void 995:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm)  =>  (MCRR2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm)
20391        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCRR2,
20392        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20393        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20394        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
20395        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
20396        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRm
20397        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, GIU_MergeMemOperands_EndOfList,
20398        GIR_EraseFromParent, /*InsnID*/0,
20399        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20400        // GIR_Coverage, 268,
20401        GIR_Done,
20402      // Label 1034: @52265
20403      GIM_Try, /*On fail goto*//*Label 1035*/ 52366, // Rule ID 608 //
20404        GIM_CheckFeatures, GIFBS_IsThumb2,
20405        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr,
20406        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20407        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20408        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20409        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20410        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20411        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20412        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20413        // MIs[1] Operand 1
20414        // No operand predicates
20415        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20416        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20417        // MIs[2] Operand 1
20418        // No operand predicates
20419        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20420        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
20421        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/5, // MIs[3]
20422        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20423        // MIs[3] Operand 1
20424        // No operand predicates
20425        GIM_CheckIsSafeToFold, /*InsnID*/1,
20426        GIM_CheckIsSafeToFold, /*InsnID*/2,
20427        GIM_CheckIsSafeToFold, /*InsnID*/3,
20428        // (intrinsic_void 994:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm)  =>  (t2MCRR (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm)
20429        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR,
20430        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20431        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20432        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
20433        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
20434        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRm
20435        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20436        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20437        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, GIU_MergeMemOperands_EndOfList,
20438        GIR_EraseFromParent, /*InsnID*/0,
20439        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20440        // GIR_Coverage, 608,
20441        GIR_Done,
20442      // Label 1035: @52366
20443      GIM_Try, /*On fail goto*//*Label 1036*/ 52467, // Rule ID 609 //
20444        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
20445        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcrr2,
20446        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20447        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20448        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20449        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20450        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20451        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20452        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20453        // MIs[1] Operand 1
20454        // No operand predicates
20455        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20456        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20457        // MIs[2] Operand 1
20458        // No operand predicates
20459        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20460        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/ARM::GPRRegClassID,
20461        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/5, // MIs[3]
20462        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20463        // MIs[3] Operand 1
20464        // No operand predicates
20465        GIM_CheckIsSafeToFold, /*InsnID*/1,
20466        GIM_CheckIsSafeToFold, /*InsnID*/2,
20467        GIM_CheckIsSafeToFold, /*InsnID*/3,
20468        // (intrinsic_void 995:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm)  =>  (t2MCRR2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm)
20469        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCRR2,
20470        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20471        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20472        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
20473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // Rt2
20474        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRm
20475        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20476        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20477        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, GIU_MergeMemOperands_EndOfList,
20478        GIR_EraseFromParent, /*InsnID*/0,
20479        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20480        // GIR_Coverage, 609,
20481        GIR_Done,
20482      // Label 1036: @52467
20483      GIM_Reject,
20484    // Label 1032: @52468
20485    GIM_Try, /*On fail goto*//*Label 1037*/ 53952,
20486      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
20487      GIM_Try, /*On fail goto*//*Label 1038*/ 52601, // Rule ID 255 //
20488        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
20489        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp,
20490        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20491        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20492        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20493        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20494        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20495        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20496        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20497        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20498        // MIs[1] Operand 1
20499        // No operand predicates
20500        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20501        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20502        // MIs[2] Operand 1
20503        // No operand predicates
20504        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
20505        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20506        // MIs[3] Operand 1
20507        // No operand predicates
20508        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/4, // MIs[4]
20509        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20510        // MIs[4] Operand 1
20511        // No operand predicates
20512        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/5, // MIs[5]
20513        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20514        // MIs[5] Operand 1
20515        // No operand predicates
20516        GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/6, // MIs[6]
20517        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
20518        // MIs[6] Operand 1
20519        // No operand predicates
20520        GIM_CheckIsSafeToFold, /*InsnID*/1,
20521        GIM_CheckIsSafeToFold, /*InsnID*/2,
20522        GIM_CheckIsSafeToFold, /*InsnID*/3,
20523        GIM_CheckIsSafeToFold, /*InsnID*/4,
20524        GIM_CheckIsSafeToFold, /*InsnID*/5,
20525        GIM_CheckIsSafeToFold, /*InsnID*/6,
20526        // (intrinsic_void 969:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (CDP (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20527        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP,
20528        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20529        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20530        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRd
20531        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRn
20532        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // CRm
20533        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/6, // opc2
20534        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20535        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20536        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, 6, GIU_MergeMemOperands_EndOfList,
20537        GIR_EraseFromParent, /*InsnID*/0,
20538        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20539        // GIR_Coverage, 255,
20540        GIR_Done,
20541      // Label 1038: @52601
20542      GIM_Try, /*On fail goto*//*Label 1039*/ 52723, // Rule ID 256 //
20543        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
20544        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2,
20545        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20546        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20547        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20548        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20549        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20550        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20551        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20552        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20553        // MIs[1] Operand 1
20554        // No operand predicates
20555        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20556        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20557        // MIs[2] Operand 1
20558        // No operand predicates
20559        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
20560        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20561        // MIs[3] Operand 1
20562        // No operand predicates
20563        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/4, // MIs[4]
20564        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20565        // MIs[4] Operand 1
20566        // No operand predicates
20567        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/5, // MIs[5]
20568        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20569        // MIs[5] Operand 1
20570        // No operand predicates
20571        GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/6, // MIs[6]
20572        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
20573        // MIs[6] Operand 1
20574        // No operand predicates
20575        GIM_CheckIsSafeToFold, /*InsnID*/1,
20576        GIM_CheckIsSafeToFold, /*InsnID*/2,
20577        GIM_CheckIsSafeToFold, /*InsnID*/3,
20578        GIM_CheckIsSafeToFold, /*InsnID*/4,
20579        GIM_CheckIsSafeToFold, /*InsnID*/5,
20580        GIM_CheckIsSafeToFold, /*InsnID*/6,
20581        // (intrinsic_void 970:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (CDP2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20582        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::CDP2,
20583        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20584        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20585        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRd
20586        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRn
20587        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // CRm
20588        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/6, // opc2
20589        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, 6, GIU_MergeMemOperands_EndOfList,
20590        GIR_EraseFromParent, /*InsnID*/0,
20591        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20592        // GIR_Coverage, 256,
20593        GIR_Done,
20594      // Label 1039: @52723
20595      GIM_Try, /*On fail goto*//*Label 1040*/ 52851, // Rule ID 610 //
20596        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
20597        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp,
20598        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20599        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20600        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20601        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20602        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20603        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20604        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20605        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20606        // MIs[1] Operand 1
20607        // No operand predicates
20608        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20609        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20610        // MIs[2] Operand 1
20611        // No operand predicates
20612        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
20613        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20614        // MIs[3] Operand 1
20615        // No operand predicates
20616        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/4, // MIs[4]
20617        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20618        // MIs[4] Operand 1
20619        // No operand predicates
20620        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/5, // MIs[5]
20621        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20622        // MIs[5] Operand 1
20623        // No operand predicates
20624        GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/6, // MIs[6]
20625        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
20626        // MIs[6] Operand 1
20627        // No operand predicates
20628        GIM_CheckIsSafeToFold, /*InsnID*/1,
20629        GIM_CheckIsSafeToFold, /*InsnID*/2,
20630        GIM_CheckIsSafeToFold, /*InsnID*/3,
20631        GIM_CheckIsSafeToFold, /*InsnID*/4,
20632        GIM_CheckIsSafeToFold, /*InsnID*/5,
20633        GIM_CheckIsSafeToFold, /*InsnID*/6,
20634        // (intrinsic_void 969:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (t2CDP (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20635        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP,
20636        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20637        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20638        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRd
20639        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRn
20640        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // CRm
20641        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/6, // opc2
20642        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20643        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20644        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, 6, GIU_MergeMemOperands_EndOfList,
20645        GIR_EraseFromParent, /*InsnID*/0,
20646        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20647        // GIR_Coverage, 610,
20648        GIR_Done,
20649      // Label 1040: @52851
20650      GIM_Try, /*On fail goto*//*Label 1041*/ 52979, // Rule ID 611 //
20651        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
20652        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_cdp2,
20653        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20654        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20655        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20656        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20657        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20658        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20659        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20660        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20661        // MIs[1] Operand 1
20662        // No operand predicates
20663        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20664        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20665        // MIs[2] Operand 1
20666        // No operand predicates
20667        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
20668        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20669        // MIs[3] Operand 1
20670        // No operand predicates
20671        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/4, // MIs[4]
20672        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20673        // MIs[4] Operand 1
20674        // No operand predicates
20675        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/5, // MIs[5]
20676        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20677        // MIs[5] Operand 1
20678        // No operand predicates
20679        GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/6, // MIs[6]
20680        GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT,
20681        // MIs[6] Operand 1
20682        // No operand predicates
20683        GIM_CheckIsSafeToFold, /*InsnID*/1,
20684        GIM_CheckIsSafeToFold, /*InsnID*/2,
20685        GIM_CheckIsSafeToFold, /*InsnID*/3,
20686        GIM_CheckIsSafeToFold, /*InsnID*/4,
20687        GIM_CheckIsSafeToFold, /*InsnID*/5,
20688        GIM_CheckIsSafeToFold, /*InsnID*/6,
20689        // (intrinsic_void 970:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (t2CDP2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20690        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2CDP2,
20691        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20692        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20693        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRd
20694        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRn
20695        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // CRm
20696        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/6, // opc2
20697        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20698        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20699        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, 6, GIU_MergeMemOperands_EndOfList,
20700        GIR_EraseFromParent, /*InsnID*/0,
20701        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20702        // GIR_Coverage, 611,
20703        GIR_Done,
20704      // Label 1041: @52979
20705      GIM_Try, /*On fail goto*//*Label 1042*/ 53102, // Rule ID 1765 //
20706        GIM_CheckFeatures, GIFBS_IsARM,
20707        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mrc,
20708        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20709        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20710        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20711        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20712        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20713        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20714        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRwithAPSRRegClassID,
20715        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20716        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20717        // MIs[1] Operand 1
20718        // No operand predicates
20719        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
20720        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20721        // MIs[2] Operand 1
20722        // No operand predicates
20723        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/4, // MIs[3]
20724        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20725        // MIs[3] Operand 1
20726        // No operand predicates
20727        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/5, // MIs[4]
20728        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20729        // MIs[4] Operand 1
20730        // No operand predicates
20731        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/6, // MIs[5]
20732        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20733        // MIs[5] Operand 1
20734        // No operand predicates
20735        GIM_CheckIsSafeToFold, /*InsnID*/1,
20736        GIM_CheckIsSafeToFold, /*InsnID*/2,
20737        GIM_CheckIsSafeToFold, /*InsnID*/3,
20738        GIM_CheckIsSafeToFold, /*InsnID*/4,
20739        GIM_CheckIsSafeToFold, /*InsnID*/5,
20740        // (intrinsic_w_chain:{ *:[i32] } 996:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (MRC:{ *:[i32] } (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20741        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MRC,
20742        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
20743        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20744        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20745        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRn
20746        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRm
20747        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // opc2
20748        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20749        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20750        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, GIU_MergeMemOperands_EndOfList,
20751        GIR_EraseFromParent, /*InsnID*/0,
20752        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20753        // GIR_Coverage, 1765,
20754        GIR_Done,
20755      // Label 1042: @53102
20756      GIM_Try, /*On fail goto*//*Label 1043*/ 53219, // Rule ID 1766 //
20757        GIM_CheckFeatures, GIFBS_HasV5T_IsARM,
20758        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mrc2,
20759        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20760        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20761        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20762        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20763        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20764        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20765        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRwithAPSRRegClassID,
20766        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20767        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20768        // MIs[1] Operand 1
20769        // No operand predicates
20770        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
20771        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20772        // MIs[2] Operand 1
20773        // No operand predicates
20774        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/4, // MIs[3]
20775        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20776        // MIs[3] Operand 1
20777        // No operand predicates
20778        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/5, // MIs[4]
20779        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20780        // MIs[4] Operand 1
20781        // No operand predicates
20782        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/6, // MIs[5]
20783        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20784        // MIs[5] Operand 1
20785        // No operand predicates
20786        GIM_CheckIsSafeToFold, /*InsnID*/1,
20787        GIM_CheckIsSafeToFold, /*InsnID*/2,
20788        GIM_CheckIsSafeToFold, /*InsnID*/3,
20789        GIM_CheckIsSafeToFold, /*InsnID*/4,
20790        GIM_CheckIsSafeToFold, /*InsnID*/5,
20791        // (intrinsic_w_chain:{ *:[i32] } 997:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (MRC2:{ *:[i32] } (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20792        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MRC2,
20793        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
20794        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20795        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20796        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRn
20797        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRm
20798        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // opc2
20799        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, GIU_MergeMemOperands_EndOfList,
20800        GIR_EraseFromParent, /*InsnID*/0,
20801        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20802        // GIR_Coverage, 1766,
20803        GIR_Done,
20804      // Label 1043: @53219
20805      GIM_Try, /*On fail goto*//*Label 1044*/ 53342, // Rule ID 1994 //
20806        GIM_CheckFeatures, GIFBS_HasV6T2_IsThumb2,
20807        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mrc,
20808        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20809        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20810        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20811        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20812        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20813        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20814        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRwithAPSRRegClassID,
20815        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20816        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20817        // MIs[1] Operand 1
20818        // No operand predicates
20819        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
20820        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20821        // MIs[2] Operand 1
20822        // No operand predicates
20823        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/4, // MIs[3]
20824        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20825        // MIs[3] Operand 1
20826        // No operand predicates
20827        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/5, // MIs[4]
20828        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20829        // MIs[4] Operand 1
20830        // No operand predicates
20831        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/6, // MIs[5]
20832        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20833        // MIs[5] Operand 1
20834        // No operand predicates
20835        GIM_CheckIsSafeToFold, /*InsnID*/1,
20836        GIM_CheckIsSafeToFold, /*InsnID*/2,
20837        GIM_CheckIsSafeToFold, /*InsnID*/3,
20838        GIM_CheckIsSafeToFold, /*InsnID*/4,
20839        GIM_CheckIsSafeToFold, /*InsnID*/5,
20840        // (intrinsic_w_chain:{ *:[i32] } 996:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (t2MRC:{ *:[i32] } (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20841        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MRC,
20842        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
20843        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20844        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20845        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRn
20846        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRm
20847        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // opc2
20848        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20849        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20850        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, GIU_MergeMemOperands_EndOfList,
20851        GIR_EraseFromParent, /*InsnID*/0,
20852        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20853        // GIR_Coverage, 1994,
20854        GIR_Done,
20855      // Label 1044: @53342
20856      GIM_Try, /*On fail goto*//*Label 1045*/ 53465, // Rule ID 1995 //
20857        GIM_CheckFeatures, GIFBS_HasV6T2_IsThumb2,
20858        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::arm_mrc2,
20859        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
20860        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20861        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20862        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20863        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20864        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20865        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRwithAPSRRegClassID,
20866        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
20867        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20868        // MIs[1] Operand 1
20869        // No operand predicates
20870        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
20871        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20872        // MIs[2] Operand 1
20873        // No operand predicates
20874        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/4, // MIs[3]
20875        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20876        // MIs[3] Operand 1
20877        // No operand predicates
20878        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/5, // MIs[4]
20879        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20880        // MIs[4] Operand 1
20881        // No operand predicates
20882        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/6, // MIs[5]
20883        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20884        // MIs[5] Operand 1
20885        // No operand predicates
20886        GIM_CheckIsSafeToFold, /*InsnID*/1,
20887        GIM_CheckIsSafeToFold, /*InsnID*/2,
20888        GIM_CheckIsSafeToFold, /*InsnID*/3,
20889        GIM_CheckIsSafeToFold, /*InsnID*/4,
20890        GIM_CheckIsSafeToFold, /*InsnID*/5,
20891        // (intrinsic_w_chain:{ *:[i32] } 997:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (t2MRC2:{ *:[i32] } (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20892        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MRC2,
20893        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rt
20894        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20895        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20896        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRn
20897        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRm
20898        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // opc2
20899        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20900        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20901        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, GIU_MergeMemOperands_EndOfList,
20902        GIR_EraseFromParent, /*InsnID*/0,
20903        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20904        // GIR_Coverage, 1995,
20905        GIR_Done,
20906      // Label 1045: @53465
20907      GIM_Try, /*On fail goto*//*Label 1046*/ 53588, // Rule ID 265 //
20908        GIM_CheckFeatures, GIFBS_IsARM,
20909        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr,
20910        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20911        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20912        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20913        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20914        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20915        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20916        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20917        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20918        // MIs[1] Operand 1
20919        // No operand predicates
20920        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20921        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20922        // MIs[2] Operand 1
20923        // No operand predicates
20924        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20925        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/4, // MIs[3]
20926        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20927        // MIs[3] Operand 1
20928        // No operand predicates
20929        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/5, // MIs[4]
20930        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20931        // MIs[4] Operand 1
20932        // No operand predicates
20933        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/6, // MIs[5]
20934        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20935        // MIs[5] Operand 1
20936        // No operand predicates
20937        GIM_CheckIsSafeToFold, /*InsnID*/1,
20938        GIM_CheckIsSafeToFold, /*InsnID*/2,
20939        GIM_CheckIsSafeToFold, /*InsnID*/3,
20940        GIM_CheckIsSafeToFold, /*InsnID*/4,
20941        GIM_CheckIsSafeToFold, /*InsnID*/5,
20942        // (intrinsic_void 992:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (MCR (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20943        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR,
20944        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20945        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20946        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
20947        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRn
20948        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRm
20949        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // opc2
20950        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
20951        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
20952        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, GIU_MergeMemOperands_EndOfList,
20953        GIR_EraseFromParent, /*InsnID*/0,
20954        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
20955        // GIR_Coverage, 265,
20956        GIR_Done,
20957      // Label 1046: @53588
20958      GIM_Try, /*On fail goto*//*Label 1047*/ 53705, // Rule ID 266 //
20959        GIM_CheckFeatures, GIFBS_IsARM_PreV8,
20960        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2,
20961        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
20962        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
20963        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
20964        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
20965        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
20966        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
20967        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20968        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
20969        // MIs[1] Operand 1
20970        // No operand predicates
20971        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
20972        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
20973        // MIs[2] Operand 1
20974        // No operand predicates
20975        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
20976        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/4, // MIs[3]
20977        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
20978        // MIs[3] Operand 1
20979        // No operand predicates
20980        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/5, // MIs[4]
20981        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
20982        // MIs[4] Operand 1
20983        // No operand predicates
20984        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/6, // MIs[5]
20985        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
20986        // MIs[5] Operand 1
20987        // No operand predicates
20988        GIM_CheckIsSafeToFold, /*InsnID*/1,
20989        GIM_CheckIsSafeToFold, /*InsnID*/2,
20990        GIM_CheckIsSafeToFold, /*InsnID*/3,
20991        GIM_CheckIsSafeToFold, /*InsnID*/4,
20992        GIM_CheckIsSafeToFold, /*InsnID*/5,
20993        // (intrinsic_void 993:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (MCR2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
20994        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR2,
20995        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
20996        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20997        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
20998        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRn
20999        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRm
21000        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // opc2
21001        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, GIU_MergeMemOperands_EndOfList,
21002        GIR_EraseFromParent, /*InsnID*/0,
21003        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21004        // GIR_Coverage, 266,
21005        GIR_Done,
21006      // Label 1047: @53705
21007      GIM_Try, /*On fail goto*//*Label 1048*/ 53828, // Rule ID 606 //
21008        GIM_CheckFeatures, GIFBS_IsThumb2,
21009        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr,
21010        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21011        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21012        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21013        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21014        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
21015        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
21016        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21017        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21018        // MIs[1] Operand 1
21019        // No operand predicates
21020        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
21021        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
21022        // MIs[2] Operand 1
21023        // No operand predicates
21024        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
21025        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/4, // MIs[3]
21026        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
21027        // MIs[3] Operand 1
21028        // No operand predicates
21029        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/5, // MIs[4]
21030        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
21031        // MIs[4] Operand 1
21032        // No operand predicates
21033        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/6, // MIs[5]
21034        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
21035        // MIs[5] Operand 1
21036        // No operand predicates
21037        GIM_CheckIsSafeToFold, /*InsnID*/1,
21038        GIM_CheckIsSafeToFold, /*InsnID*/2,
21039        GIM_CheckIsSafeToFold, /*InsnID*/3,
21040        GIM_CheckIsSafeToFold, /*InsnID*/4,
21041        GIM_CheckIsSafeToFold, /*InsnID*/5,
21042        // (intrinsic_void 992:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (t2MCR (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
21043        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR,
21044        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
21045        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
21046        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
21047        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRn
21048        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRm
21049        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // opc2
21050        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21051        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21052        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, GIU_MergeMemOperands_EndOfList,
21053        GIR_EraseFromParent, /*InsnID*/0,
21054        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21055        // GIR_Coverage, 606,
21056        GIR_Done,
21057      // Label 1048: @53828
21058      GIM_Try, /*On fail goto*//*Label 1049*/ 53951, // Rule ID 607 //
21059        GIM_CheckFeatures, GIFBS_IsThumb2_PreV8,
21060        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::arm_mcr2,
21061        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21062        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21063        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
21064        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
21065        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
21066        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
21067        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21068        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21069        // MIs[1] Operand 1
21070        // No operand predicates
21071        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
21072        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
21073        // MIs[2] Operand 1
21074        // No operand predicates
21075        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::GPRRegClassID,
21076        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/4, // MIs[3]
21077        GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT,
21078        // MIs[3] Operand 1
21079        // No operand predicates
21080        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/5, // MIs[4]
21081        GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT,
21082        // MIs[4] Operand 1
21083        // No operand predicates
21084        GIM_RecordInsn, /*DefineMI*/5, /*MI*/0, /*OpIdx*/6, // MIs[5]
21085        GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT,
21086        // MIs[5] Operand 1
21087        // No operand predicates
21088        GIM_CheckIsSafeToFold, /*InsnID*/1,
21089        GIM_CheckIsSafeToFold, /*InsnID*/2,
21090        GIM_CheckIsSafeToFold, /*InsnID*/3,
21091        GIM_CheckIsSafeToFold, /*InsnID*/4,
21092        GIM_CheckIsSafeToFold, /*InsnID*/5,
21093        // (intrinsic_void 993:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)  =>  (t2MCR2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
21094        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MCR2,
21095        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // cop
21096        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
21097        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Rt
21098        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // CRn
21099        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // CRm
21100        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // opc2
21101        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21102        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21103        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, 3, 4, 5, GIU_MergeMemOperands_EndOfList,
21104        GIR_EraseFromParent, /*InsnID*/0,
21105        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21106        // GIR_Coverage, 607,
21107        GIR_Done,
21108      // Label 1049: @53951
21109      GIM_Reject,
21110    // Label 1037: @53952
21111    GIM_Reject,
21112    // Label 11: @53953
21113    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1053*/ 54075,
21114    /*GILLT_v2s64*//*Label 1050*/ 53964, 0,
21115    /*GILLT_v4s32*//*Label 1051*/ 54001, 0,
21116    /*GILLT_v8s16*//*Label 1052*/ 54038,
21117    // Label 1050: @53964
21118    GIM_Try, /*On fail goto*//*Label 1054*/ 54000, // Rule ID 2278 //
21119      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
21120      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21121      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21122      // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
21123      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
21124      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21125      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21126      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21127      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21128      GIR_EraseFromParent, /*InsnID*/0,
21129      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21130      // GIR_Coverage, 2278,
21131      GIR_Done,
21132    // Label 1054: @54000
21133    GIM_Reject,
21134    // Label 1051: @54001
21135    GIM_Try, /*On fail goto*//*Label 1055*/ 54037, // Rule ID 2277 //
21136      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
21137      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21138      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21139      // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
21140      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
21141      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21142      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21143      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21144      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21145      GIR_EraseFromParent, /*InsnID*/0,
21146      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21147      // GIR_Coverage, 2277,
21148      GIR_Done,
21149    // Label 1055: @54037
21150    GIM_Reject,
21151    // Label 1052: @54038
21152    GIM_Try, /*On fail goto*//*Label 1056*/ 54074, // Rule ID 2276 //
21153      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
21154      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21155      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21156      // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
21157      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
21158      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21159      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21160      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21161      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21162      GIR_EraseFromParent, /*InsnID*/0,
21163      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21164      // GIR_Coverage, 2276,
21165      GIR_Done,
21166    // Label 1056: @54074
21167    GIM_Reject,
21168    // Label 1053: @54075
21169    GIM_Reject,
21170    // Label 12: @54076
21171    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 8, /*)*//*default:*//*Label 1060*/ 54204,
21172    /*GILLT_v2s32*//*Label 1057*/ 54087, 0,
21173    /*GILLT_v4s16*//*Label 1058*/ 54126, 0,
21174    /*GILLT_v8s8*//*Label 1059*/ 54165,
21175    // Label 1057: @54087
21176    GIM_Try, /*On fail goto*//*Label 1061*/ 54125, // Rule ID 1559 //
21177      GIM_CheckFeatures, GIFBS_HasNEON,
21178      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
21179      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21180      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
21181      // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)  =>  (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
21182      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv2i32,
21183      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21184      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21185      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21186      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21187      GIR_EraseFromParent, /*InsnID*/0,
21188      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21189      // GIR_Coverage, 1559,
21190      GIR_Done,
21191    // Label 1061: @54125
21192    GIM_Reject,
21193    // Label 1058: @54126
21194    GIM_Try, /*On fail goto*//*Label 1062*/ 54164, // Rule ID 1558 //
21195      GIM_CheckFeatures, GIFBS_HasNEON,
21196      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
21197      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21198      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
21199      // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)  =>  (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
21200      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv4i16,
21201      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21202      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21203      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21204      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21205      GIR_EraseFromParent, /*InsnID*/0,
21206      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21207      // GIR_Coverage, 1558,
21208      GIR_Done,
21209    // Label 1062: @54164
21210    GIM_Reject,
21211    // Label 1059: @54165
21212    GIM_Try, /*On fail goto*//*Label 1063*/ 54203, // Rule ID 1557 //
21213      GIM_CheckFeatures, GIFBS_HasNEON,
21214      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
21215      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21216      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
21217      // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)  =>  (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
21218      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVNv8i8,
21219      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21220      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21221      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21222      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21223      GIR_EraseFromParent, /*InsnID*/0,
21224      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21225      // GIR_Coverage, 1557,
21226      GIR_Done,
21227    // Label 1063: @54203
21228    GIM_Reject,
21229    // Label 1060: @54204
21230    GIM_Reject,
21231    // Label 13: @54205
21232    GIM_Try, /*On fail goto*//*Label 1064*/ 54369,
21233      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21234      GIM_Try, /*On fail goto*//*Label 1065*/ 54246, // Rule ID 408 //
21235        GIM_CheckFeatures, GIFBS_IsThumb2,
21236        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
21237        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21238        // MIs[0] Operand 1
21239        // No operand predicates
21240        // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm  =>  (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
21241        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi,
21242        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21243        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
21244        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21245        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21246        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21247        GIR_EraseFromParent, /*InsnID*/0,
21248        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21249        // GIR_Coverage, 408,
21250        GIR_Done,
21251      // Label 1065: @54246
21252      GIM_Try, /*On fail goto*//*Label 1066*/ 54281, // Rule ID 59 //
21253        GIM_CheckFeatures, GIFBS_IsARM,
21254        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
21255        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
21256        // MIs[0] Operand 1
21257        // No operand predicates
21258        // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm  =>  (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
21259        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi,
21260        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21261        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
21262        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21263        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21264        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21265        GIR_EraseFromParent, /*InsnID*/0,
21266        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21267        // GIR_Coverage, 59,
21268        GIR_Done,
21269      // Label 1066: @54281
21270      GIM_Try, /*On fail goto*//*Label 1067*/ 54345,
21271        GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_imm0_65535,
21272        GIM_Try, /*On fail goto*//*Label 1068*/ 54315, // Rule ID 60 //
21273          GIM_CheckFeatures, GIFBS_HasV6T2_IsARM,
21274          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
21275          // MIs[0] Operand 1
21276          // No operand predicates
21277          // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm  =>  (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
21278          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MOVi16,
21279          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21280          GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
21281          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21282          GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21283          GIR_EraseFromParent, /*InsnID*/0,
21284          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21285          // GIR_Coverage, 60,
21286          GIR_Done,
21287        // Label 1068: @54315
21288        GIM_Try, /*On fail goto*//*Label 1069*/ 54344, // Rule ID 409 //
21289          GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb,
21290          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21291          // MIs[0] Operand 1
21292          // No operand predicates
21293          // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm  =>  (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
21294          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi16,
21295          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21296          GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
21297          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21298          GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21299          GIR_EraseFromParent, /*InsnID*/0,
21300          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21301          // GIR_Coverage, 409,
21302          GIR_Done,
21303        // Label 1069: @54344
21304        GIM_Reject,
21305      // Label 1067: @54345
21306      GIM_Try, /*On fail goto*//*Label 1070*/ 54368, // Rule ID 595 //
21307        GIM_CheckFeatures, GIFBS_IsThumb_UseMovt,
21308        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21309        // MIs[0] Operand 1
21310        // No operand predicates
21311        // (imm:{ *:[i32] }):$src  =>  (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
21312        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MOVi32imm,
21313        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
21314        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
21315        GIR_EraseFromParent, /*InsnID*/0,
21316        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21317        // GIR_Coverage, 595,
21318        GIR_Done,
21319      // Label 1070: @54368
21320      GIM_Reject,
21321    // Label 1064: @54369
21322    GIM_Reject,
21323    // Label 14: @54370
21324    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1074*/ 54498,
21325    /*GILLT_v2s64*//*Label 1071*/ 54381, 0,
21326    /*GILLT_v4s32*//*Label 1072*/ 54420, 0,
21327    /*GILLT_v8s16*//*Label 1073*/ 54459,
21328    // Label 1071: @54381
21329    GIM_Try, /*On fail goto*//*Label 1075*/ 54419, // Rule ID 1571 //
21330      GIM_CheckFeatures, GIFBS_HasNEON,
21331      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
21332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21333      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21334      // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
21335      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv2i64,
21336      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21337      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21338      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21339      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21340      GIR_EraseFromParent, /*InsnID*/0,
21341      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21342      // GIR_Coverage, 1571,
21343      GIR_Done,
21344    // Label 1075: @54419
21345    GIM_Reject,
21346    // Label 1072: @54420
21347    GIM_Try, /*On fail goto*//*Label 1076*/ 54458, // Rule ID 1570 //
21348      GIM_CheckFeatures, GIFBS_HasNEON,
21349      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
21350      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21351      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21352      // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
21353      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv4i32,
21354      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21355      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21356      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21357      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21358      GIR_EraseFromParent, /*InsnID*/0,
21359      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21360      // GIR_Coverage, 1570,
21361      GIR_Done,
21362    // Label 1076: @54458
21363    GIM_Reject,
21364    // Label 1073: @54459
21365    GIM_Try, /*On fail goto*//*Label 1077*/ 54497, // Rule ID 1569 //
21366      GIM_CheckFeatures, GIFBS_HasNEON,
21367      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
21368      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21369      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21370      // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
21371      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLsv8i16,
21372      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21373      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21374      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21375      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21376      GIR_EraseFromParent, /*InsnID*/0,
21377      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21378      // GIR_Coverage, 1569,
21379      GIR_Done,
21380    // Label 1077: @54497
21381    GIM_Reject,
21382    // Label 1074: @54498
21383    GIM_Reject,
21384    // Label 15: @54499
21385    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1081*/ 55008,
21386    /*GILLT_v2s64*//*Label 1078*/ 54510, 0,
21387    /*GILLT_v4s32*//*Label 1079*/ 54676, 0,
21388    /*GILLT_v8s16*//*Label 1080*/ 54842,
21389    // Label 1078: @54510
21390    GIM_Try, /*On fail goto*//*Label 1082*/ 54675,
21391      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
21392      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21393      GIM_Try, /*On fail goto*//*Label 1083*/ 54582, // Rule ID 1146 //
21394        GIM_CheckFeatures, GIFBS_HasNEON,
21395        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21396        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
21397        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
21398        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
21399        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
21400        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
21401        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21402        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21403        GIM_CheckIsSafeToFold, /*InsnID*/1,
21404        // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1016:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21405        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv2i64,
21406        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21407        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
21408        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
21409        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21410        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21411        GIR_EraseFromParent, /*InsnID*/0,
21412        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21413        // GIR_Coverage, 1146,
21414        GIR_Done,
21415      // Label 1083: @54582
21416      GIM_Try, /*On fail goto*//*Label 1084*/ 54644, // Rule ID 1149 //
21417        GIM_CheckFeatures, GIFBS_HasNEON,
21418        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21419        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
21420        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
21421        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
21422        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
21423        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
21424        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21425        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21426        GIM_CheckIsSafeToFold, /*InsnID*/1,
21427        // (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1017:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))  =>  (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21428        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv2i64,
21429        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21430        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
21431        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
21432        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21433        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21434        GIR_EraseFromParent, /*InsnID*/0,
21435        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21436        // GIR_Coverage, 1149,
21437        GIR_Done,
21438      // Label 1084: @54644
21439      GIM_Try, /*On fail goto*//*Label 1085*/ 54674, // Rule ID 1574 //
21440        GIM_CheckFeatures, GIFBS_HasNEON,
21441        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21442        // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)  =>  (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
21443        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv2i64,
21444        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21445        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21446        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21447        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21448        GIR_EraseFromParent, /*InsnID*/0,
21449        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21450        // GIR_Coverage, 1574,
21451        GIR_Done,
21452      // Label 1085: @54674
21453      GIM_Reject,
21454    // Label 1082: @54675
21455    GIM_Reject,
21456    // Label 1079: @54676
21457    GIM_Try, /*On fail goto*//*Label 1086*/ 54841,
21458      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
21459      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21460      GIM_Try, /*On fail goto*//*Label 1087*/ 54748, // Rule ID 1145 //
21461        GIM_CheckFeatures, GIFBS_HasNEON,
21462        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21463        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
21464        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
21465        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
21466        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
21467        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
21468        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21469        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21470        GIM_CheckIsSafeToFold, /*InsnID*/1,
21471        // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1016:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21472        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv4i32,
21473        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21474        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
21475        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
21476        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21477        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21478        GIR_EraseFromParent, /*InsnID*/0,
21479        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21480        // GIR_Coverage, 1145,
21481        GIR_Done,
21482      // Label 1087: @54748
21483      GIM_Try, /*On fail goto*//*Label 1088*/ 54810, // Rule ID 1148 //
21484        GIM_CheckFeatures, GIFBS_HasNEON,
21485        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21486        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
21487        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
21488        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
21489        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
21490        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
21491        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21492        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21493        GIM_CheckIsSafeToFold, /*InsnID*/1,
21494        // (zext:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 1017:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))  =>  (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21495        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv4i32,
21496        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21497        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
21498        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
21499        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21500        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21501        GIR_EraseFromParent, /*InsnID*/0,
21502        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21503        // GIR_Coverage, 1148,
21504        GIR_Done,
21505      // Label 1088: @54810
21506      GIM_Try, /*On fail goto*//*Label 1089*/ 54840, // Rule ID 1573 //
21507        GIM_CheckFeatures, GIFBS_HasNEON,
21508        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21509        // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)  =>  (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
21510        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv4i32,
21511        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21512        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21513        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21514        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21515        GIR_EraseFromParent, /*InsnID*/0,
21516        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21517        // GIR_Coverage, 1573,
21518        GIR_Done,
21519      // Label 1089: @54840
21520      GIM_Reject,
21521    // Label 1086: @54841
21522    GIM_Reject,
21523    // Label 1080: @54842
21524    GIM_Try, /*On fail goto*//*Label 1090*/ 55007,
21525      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s8,
21526      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21527      GIM_Try, /*On fail goto*//*Label 1091*/ 54914, // Rule ID 1144 //
21528        GIM_CheckFeatures, GIFBS_HasNEON,
21529        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21530        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
21531        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
21532        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
21533        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
21534        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
21535        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21536        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21537        GIM_CheckIsSafeToFold, /*InsnID*/1,
21538        // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1016:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21539        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLsv8i16,
21540        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21541        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
21542        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
21543        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21544        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21545        GIR_EraseFromParent, /*InsnID*/0,
21546        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21547        // GIR_Coverage, 1144,
21548        GIR_Done,
21549      // Label 1091: @54914
21550      GIM_Try, /*On fail goto*//*Label 1092*/ 54976, // Rule ID 1147 //
21551        GIM_CheckFeatures, GIFBS_HasNEON,
21552        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21553        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
21554        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
21555        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
21556        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
21557        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
21558        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21559        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
21560        GIM_CheckIsSafeToFold, /*InsnID*/1,
21561        // (zext:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i8] } 1017:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))  =>  (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21562        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABDLuv8i16,
21563        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21564        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
21565        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
21566        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21567        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21568        GIR_EraseFromParent, /*InsnID*/0,
21569        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21570        // GIR_Coverage, 1147,
21571        GIR_Done,
21572      // Label 1092: @54976
21573      GIM_Try, /*On fail goto*//*Label 1093*/ 55006, // Rule ID 1572 //
21574        GIM_CheckFeatures, GIFBS_HasNEON,
21575        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21576        // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)  =>  (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
21577        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMOVLuv8i16,
21578        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21579        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
21580        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21581        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21582        GIR_EraseFromParent, /*InsnID*/0,
21583        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21584        // GIR_Coverage, 1572,
21585        GIR_Done,
21586      // Label 1093: @55006
21587      GIM_Reject,
21588    // Label 1090: @55007
21589    GIM_Reject,
21590    // Label 1081: @55008
21591    GIM_Reject,
21592    // Label 16: @55009
21593    GIM_Try, /*On fail goto*//*Label 1094*/ 55113,
21594      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21595      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21596      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21597      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21598      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
21599      GIM_Try, /*On fail goto*//*Label 1095*/ 55075, // Rule ID 474 //
21600        GIM_CheckFeatures, GIFBS_IsThumb2,
21601        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21602        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
21603        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm1_31,
21604        // MIs[1] Operand 1
21605        // No operand predicates
21606        GIM_CheckIsSafeToFold, /*InsnID*/1,
21607        // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm)  =>  (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
21608        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLri,
21609        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21610        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
21611        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
21612        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21613        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21614        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21615        GIR_EraseFromParent, /*InsnID*/0,
21616        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21617        // GIR_Coverage, 474,
21618        GIR_Done,
21619      // Label 1095: @55075
21620      GIM_Try, /*On fail goto*//*Label 1096*/ 55112, // Rule ID 475 //
21621        GIM_CheckFeatures, GIFBS_IsThumb2,
21622        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21623        // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
21624        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSLrr,
21625        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21626        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
21627        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
21628        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21629        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21630        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21631        GIR_EraseFromParent, /*InsnID*/0,
21632        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21633        // GIR_Coverage, 475,
21634        GIR_Done,
21635      // Label 1096: @55112
21636      GIM_Reject,
21637    // Label 1094: @55113
21638    GIM_Reject,
21639    // Label 17: @55114
21640    GIM_Try, /*On fail goto*//*Label 1097*/ 55171, // Rule ID 477 //
21641      GIM_CheckFeatures, GIFBS_IsThumb2,
21642      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21643      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21644      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21645      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21646      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
21647      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21648      // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
21649      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2LSRrr,
21650      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21651      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
21652      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
21653      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21654      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21655      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21656      GIR_EraseFromParent, /*InsnID*/0,
21657      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21658      // GIR_Coverage, 477,
21659      GIR_Done,
21660    // Label 1097: @55171
21661    GIM_Reject,
21662    // Label 18: @55172
21663    GIM_Try, /*On fail goto*//*Label 1098*/ 55384,
21664      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
21665      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21666      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21667      GIM_Try, /*On fail goto*//*Label 1099*/ 55237, // Rule ID 203 //
21668        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
21669        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
21670        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21671        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
21672        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
21673        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
21674        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
21675        GIM_CheckIsSafeToFold, /*InsnID*/1,
21676        // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
21677        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REVSH,
21678        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21679        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
21680        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21681        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21682        GIR_EraseFromParent, /*InsnID*/0,
21683        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21684        // GIR_Coverage, 203,
21685        GIR_Done,
21686      // Label 1099: @55237
21687      GIM_Try, /*On fail goto*//*Label 1100*/ 55288, // Rule ID 336 //
21688        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
21689        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
21690        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21691        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
21692        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
21693        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
21694        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
21695        GIM_CheckIsSafeToFold, /*InsnID*/1,
21696        // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
21697        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREVSH,
21698        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21699        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
21700        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21701        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21702        GIR_EraseFromParent, /*InsnID*/0,
21703        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21704        // GIR_Coverage, 336,
21705        GIR_Done,
21706      // Label 1100: @55288
21707      GIM_Try, /*On fail goto*//*Label 1101*/ 55383,
21708        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
21709        GIM_Try, /*On fail goto*//*Label 1102*/ 55341, // Rule ID 542 //
21710          GIM_CheckFeatures, GIFBS_IsThumb2,
21711          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21712          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BSWAP,
21713          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
21714          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
21715          GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 16,
21716          GIM_CheckIsSafeToFold, /*InsnID*/1,
21717          // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] })  =>  (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
21718          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REVSH,
21719          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21720          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
21721          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21722          GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21723          GIR_EraseFromParent, /*InsnID*/0,
21724          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21725          // GIR_Coverage, 542,
21726          GIR_Done,
21727        // Label 1102: @55341
21728        GIM_Try, /*On fail goto*//*Label 1103*/ 55382, // Rule ID 479 //
21729          GIM_CheckFeatures, GIFBS_IsThumb2,
21730          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
21731          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
21732          // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)  =>  (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
21733          GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ASRrr,
21734          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
21735          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
21736          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
21737          GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21738          GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21739          GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21740          GIR_EraseFromParent, /*InsnID*/0,
21741          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21742          // GIR_Coverage, 479,
21743          GIR_Done,
21744        // Label 1103: @55382
21745        GIM_Reject,
21746      // Label 1101: @55383
21747      GIM_Reject,
21748    // Label 1098: @55384
21749    GIM_Reject,
21750    // Label 19: @55385
21751    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 9, /*)*//*default:*//*Label 1111*/ 56015,
21752    /*GILLT_s16*//*Label 1104*/ 55400,
21753    /*GILLT_s32*//*Label 1105*/ 55451,
21754    /*GILLT_s64*//*Label 1106*/ 55502,
21755    /*GILLT_v2s32*//*Label 1107*/ 55553, 0,
21756    /*GILLT_v4s16*//*Label 1108*/ 55604,
21757    /*GILLT_v4s32*//*Label 1109*/ 55784, 0,
21758    /*GILLT_v8s16*//*Label 1110*/ 55835,
21759    // Label 1104: @55400
21760    GIM_Try, /*On fail goto*//*Label 1112*/ 55450, // Rule ID 620 //
21761      GIM_CheckFeatures, GIFBS_HasFullFP16,
21762      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
21763      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
21764      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
21765      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
21766      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
21767      // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
21768      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDH,
21769      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
21770      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
21771      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
21772      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21773      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21774      GIR_EraseFromParent, /*InsnID*/0,
21775      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21776      // GIR_Coverage, 620,
21777      GIR_Done,
21778    // Label 1112: @55450
21779    GIM_Reject,
21780    // Label 1105: @55451
21781    GIM_Try, /*On fail goto*//*Label 1113*/ 55501, // Rule ID 619 //
21782      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
21783      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
21784      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
21785      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
21786      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
21787      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
21788      // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
21789      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDS,
21790      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
21791      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
21792      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
21793      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21794      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21795      GIR_EraseFromParent, /*InsnID*/0,
21796      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21797      // GIR_Coverage, 619,
21798      GIR_Done,
21799    // Label 1113: @55501
21800    GIM_Reject,
21801    // Label 1106: @55502
21802    GIM_Try, /*On fail goto*//*Label 1114*/ 55552, // Rule ID 618 //
21803      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
21804      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
21805      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
21806      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21807      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21808      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21809      // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
21810      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDD,
21811      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
21812      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
21813      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
21814      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21815      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21816      GIR_EraseFromParent, /*InsnID*/0,
21817      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21818      // GIR_Coverage, 618,
21819      GIR_Done,
21820    // Label 1114: @55552
21821    GIM_Reject,
21822    // Label 1107: @55553
21823    GIM_Try, /*On fail goto*//*Label 1115*/ 55603, // Rule ID 762 //
21824      GIM_CheckFeatures, GIFBS_HasNEON,
21825      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
21826      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
21827      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21828      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21829      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21830      // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21831      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfd,
21832      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21833      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21834      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21835      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21836      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21837      GIR_EraseFromParent, /*InsnID*/0,
21838      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21839      // GIR_Coverage, 762,
21840      GIR_Done,
21841    // Label 1115: @55603
21842    GIM_Reject,
21843    // Label 1108: @55604
21844    GIM_Try, /*On fail goto*//*Label 1116*/ 55783,
21845      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
21846      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
21847      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
21848      GIM_Try, /*On fail goto*//*Label 1117*/ 55681, // Rule ID 2657 //
21849        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
21850        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21851        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21852        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
21853        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
21854        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21855        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21856        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21857        GIM_CheckIsSafeToFold, /*InsnID*/1,
21858        // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1)  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21859        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
21860        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21861        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21862        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
21863        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
21864        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21865        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21866        GIR_EraseFromParent, /*InsnID*/0,
21867        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21868        // GIR_Coverage, 2657,
21869        GIR_Done,
21870      // Label 1117: @55681
21871      GIM_Try, /*On fail goto*//*Label 1118*/ 55744, // Rule ID 931 //
21872        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
21873        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21874        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21875        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21876        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
21877        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
21878        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21879        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21880        GIM_CheckIsSafeToFold, /*InsnID*/1,
21881        // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21882        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhd,
21883        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21884        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
21885        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
21886        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
21887        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21888        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21889        GIR_EraseFromParent, /*InsnID*/0,
21890        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21891        // GIR_Coverage, 931,
21892        GIR_Done,
21893      // Label 1118: @55744
21894      GIM_Try, /*On fail goto*//*Label 1119*/ 55782, // Rule ID 764 //
21895        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21896        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
21897        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
21898        // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21899        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhd,
21900        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21901        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21902        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21903        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21904        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21905        GIR_EraseFromParent, /*InsnID*/0,
21906        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21907        // GIR_Coverage, 764,
21908        GIR_Done,
21909      // Label 1119: @55782
21910      GIM_Reject,
21911    // Label 1116: @55783
21912    GIM_Reject,
21913    // Label 1109: @55784
21914    GIM_Try, /*On fail goto*//*Label 1120*/ 55834, // Rule ID 763 //
21915      GIM_CheckFeatures, GIFBS_HasNEON,
21916      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
21917      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
21918      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21919      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
21920      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21921      // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21922      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDfq,
21923      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21924      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21925      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21926      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21927      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21928      GIR_EraseFromParent, /*InsnID*/0,
21929      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21930      // GIR_Coverage, 763,
21931      GIR_Done,
21932    // Label 1120: @55834
21933    GIM_Reject,
21934    // Label 1110: @55835
21935    GIM_Try, /*On fail goto*//*Label 1121*/ 56014,
21936      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
21937      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
21938      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
21939      GIM_Try, /*On fail goto*//*Label 1122*/ 55912, // Rule ID 2658 //
21940        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
21941        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21942        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21943        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
21944        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
21945        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
21946        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21947        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21948        GIM_CheckIsSafeToFold, /*InsnID*/1,
21949        // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1)  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21950        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
21951        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21952        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
21953        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
21954        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
21955        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21956        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21957        GIR_EraseFromParent, /*InsnID*/0,
21958        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21959        // GIR_Coverage, 2658,
21960        GIR_Done,
21961      // Label 1122: @55912
21962      GIM_Try, /*On fail goto*//*Label 1123*/ 55975, // Rule ID 932 //
21963        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
21964        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
21965        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
21966        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
21967        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
21968        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
21969        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
21970        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21971        GIM_CheckIsSafeToFold, /*InsnID*/1,
21972        // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21973        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAhq,
21974        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21975        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
21976        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
21977        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
21978        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21979        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21980        GIR_EraseFromParent, /*InsnID*/0,
21981        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21982        // GIR_Coverage, 932,
21983        GIR_Done,
21984      // Label 1123: @55975
21985      GIM_Try, /*On fail goto*//*Label 1124*/ 56013, // Rule ID 765 //
21986        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
21987        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
21988        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
21989        // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21990        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDhq,
21991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
21992        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
21993        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
21994        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
21995        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
21996        GIR_EraseFromParent, /*InsnID*/0,
21997        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
21998        // GIR_Coverage, 765,
21999        GIR_Done,
22000      // Label 1124: @56013
22001      GIM_Reject,
22002    // Label 1121: @56014
22003    GIM_Reject,
22004    // Label 1111: @56015
22005    GIM_Reject,
22006    // Label 20: @56016
22007    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 9, /*)*//*default:*//*Label 1132*/ 56630,
22008    /*GILLT_s16*//*Label 1125*/ 56031,
22009    /*GILLT_s32*//*Label 1126*/ 56082,
22010    /*GILLT_s64*//*Label 1127*/ 56133,
22011    /*GILLT_v2s32*//*Label 1128*/ 56184, 0,
22012    /*GILLT_v4s16*//*Label 1129*/ 56235,
22013    /*GILLT_v4s32*//*Label 1130*/ 56407, 0,
22014    /*GILLT_v8s16*//*Label 1131*/ 56458,
22015    // Label 1125: @56031
22016    GIM_Try, /*On fail goto*//*Label 1133*/ 56081, // Rule ID 623 //
22017      GIM_CheckFeatures, GIFBS_HasFullFP16,
22018      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
22019      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
22020      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
22021      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
22022      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
22023      // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
22024      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBH,
22025      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22026      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
22027      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22028      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22029      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22030      GIR_EraseFromParent, /*InsnID*/0,
22031      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22032      // GIR_Coverage, 623,
22033      GIR_Done,
22034    // Label 1133: @56081
22035    GIM_Reject,
22036    // Label 1126: @56082
22037    GIM_Try, /*On fail goto*//*Label 1134*/ 56132, // Rule ID 622 //
22038      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
22039      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22040      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22041      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
22042      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22043      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
22044      // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
22045      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBS,
22046      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22047      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
22048      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22049      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22050      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22051      GIR_EraseFromParent, /*InsnID*/0,
22052      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22053      // GIR_Coverage, 622,
22054      GIR_Done,
22055    // Label 1134: @56132
22056    GIM_Reject,
22057    // Label 1127: @56133
22058    GIM_Try, /*On fail goto*//*Label 1135*/ 56183, // Rule ID 621 //
22059      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
22060      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22061      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22062      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22063      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22064      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22065      // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
22066      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBD,
22067      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22068      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
22069      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
22070      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22071      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22072      GIR_EraseFromParent, /*InsnID*/0,
22073      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22074      // GIR_Coverage, 621,
22075      GIR_Done,
22076    // Label 1135: @56183
22077    GIM_Reject,
22078    // Label 1128: @56184
22079    GIM_Try, /*On fail goto*//*Label 1136*/ 56234, // Rule ID 949 //
22080      GIM_CheckFeatures, GIFBS_HasNEON,
22081      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
22082      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22083      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22084      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22085      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22086      // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
22087      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfd,
22088      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22089      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22090      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22091      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22092      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22093      GIR_EraseFromParent, /*InsnID*/0,
22094      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22095      // GIR_Coverage, 949,
22096      GIR_Done,
22097    // Label 1136: @56234
22098    GIM_Reject,
22099    // Label 1129: @56235
22100    GIM_Try, /*On fail goto*//*Label 1137*/ 56406,
22101      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
22102      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22103      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22104      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22105      GIM_Try, /*On fail goto*//*Label 1138*/ 56312, // Rule ID 909 //
22106        GIM_CheckFeatures, GIFBS_DontUseFusedMAC_HasFullFP16_HasNEON_UseFPVMLx,
22107        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22108        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22109        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
22110        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
22111        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22112        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22113        GIM_CheckIsSafeToFold, /*InsnID*/1,
22114        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22115        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShd,
22116        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22117        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
22118        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
22119        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
22120        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22121        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22122        GIR_EraseFromParent, /*InsnID*/0,
22123        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22124        // GIR_Coverage, 909,
22125        GIR_Done,
22126      // Label 1138: @56312
22127      GIM_Try, /*On fail goto*//*Label 1139*/ 56371, // Rule ID 935 //
22128        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
22129        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22130        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22131        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
22132        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
22133        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22134        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22135        GIM_CheckIsSafeToFold, /*InsnID*/1,
22136        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm))  =>  (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22137        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShd,
22138        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
22140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
22141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
22142        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22143        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22144        GIR_EraseFromParent, /*InsnID*/0,
22145        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22146        // GIR_Coverage, 935,
22147        GIR_Done,
22148      // Label 1139: @56371
22149      GIM_Try, /*On fail goto*//*Label 1140*/ 56405, // Rule ID 951 //
22150        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
22151        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22152        // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22153        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhd,
22154        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22155        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22156        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22157        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22158        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22159        GIR_EraseFromParent, /*InsnID*/0,
22160        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22161        // GIR_Coverage, 951,
22162        GIR_Done,
22163      // Label 1140: @56405
22164      GIM_Reject,
22165    // Label 1137: @56406
22166    GIM_Reject,
22167    // Label 1130: @56407
22168    GIM_Try, /*On fail goto*//*Label 1141*/ 56457, // Rule ID 950 //
22169      GIM_CheckFeatures, GIFBS_HasNEON,
22170      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22171      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22172      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22173      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
22174      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22175      // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
22176      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBfq,
22177      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22178      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22179      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22180      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22181      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22182      GIR_EraseFromParent, /*InsnID*/0,
22183      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22184      // GIR_Coverage, 950,
22185      GIR_Done,
22186    // Label 1141: @56457
22187    GIM_Reject,
22188    // Label 1131: @56458
22189    GIM_Try, /*On fail goto*//*Label 1142*/ 56629,
22190      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
22191      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22192      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22193      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
22194      GIM_Try, /*On fail goto*//*Label 1143*/ 56535, // Rule ID 910 //
22195        GIM_CheckFeatures, GIFBS_DontUseFusedMAC_HasFullFP16_HasNEON_UseFPVMLx,
22196        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22197        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22198        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
22199        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
22200        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
22201        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22202        GIM_CheckIsSafeToFold, /*InsnID*/1,
22203        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
22204        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLShq,
22205        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22206        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
22207        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
22208        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
22209        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22210        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22211        GIR_EraseFromParent, /*InsnID*/0,
22212        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22213        // GIR_Coverage, 910,
22214        GIR_Done,
22215      // Label 1143: @56535
22216      GIM_Try, /*On fail goto*//*Label 1144*/ 56594, // Rule ID 936 //
22217        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
22218        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22219        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22220        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
22221        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
22222        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
22223        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22224        GIM_CheckIsSafeToFold, /*InsnID*/1,
22225        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm))  =>  (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
22226        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMShq,
22227        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22228        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
22229        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
22230        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
22231        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22232        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22233        GIR_EraseFromParent, /*InsnID*/0,
22234        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22235        // GIR_Coverage, 936,
22236        GIR_Done,
22237      // Label 1144: @56594
22238      GIM_Try, /*On fail goto*//*Label 1145*/ 56628, // Rule ID 952 //
22239        GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
22240        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22241        // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
22242        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSUBhq,
22243        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22244        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22245        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22246        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22247        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22248        GIR_EraseFromParent, /*InsnID*/0,
22249        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22250        // GIR_Coverage, 952,
22251        GIR_Done,
22252      // Label 1145: @56628
22253      GIM_Reject,
22254    // Label 1142: @56629
22255    GIM_Reject,
22256    // Label 1132: @56630
22257    GIM_Reject,
22258    // Label 21: @56631
22259    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 9, /*)*//*default:*//*Label 1153*/ 57213,
22260    /*GILLT_s16*//*Label 1146*/ 56646,
22261    /*GILLT_s32*//*Label 1147*/ 56697,
22262    /*GILLT_s64*//*Label 1148*/ 56853,
22263    /*GILLT_v2s32*//*Label 1149*/ 57009, 0,
22264    /*GILLT_v4s16*//*Label 1150*/ 57060,
22265    /*GILLT_v4s32*//*Label 1151*/ 57111, 0,
22266    /*GILLT_v8s16*//*Label 1152*/ 57162,
22267    // Label 1146: @56646
22268    GIM_Try, /*On fail goto*//*Label 1154*/ 56696, // Rule ID 629 //
22269      GIM_CheckFeatures, GIFBS_HasFullFP16,
22270      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
22271      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
22272      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
22273      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
22274      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
22275      // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
22276      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULH,
22277      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22278      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
22279      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22280      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22281      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22282      GIR_EraseFromParent, /*InsnID*/0,
22283      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22284      // GIR_Coverage, 629,
22285      GIR_Done,
22286    // Label 1154: @56696
22287    GIM_Reject,
22288    // Label 1147: @56697
22289    GIM_Try, /*On fail goto*//*Label 1155*/ 56852,
22290      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22291      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22292      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
22293      GIM_Try, /*On fail goto*//*Label 1156*/ 56762, // Rule ID 2030 //
22294        GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding,
22295        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22296        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22297        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22298        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22299        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
22300        GIM_CheckIsSafeToFold, /*InsnID*/1,
22301        // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b)  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
22302        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
22303        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22304        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
22305        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
22306        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22307        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22308        GIR_EraseFromParent, /*InsnID*/0,
22309        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22310        // GIR_Coverage, 2030,
22311        GIR_Done,
22312      // Label 1156: @56762
22313      GIM_Try, /*On fail goto*//*Label 1157*/ 56813, // Rule ID 2773 //
22314        GIM_CheckFeatures, GIFBS_NoHonorSignDependentRounding,
22315        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22316        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22317        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22318        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22319        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22320        GIM_CheckIsSafeToFold, /*InsnID*/1,
22321        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a))  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
22322        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
22323        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22324        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
22325        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
22326        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22327        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22328        GIR_EraseFromParent, /*InsnID*/0,
22329        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22330        // GIR_Coverage, 2773,
22331        GIR_Done,
22332      // Label 1157: @56813
22333      GIM_Try, /*On fail goto*//*Label 1158*/ 56851, // Rule ID 628 //
22334        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
22335        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22336        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
22337        // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
22338        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULS,
22339        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22340        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
22341        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22342        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22343        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22344        GIR_EraseFromParent, /*InsnID*/0,
22345        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22346        // GIR_Coverage, 628,
22347        GIR_Done,
22348      // Label 1158: @56851
22349      GIM_Reject,
22350    // Label 1155: @56852
22351    GIM_Reject,
22352    // Label 1148: @56853
22353    GIM_Try, /*On fail goto*//*Label 1159*/ 57008,
22354      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22355      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22356      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22357      GIM_Try, /*On fail goto*//*Label 1160*/ 56918, // Rule ID 2029 //
22358        GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding,
22359        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22360        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22361        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22362        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22363        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22364        GIM_CheckIsSafeToFold, /*InsnID*/1,
22365        // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b)  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
22366        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
22367        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22368        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
22369        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
22370        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22371        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22372        GIR_EraseFromParent, /*InsnID*/0,
22373        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22374        // GIR_Coverage, 2029,
22375        GIR_Done,
22376      // Label 1160: @56918
22377      GIM_Try, /*On fail goto*//*Label 1161*/ 56969, // Rule ID 2772 //
22378        GIM_CheckFeatures, GIFBS_HasDPVFP_NoHonorSignDependentRounding,
22379        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22380        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22381        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22382        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22383        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22384        GIM_CheckIsSafeToFold, /*InsnID*/1,
22385        // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a))  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
22386        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
22387        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22388        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
22389        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
22390        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22391        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22392        GIR_EraseFromParent, /*InsnID*/0,
22393        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22394        // GIR_Coverage, 2772,
22395        GIR_Done,
22396      // Label 1161: @56969
22397      GIM_Try, /*On fail goto*//*Label 1162*/ 57007, // Rule ID 627 //
22398        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
22399        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22400        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22401        // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
22402        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULD,
22403        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22404        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
22405        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
22406        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22407        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22408        GIR_EraseFromParent, /*InsnID*/0,
22409        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22410        // GIR_Coverage, 627,
22411        GIR_Done,
22412      // Label 1162: @57007
22413      GIM_Reject,
22414    // Label 1159: @57008
22415    GIM_Reject,
22416    // Label 1149: @57009
22417    GIM_Try, /*On fail goto*//*Label 1163*/ 57059, // Rule ID 829 //
22418      GIM_CheckFeatures, GIFBS_HasNEON,
22419      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
22420      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22421      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22422      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22423      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22424      // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)  =>  (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
22425      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfd,
22426      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22427      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22428      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22429      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22430      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22431      GIR_EraseFromParent, /*InsnID*/0,
22432      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22433      // GIR_Coverage, 829,
22434      GIR_Done,
22435    // Label 1163: @57059
22436    GIM_Reject,
22437    // Label 1150: @57060
22438    GIM_Try, /*On fail goto*//*Label 1164*/ 57110, // Rule ID 831 //
22439      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
22440      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
22441      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
22442      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22443      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22444      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22445      // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)  =>  (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22446      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhd,
22447      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22448      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22449      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22450      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22451      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22452      GIR_EraseFromParent, /*InsnID*/0,
22453      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22454      // GIR_Coverage, 831,
22455      GIR_Done,
22456    // Label 1164: @57110
22457    GIM_Reject,
22458    // Label 1151: @57111
22459    GIM_Try, /*On fail goto*//*Label 1165*/ 57161, // Rule ID 830 //
22460      GIM_CheckFeatures, GIFBS_HasNEON,
22461      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22462      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22463      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22464      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
22465      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22466      // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)  =>  (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
22467      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULfq,
22468      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22469      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22470      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22471      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22472      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22473      GIR_EraseFromParent, /*InsnID*/0,
22474      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22475      // GIR_Coverage, 830,
22476      GIR_Done,
22477    // Label 1165: @57161
22478    GIM_Reject,
22479    // Label 1152: @57162
22480    GIM_Try, /*On fail goto*//*Label 1166*/ 57212, // Rule ID 832 //
22481      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
22482      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
22483      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
22484      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22485      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
22486      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22487      // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)  =>  (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
22488      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMULhq,
22489      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22490      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22491      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22492      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22493      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22494      GIR_EraseFromParent, /*InsnID*/0,
22495      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22496      // GIR_Coverage, 832,
22497      GIR_Done,
22498    // Label 1166: @57212
22499    GIM_Reject,
22500    // Label 1153: @57213
22501    GIM_Reject,
22502    // Label 22: @57214
22503    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1171*/ 58106,
22504    /*GILLT_s32*//*Label 1167*/ 57226,
22505    /*GILLT_s64*//*Label 1168*/ 57541,
22506    /*GILLT_v2s32*//*Label 1169*/ 57856, 0, 0,
22507    /*GILLT_v4s32*//*Label 1170*/ 57981,
22508    // Label 1167: @57226
22509    GIM_Try, /*On fail goto*//*Label 1172*/ 57540,
22510      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22511      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22512      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
22513      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
22514      GIM_Try, /*On fail goto*//*Label 1173*/ 57316, // Rule ID 2114 //
22515        GIM_CheckFeatures, GIFBS_HasVFP4,
22516        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22517        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22518        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22519        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22520        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
22521        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
22522        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
22523        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22524        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22525        GIM_CheckIsSafeToFold, /*InsnID*/1,
22526        GIM_CheckIsSafeToFold, /*InsnID*/2,
22527        // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
22528        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
22529        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22530        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
22531        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
22532        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22533        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22534        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22535        GIR_EraseFromParent, /*InsnID*/0,
22536        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22537        // GIR_Coverage, 2114,
22538        GIR_Done,
22539      // Label 1173: @57316
22540      GIM_Try, /*On fail goto*//*Label 1174*/ 57375, // Rule ID 2106 //
22541        GIM_CheckFeatures, GIFBS_HasVFP4,
22542        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22543        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22544        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22545        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22546        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
22547        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
22548        GIM_CheckIsSafeToFold, /*InsnID*/1,
22549        // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)  =>  (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
22550        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
22551        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22552        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
22553        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
22554        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22555        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22556        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22557        GIR_EraseFromParent, /*InsnID*/0,
22558        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22559        // GIR_Coverage, 2106,
22560        GIR_Done,
22561      // Label 1174: @57375
22562      GIM_Try, /*On fail goto*//*Label 1175*/ 57434, // Rule ID 2108 //
22563        GIM_CheckFeatures, GIFBS_HasVFP4,
22564        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22565        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22566        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22567        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22568        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22569        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
22570        GIM_CheckIsSafeToFold, /*InsnID*/1,
22571        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm), SPR:{ *:[f32] }:$Sdin)  =>  (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
22572        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSS,
22573        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22574        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
22575        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
22576        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
22577        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22578        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22579        GIR_EraseFromParent, /*InsnID*/0,
22580        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22581        // GIR_Coverage, 2108,
22582        GIR_Done,
22583      // Label 1175: @57434
22584      GIM_Try, /*On fail goto*//*Label 1176*/ 57493, // Rule ID 2118 //
22585        GIM_CheckFeatures, GIFBS_HasVFP4,
22586        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22587        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
22588        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
22589        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22590        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22591        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22592        GIM_CheckIsSafeToFold, /*InsnID*/1,
22593        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
22594        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
22595        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22596        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
22597        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
22598        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22599        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22600        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22601        GIR_EraseFromParent, /*InsnID*/0,
22602        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22603        // GIR_Coverage, 2118,
22604        GIR_Done,
22605      // Label 1176: @57493
22606      GIM_Try, /*On fail goto*//*Label 1177*/ 57539, // Rule ID 2101 //
22607        GIM_CheckFeatures, GIFBS_HasVFP4,
22608        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22609        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
22610        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::SPRRegClassID,
22611        // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)  =>  (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
22612        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAS,
22613        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22614        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Sdin
22615        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
22616        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22617        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22618        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22619        GIR_EraseFromParent, /*InsnID*/0,
22620        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22621        // GIR_Coverage, 2101,
22622        GIR_Done,
22623      // Label 1177: @57539
22624      GIM_Reject,
22625    // Label 1172: @57540
22626    GIM_Reject,
22627    // Label 1168: @57541
22628    GIM_Try, /*On fail goto*//*Label 1178*/ 57855,
22629      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22630      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22631      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
22632      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22633      GIM_Try, /*On fail goto*//*Label 1179*/ 57631, // Rule ID 2113 //
22634        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
22635        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22636        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22637        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22638        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22639        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22640        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
22641        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
22642        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
22643        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22644        GIM_CheckIsSafeToFold, /*InsnID*/1,
22645        GIM_CheckIsSafeToFold, /*InsnID*/2,
22646        // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
22647        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
22648        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22649        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
22650        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
22651        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
22652        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22653        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22654        GIR_EraseFromParent, /*InsnID*/0,
22655        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22656        // GIR_Coverage, 2113,
22657        GIR_Done,
22658      // Label 1179: @57631
22659      GIM_Try, /*On fail goto*//*Label 1180*/ 57690, // Rule ID 2105 //
22660        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
22661        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22662        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22663        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22664        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22665        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22666        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22667        GIM_CheckIsSafeToFold, /*InsnID*/1,
22668        // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)  =>  (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
22669        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
22670        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22671        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
22672        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
22673        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
22674        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22675        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22676        GIR_EraseFromParent, /*InsnID*/0,
22677        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22678        // GIR_Coverage, 2105,
22679        GIR_Done,
22680      // Label 1180: @57690
22681      GIM_Try, /*On fail goto*//*Label 1181*/ 57749, // Rule ID 2107 //
22682        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
22683        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22684        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22685        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22686        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22687        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22688        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22689        GIM_CheckIsSafeToFold, /*InsnID*/1,
22690        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm), DPR:{ *:[f64] }:$Ddin)  =>  (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
22691        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSD,
22692        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22693        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
22694        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
22695        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
22696        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22697        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22698        GIR_EraseFromParent, /*InsnID*/0,
22699        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22700        // GIR_Coverage, 2107,
22701        GIR_Done,
22702      // Label 1181: @57749
22703      GIM_Try, /*On fail goto*//*Label 1182*/ 57808, // Rule ID 2117 //
22704        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
22705        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22706        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22707        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
22708        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22709        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22710        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22711        GIM_CheckIsSafeToFold, /*InsnID*/1,
22712        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
22713        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
22714        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22715        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
22716        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
22717        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
22718        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22719        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22720        GIR_EraseFromParent, /*InsnID*/0,
22721        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22722        // GIR_Coverage, 2117,
22723        GIR_Done,
22724      // Label 1182: @57808
22725      GIM_Try, /*On fail goto*//*Label 1183*/ 57854, // Rule ID 2100 //
22726        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
22727        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22728        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22729        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22730        // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)  =>  (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
22731        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAD,
22732        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22733        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // Ddin
22734        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
22735        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
22736        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22737        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22738        GIR_EraseFromParent, /*InsnID*/0,
22739        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22740        // GIR_Coverage, 2100,
22741        GIR_Done,
22742      // Label 1183: @57854
22743      GIM_Reject,
22744    // Label 1178: @57855
22745    GIM_Reject,
22746    // Label 1169: @57856
22747    GIM_Try, /*On fail goto*//*Label 1184*/ 57980,
22748      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
22749      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
22750      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
22751      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22752      GIM_Try, /*On fail goto*//*Label 1185*/ 57933, // Rule ID 2193 //
22753        GIM_CheckFeatures, GIFBS_HasVFP4,
22754        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22755        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22756        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
22757        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22758        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22759        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22760        GIM_CheckIsSafeToFold, /*InsnID*/1,
22761        // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1)  =>  (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
22762        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfd,
22763        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22764        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
22765        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
22766        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22767        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22768        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22769        GIR_EraseFromParent, /*InsnID*/0,
22770        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22771        // GIR_Coverage, 2193,
22772        GIR_Done,
22773      // Label 1185: @57933
22774      GIM_Try, /*On fail goto*//*Label 1186*/ 57979, // Rule ID 2191 //
22775        GIM_CheckFeatures, GIFBS_HasVFP4,
22776        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22777        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22778        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::DPRRegClassID,
22779        // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1)  =>  (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
22780        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfd,
22781        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22782        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
22783        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22784        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22785        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22786        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22787        GIR_EraseFromParent, /*InsnID*/0,
22788        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22789        // GIR_Coverage, 2191,
22790        GIR_Done,
22791      // Label 1186: @57979
22792      GIM_Reject,
22793    // Label 1184: @57980
22794    GIM_Reject,
22795    // Label 1170: @57981
22796    GIM_Try, /*On fail goto*//*Label 1187*/ 58105,
22797      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
22798      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
22799      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
22800      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
22801      GIM_Try, /*On fail goto*//*Label 1188*/ 58058, // Rule ID 2194 //
22802        GIM_CheckFeatures, GIFBS_HasVFP4,
22803        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22804        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
22805        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22806        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::QPRRegClassID,
22807        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22808        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22809        GIM_CheckIsSafeToFold, /*InsnID*/1,
22810        // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1)  =>  (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
22811        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMSfq,
22812        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22813        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
22814        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
22815        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22816        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22817        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22818        GIR_EraseFromParent, /*InsnID*/0,
22819        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22820        // GIR_Coverage, 2194,
22821        GIR_Done,
22822      // Label 1188: @58058
22823      GIM_Try, /*On fail goto*//*Label 1189*/ 58104, // Rule ID 2192 //
22824        GIM_CheckFeatures, GIFBS_HasVFP4,
22825        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
22826        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
22827        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/ARM::QPRRegClassID,
22828        // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1)  =>  (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
22829        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFMAfq,
22830        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
22831        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
22832        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
22833        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
22834        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22835        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22836        GIR_EraseFromParent, /*InsnID*/0,
22837        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22838        // GIR_Coverage, 2192,
22839        GIR_Done,
22840      // Label 1189: @58104
22841      GIM_Reject,
22842    // Label 1187: @58105
22843    GIM_Reject,
22844    // Label 1171: @58106
22845    GIM_Reject,
22846    // Label 23: @58107
22847    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 1193*/ 58269,
22848    /*GILLT_s16*//*Label 1190*/ 58116,
22849    /*GILLT_s32*//*Label 1191*/ 58167,
22850    /*GILLT_s64*//*Label 1192*/ 58218,
22851    // Label 1190: @58116
22852    GIM_Try, /*On fail goto*//*Label 1194*/ 58166, // Rule ID 626 //
22853      GIM_CheckFeatures, GIFBS_HasFullFP16,
22854      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
22855      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
22856      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
22857      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
22858      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::HPRRegClassID,
22859      // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)  =>  (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
22860      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVH,
22861      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22862      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
22863      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22864      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22865      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22866      GIR_EraseFromParent, /*InsnID*/0,
22867      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22868      // GIR_Coverage, 626,
22869      GIR_Done,
22870    // Label 1194: @58166
22871    GIM_Reject,
22872    // Label 1191: @58167
22873    GIM_Try, /*On fail goto*//*Label 1195*/ 58217, // Rule ID 625 //
22874      GIM_CheckFeatures, GIFBS_HasVFP2,
22875      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22876      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
22877      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
22878      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22879      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::SPRRegClassID,
22880      // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)  =>  (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
22881      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVS,
22882      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22883      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sn
22884      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Sm
22885      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22886      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22887      GIR_EraseFromParent, /*InsnID*/0,
22888      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22889      // GIR_Coverage, 625,
22890      GIR_Done,
22891    // Label 1195: @58217
22892    GIM_Reject,
22893    // Label 1192: @58218
22894    GIM_Try, /*On fail goto*//*Label 1196*/ 58268, // Rule ID 624 //
22895      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
22896      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
22897      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
22898      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
22899      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
22900      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
22901      // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)  =>  (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
22902      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VDIVD,
22903      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
22904      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dn
22905      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Dm
22906      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22907      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22908      GIR_EraseFromParent, /*InsnID*/0,
22909      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22910      // GIR_Coverage, 624,
22911      GIR_Done,
22912    // Label 1196: @58268
22913    GIM_Reject,
22914    // Label 1193: @58269
22915    GIM_Reject,
22916    // Label 24: @58270
22917    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 9, /*)*//*default:*//*Label 1204*/ 59186,
22918    /*GILLT_s16*//*Label 1197*/ 58285,
22919    /*GILLT_s32*//*Label 1198*/ 58382,
22920    /*GILLT_s64*//*Label 1199*/ 58706,
22921    /*GILLT_v2s32*//*Label 1200*/ 59030, 0,
22922    /*GILLT_v4s16*//*Label 1201*/ 59069,
22923    /*GILLT_v4s32*//*Label 1202*/ 59108, 0,
22924    /*GILLT_v8s16*//*Label 1203*/ 59147,
22925    // Label 1197: @58285
22926    GIM_Try, /*On fail goto*//*Label 1205*/ 58381,
22927      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
22928      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
22929      GIM_Try, /*On fail goto*//*Label 1206*/ 58350, // Rule ID 632 //
22930        GIM_CheckFeatures, GIFBS_HasFullFP16,
22931        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22932        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
22933        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
22934        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
22935        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::HPRRegClassID,
22936        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::HPRRegClassID,
22937        GIM_CheckIsSafeToFold, /*InsnID*/1,
22938        // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm))  =>  (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
22939        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULH,
22940        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22941        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
22942        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
22943        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22944        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22945        GIR_EraseFromParent, /*InsnID*/0,
22946        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22947        // GIR_Coverage, 632,
22948        GIR_Done,
22949      // Label 1206: @58350
22950      GIM_Try, /*On fail goto*//*Label 1207*/ 58380, // Rule ID 669 //
22951        GIM_CheckFeatures, GIFBS_HasFullFP16,
22952        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
22953        // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm)  =>  (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
22954        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGH,
22955        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22956        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
22957        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22958        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22959        GIR_EraseFromParent, /*InsnID*/0,
22960        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22961        // GIR_Coverage, 669,
22962        GIR_Done,
22963      // Label 1207: @58380
22964      GIM_Reject,
22965    // Label 1205: @58381
22966    GIM_Reject,
22967    // Label 1198: @58382
22968    GIM_Try, /*On fail goto*//*Label 1208*/ 58705,
22969      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
22970      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
22971      GIM_Try, /*On fail goto*//*Label 1209*/ 58472, // Rule ID 2120 //
22972        GIM_CheckFeatures, GIFBS_HasVFP4,
22973        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22974        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
22975        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22976        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22977        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22978        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
22979        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
22980        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
22981        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
22982        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
22983        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
22984        GIM_CheckIsSafeToFold, /*InsnID*/1,
22985        GIM_CheckIsSafeToFold, /*InsnID*/2,
22986        // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
22987        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
22988        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
22989        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
22990        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
22991        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
22992        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
22993        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
22994        GIR_EraseFromParent, /*InsnID*/0,
22995        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
22996        // GIR_Coverage, 2120,
22997        GIR_Done,
22998      // Label 1209: @58472
22999      GIM_Try, /*On fail goto*//*Label 1210*/ 58552, // Rule ID 2122 //
23000        GIM_CheckFeatures, GIFBS_HasVFP4,
23001        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23002        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
23003        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23004        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23005        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23006        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
23007        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
23008        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
23009        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
23010        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::SPRRegClassID,
23011        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
23012        GIM_CheckIsSafeToFold, /*InsnID*/1,
23013        GIM_CheckIsSafeToFold, /*InsnID*/2,
23014        // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm), SPR:{ *:[f32] }:$Sdin))  =>  (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
23015        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSS,
23016        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23017        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
23018        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
23019        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sm
23020        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23021        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23022        GIR_EraseFromParent, /*InsnID*/0,
23023        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23024        // GIR_Coverage, 2122,
23025        GIR_Done,
23026      // Label 1210: @58552
23027      GIM_Try, /*On fail goto*//*Label 1211*/ 58619, // Rule ID 2112 //
23028        GIM_CheckFeatures, GIFBS_HasVFP4,
23029        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23030        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
23031        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23032        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23033        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23034        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
23035        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
23036        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::SPRRegClassID,
23037        GIM_CheckIsSafeToFold, /*InsnID*/1,
23038        // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin))  =>  (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
23039        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAS,
23040        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23041        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
23042        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
23043        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
23044        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23045        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23046        GIR_EraseFromParent, /*InsnID*/0,
23047        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23048        // GIR_Coverage, 2112,
23049        GIR_Done,
23050      // Label 1211: @58619
23051      GIM_Try, /*On fail goto*//*Label 1212*/ 58674, // Rule ID 631 //
23052        GIM_CheckFeatures, GIFBS_HasVFP2,
23053        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23054        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
23055        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23056        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23057        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::SPRRegClassID,
23058        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::SPRRegClassID,
23059        GIM_CheckIsSafeToFold, /*InsnID*/1,
23060        // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm))  =>  (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
23061        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULS,
23062        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23063        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
23064        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
23065        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23066        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23067        GIR_EraseFromParent, /*InsnID*/0,
23068        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23069        // GIR_Coverage, 631,
23070        GIR_Done,
23071      // Label 1212: @58674
23072      GIM_Try, /*On fail goto*//*Label 1213*/ 58704, // Rule ID 668 //
23073        GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
23074        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
23075        // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm)  =>  (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
23076        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGS,
23077        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23078        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
23079        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23080        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23081        GIR_EraseFromParent, /*InsnID*/0,
23082        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23083        // GIR_Coverage, 668,
23084        GIR_Done,
23085      // Label 1213: @58704
23086      GIM_Reject,
23087    // Label 1208: @58705
23088    GIM_Reject,
23089    // Label 1199: @58706
23090    GIM_Try, /*On fail goto*//*Label 1214*/ 59029,
23091      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23092      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23093      GIM_Try, /*On fail goto*//*Label 1215*/ 58796, // Rule ID 2119 //
23094        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
23095        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23096        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
23097        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23098        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23099        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23100        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23101        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
23102        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23103        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23104        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23105        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23106        GIM_CheckIsSafeToFold, /*InsnID*/1,
23107        GIM_CheckIsSafeToFold, /*InsnID*/2,
23108        // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
23109        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
23110        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
23111        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
23112        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
23113        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
23114        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23115        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23116        GIR_EraseFromParent, /*InsnID*/0,
23117        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23118        // GIR_Coverage, 2119,
23119        GIR_Done,
23120      // Label 1215: @58796
23121      GIM_Try, /*On fail goto*//*Label 1216*/ 58876, // Rule ID 2121 //
23122        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
23123        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23124        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
23125        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23126        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23127        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23128        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23129        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
23130        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
23131        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23132        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23133        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23134        GIM_CheckIsSafeToFold, /*InsnID*/1,
23135        GIM_CheckIsSafeToFold, /*InsnID*/2,
23136        // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm), DPR:{ *:[f64] }:$Ddin))  =>  (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
23137        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMSD,
23138        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
23139        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
23140        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
23141        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dm
23142        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23143        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23144        GIR_EraseFromParent, /*InsnID*/0,
23145        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23146        // GIR_Coverage, 2121,
23147        GIR_Done,
23148      // Label 1216: @58876
23149      GIM_Try, /*On fail goto*//*Label 1217*/ 58943, // Rule ID 2111 //
23150        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP4,
23151        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23152        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMA,
23153        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23154        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23155        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23156        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23157        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23158        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
23159        GIM_CheckIsSafeToFold, /*InsnID*/1,
23160        // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin))  =>  (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
23161        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VFNMAD,
23162        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
23163        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
23164        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
23165        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
23166        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23167        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23168        GIR_EraseFromParent, /*InsnID*/0,
23169        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23170        // GIR_Coverage, 2111,
23171        GIR_Done,
23172      // Label 1217: @58943
23173      GIM_Try, /*On fail goto*//*Label 1218*/ 58998, // Rule ID 630 //
23174        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
23175        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23176        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
23177        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23178        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23179        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23180        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
23181        GIM_CheckIsSafeToFold, /*InsnID*/1,
23182        // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm))  =>  (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
23183        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNMULD,
23184        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
23185        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
23186        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
23187        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23188        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23189        GIR_EraseFromParent, /*InsnID*/0,
23190        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23191        // GIR_Coverage, 630,
23192        GIR_Done,
23193      // Label 1218: @58998
23194      GIM_Try, /*On fail goto*//*Label 1219*/ 59028, // Rule ID 667 //
23195        GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
23196        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23197        // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm)  =>  (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
23198        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGD,
23199        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
23200        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
23201        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23202        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23203        GIR_EraseFromParent, /*InsnID*/0,
23204        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23205        // GIR_Coverage, 667,
23206        GIR_Done,
23207      // Label 1219: @59028
23208      GIM_Reject,
23209    // Label 1214: @59029
23210    GIM_Reject,
23211    // Label 1200: @59030
23212    GIM_Try, /*On fail goto*//*Label 1220*/ 59068, // Rule ID 1501 //
23213      GIM_CheckFeatures, GIFBS_HasNEON,
23214      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
23215      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23216      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23217      // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
23218      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGfd,
23219      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23220      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23221      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23222      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23223      GIR_EraseFromParent, /*InsnID*/0,
23224      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23225      // GIR_Coverage, 1501,
23226      GIR_Done,
23227    // Label 1220: @59068
23228    GIM_Reject,
23229    // Label 1201: @59069
23230    GIM_Try, /*On fail goto*//*Label 1221*/ 59107, // Rule ID 1503 //
23231      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
23232      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
23233      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23234      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23235      // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
23236      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhd,
23237      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23238      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23239      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23240      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23241      GIR_EraseFromParent, /*InsnID*/0,
23242      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23243      // GIR_Coverage, 1503,
23244      GIR_Done,
23245    // Label 1221: @59107
23246    GIM_Reject,
23247    // Label 1202: @59108
23248    GIM_Try, /*On fail goto*//*Label 1222*/ 59146, // Rule ID 1502 //
23249      GIM_CheckFeatures, GIFBS_HasNEON,
23250      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23251      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23252      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
23253      // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
23254      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGf32q,
23255      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23256      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23257      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23258      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23259      GIR_EraseFromParent, /*InsnID*/0,
23260      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23261      // GIR_Coverage, 1502,
23262      GIR_Done,
23263    // Label 1222: @59146
23264    GIM_Reject,
23265    // Label 1203: @59147
23266    GIM_Try, /*On fail goto*//*Label 1223*/ 59185, // Rule ID 1504 //
23267      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
23268      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23269      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23270      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
23271      // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
23272      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VNEGhq,
23273      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23274      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23275      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23276      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23277      GIR_EraseFromParent, /*InsnID*/0,
23278      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23279      // GIR_Coverage, 1504,
23280      GIR_Done,
23281    // Label 1223: @59185
23282    GIM_Reject,
23283    // Label 1204: @59186
23284    GIM_Reject,
23285    // Label 25: @59187
23286    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1226*/ 59343,
23287    /*GILLT_s32*//*Label 1224*/ 59195,
23288    /*GILLT_s64*//*Label 1225*/ 59250,
23289    // Label 1224: @59195
23290    GIM_Try, /*On fail goto*//*Label 1227*/ 59249, // Rule ID 2031 //
23291      GIM_CheckFeatures, GIFBS_HasFullFP16,
23292      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
23293      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23294      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
23295      // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm)  =>  (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
23296      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23297      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
23298      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23299      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
23300      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23301      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHS,
23302      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23303      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23304      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23305      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23306      GIR_EraseFromParent, /*InsnID*/0,
23307      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23308      // GIR_Coverage, 2031,
23309      GIR_Done,
23310    // Label 1227: @59249
23311    GIM_Reject,
23312    // Label 1225: @59250
23313    GIM_Try, /*On fail goto*//*Label 1228*/ 59288, // Rule ID 665 //
23314      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
23315      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23316      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23317      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
23318      // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm)  =>  (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm)
23319      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTDS,
23320      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
23321      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Sm
23322      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23323      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23324      GIR_EraseFromParent, /*InsnID*/0,
23325      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23326      // GIR_Coverage, 665,
23327      GIR_Done,
23328    // Label 1228: @59288
23329    GIM_Try, /*On fail goto*//*Label 1229*/ 59342, // Rule ID 2035 //
23330      GIM_CheckFeatures, GIFBS_HasFullFP16,
23331      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
23332      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23333      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
23334      // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm)  =>  (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
23335      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23336      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
23337      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23338      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
23339      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23340      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTBHD,
23341      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
23342      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23343      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23344      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23345      GIR_EraseFromParent, /*InsnID*/0,
23346      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23347      // GIR_Coverage, 2035,
23348      GIR_Done,
23349    // Label 1229: @59342
23350    GIM_Reject,
23351    // Label 1226: @59343
23352    GIM_Reject,
23353    // Label 26: @59344
23354    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1232*/ 59504,
23355    /*GILLT_s16*//*Label 1230*/ 59352,
23356    /*GILLT_s32*//*Label 1231*/ 59465,
23357    // Label 1230: @59352
23358    GIM_Try, /*On fail goto*//*Label 1233*/ 59408, // Rule ID 2033 //
23359      GIM_CheckFeatures, GIFBS_HasFullFP16,
23360      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23361      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23362      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
23363      // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] })
23364      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23365      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBSH,
23366      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23367      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
23368      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
23369      GIR_AddRegister, /*InsnID*/1, ::zero_reg,
23370      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23371      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23372      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23373      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23374      GIR_EraseFromParent, /*InsnID*/0,
23375      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC HPR*/0,
23376      // GIR_Coverage, 2033,
23377      GIR_Done,
23378    // Label 1233: @59408
23379    GIM_Try, /*On fail goto*//*Label 1234*/ 59464, // Rule ID 2037 //
23380      GIM_CheckFeatures, GIFBS_HasFullFP16,
23381      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23382      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23383      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23384      // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm)  =>  (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] })
23385      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23386      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VCVTBDH,
23387      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23388      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm
23389      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
23390      GIR_AddRegister, /*InsnID*/1, ::zero_reg,
23391      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23392      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23393      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23394      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23395      GIR_EraseFromParent, /*InsnID*/0,
23396      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC HPR*/0,
23397      // GIR_Coverage, 2037,
23398      GIR_Done,
23399    // Label 1234: @59464
23400    GIM_Reject,
23401    // Label 1231: @59465
23402    GIM_Try, /*On fail goto*//*Label 1235*/ 59503, // Rule ID 666 //
23403      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
23404      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23405      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23406      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23407      // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm)  =>  (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
23408      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTSD,
23409      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23410      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Dm
23411      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23412      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23413      GIR_EraseFromParent, /*InsnID*/0,
23414      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23415      // GIR_Coverage, 666,
23416      GIR_Done,
23417    // Label 1235: @59503
23418    GIM_Reject,
23419    // Label 1232: @59504
23420    GIM_Reject,
23421    // Label 27: @59505
23422    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1241*/ 59844,
23423    /*GILLT_s32*//*Label 1236*/ 59519, 0,
23424    /*GILLT_v2s32*//*Label 1237*/ 59688, 0,
23425    /*GILLT_v4s16*//*Label 1238*/ 59727,
23426    /*GILLT_v4s32*//*Label 1239*/ 59766, 0,
23427    /*GILLT_v8s16*//*Label 1240*/ 59805,
23428    // Label 1236: @59519
23429    GIM_Try, /*On fail goto*//*Label 1242*/ 59575, // Rule ID 2072 //
23430      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
23431      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23432      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23433      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23434      // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
23435      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23436      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZD,
23437      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23438      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23439      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
23440      GIR_AddRegister, /*InsnID*/1, ::zero_reg,
23441      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23442      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23443      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23444      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23445      GIR_EraseFromParent, /*InsnID*/0,
23446      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/2,
23447      // GIR_Coverage, 2072,
23448      GIR_Done,
23449    // Label 1242: @59575
23450    GIM_Try, /*On fail goto*//*Label 1243*/ 59631, // Rule ID 2074 //
23451      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
23452      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23453      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23454      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
23455      // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
23456      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23457      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZS,
23458      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23459      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23460      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
23461      GIR_AddRegister, /*InsnID*/1, ::zero_reg,
23462      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23463      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23464      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23465      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23466      GIR_EraseFromParent, /*InsnID*/0,
23467      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/2,
23468      // GIR_Coverage, 2074,
23469      GIR_Done,
23470    // Label 1243: @59631
23471    GIM_Try, /*On fail goto*//*Label 1244*/ 59687, // Rule ID 2076 //
23472      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
23473      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
23474      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23475      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
23476      // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
23477      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23478      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOSIZH,
23479      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23480      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23481      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
23482      GIR_AddRegister, /*InsnID*/1, ::zero_reg,
23483      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23484      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23485      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23486      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23487      GIR_EraseFromParent, /*InsnID*/0,
23488      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/2,
23489      // GIR_Coverage, 2076,
23490      GIR_Done,
23491    // Label 1244: @59687
23492    GIM_Reject,
23493    // Label 1237: @59688
23494    GIM_Try, /*On fail goto*//*Label 1245*/ 59726, // Rule ID 1575 //
23495      GIM_CheckFeatures, GIFBS_HasNEON,
23496      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
23497      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23498      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23499      // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
23500      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sd,
23501      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23502      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23503      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23504      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23505      GIR_EraseFromParent, /*InsnID*/0,
23506      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23507      // GIR_Coverage, 1575,
23508      GIR_Done,
23509    // Label 1245: @59726
23510    GIM_Reject,
23511    // Label 1238: @59727
23512    GIM_Try, /*On fail goto*//*Label 1246*/ 59765, // Rule ID 1583 //
23513      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
23514      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
23515      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23516      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23517      // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
23518      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sd,
23519      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23520      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23521      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23522      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23523      GIR_EraseFromParent, /*InsnID*/0,
23524      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23525      // GIR_Coverage, 1583,
23526      GIR_Done,
23527    // Label 1246: @59765
23528    GIM_Reject,
23529    // Label 1239: @59766
23530    GIM_Try, /*On fail goto*//*Label 1247*/ 59804, // Rule ID 1579 //
23531      GIM_CheckFeatures, GIFBS_HasNEON,
23532      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23533      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23534      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
23535      // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
23536      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2sq,
23537      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23538      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23539      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23540      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23541      GIR_EraseFromParent, /*InsnID*/0,
23542      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23543      // GIR_Coverage, 1579,
23544      GIR_Done,
23545    // Label 1247: @59804
23546    GIM_Reject,
23547    // Label 1240: @59805
23548    GIM_Try, /*On fail goto*//*Label 1248*/ 59843, // Rule ID 1587 //
23549      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
23550      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23551      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23552      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
23553      // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
23554      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2sq,
23555      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23556      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23557      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23558      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23559      GIR_EraseFromParent, /*InsnID*/0,
23560      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23561      // GIR_Coverage, 1587,
23562      GIR_Done,
23563    // Label 1248: @59843
23564    GIM_Reject,
23565    // Label 1241: @59844
23566    GIM_Reject,
23567    // Label 28: @59845
23568    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1254*/ 60184,
23569    /*GILLT_s32*//*Label 1249*/ 59859, 0,
23570    /*GILLT_v2s32*//*Label 1250*/ 60028, 0,
23571    /*GILLT_v4s16*//*Label 1251*/ 60067,
23572    /*GILLT_v4s32*//*Label 1252*/ 60106, 0,
23573    /*GILLT_v8s16*//*Label 1253*/ 60145,
23574    // Label 1249: @59859
23575    GIM_Try, /*On fail goto*//*Label 1255*/ 59915, // Rule ID 2077 //
23576      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
23577      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
23578      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23579      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23580      // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
23581      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23582      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZD,
23583      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23584      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23585      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
23586      GIR_AddRegister, /*InsnID*/1, ::zero_reg,
23587      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23588      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23589      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23590      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23591      GIR_EraseFromParent, /*InsnID*/0,
23592      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/2,
23593      // GIR_Coverage, 2077,
23594      GIR_Done,
23595    // Label 1255: @59915
23596    GIM_Try, /*On fail goto*//*Label 1256*/ 59971, // Rule ID 2079 //
23597      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
23598      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23599      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23600      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::SPRRegClassID,
23601      // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
23602      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23603      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZS,
23604      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23605      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23606      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
23607      GIR_AddRegister, /*InsnID*/1, ::zero_reg,
23608      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23609      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23610      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23611      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23612      GIR_EraseFromParent, /*InsnID*/0,
23613      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/2,
23614      // GIR_Coverage, 2079,
23615      GIR_Done,
23616    // Label 1256: @59971
23617    GIM_Try, /*On fail goto*//*Label 1257*/ 60027, // Rule ID 2081 //
23618      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
23619      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
23620      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
23621      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::HPRRegClassID,
23622      // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a)  =>  (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
23623      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23624      GIR_BuildMI, /*InsnID*/1, /*Opcode*/ARM::VTOUIZH,
23625      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23626      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23627      GIR_AddImm, /*InsnID*/1, /*Imm*/14,
23628      GIR_AddRegister, /*InsnID*/1, ::zero_reg,
23629      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23630      GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
23631      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
23632      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23633      GIR_EraseFromParent, /*InsnID*/0,
23634      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR*/2,
23635      // GIR_Coverage, 2081,
23636      GIR_Done,
23637    // Label 1257: @60027
23638    GIM_Reject,
23639    // Label 1250: @60028
23640    GIM_Try, /*On fail goto*//*Label 1258*/ 60066, // Rule ID 1576 //
23641      GIM_CheckFeatures, GIFBS_HasNEON,
23642      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
23643      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23644      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23645      // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)  =>  (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
23646      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2ud,
23647      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23648      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23649      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23650      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23651      GIR_EraseFromParent, /*InsnID*/0,
23652      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23653      // GIR_Coverage, 1576,
23654      GIR_Done,
23655    // Label 1258: @60066
23656    GIM_Reject,
23657    // Label 1251: @60067
23658    GIM_Try, /*On fail goto*//*Label 1259*/ 60105, // Rule ID 1584 //
23659      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
23660      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
23661      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23662      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23663      // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)  =>  (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
23664      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2ud,
23665      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23666      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23667      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23668      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23669      GIR_EraseFromParent, /*InsnID*/0,
23670      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23671      // GIR_Coverage, 1584,
23672      GIR_Done,
23673    // Label 1259: @60105
23674    GIM_Reject,
23675    // Label 1252: @60106
23676    GIM_Try, /*On fail goto*//*Label 1260*/ 60144, // Rule ID 1580 //
23677      GIM_CheckFeatures, GIFBS_HasNEON,
23678      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23679      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23680      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
23681      // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)  =>  (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
23682      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTf2uq,
23683      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23684      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23685      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23686      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23687      GIR_EraseFromParent, /*InsnID*/0,
23688      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23689      // GIR_Coverage, 1580,
23690      GIR_Done,
23691    // Label 1260: @60144
23692    GIM_Reject,
23693    // Label 1253: @60145
23694    GIM_Try, /*On fail goto*//*Label 1261*/ 60183, // Rule ID 1588 //
23695      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
23696      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23697      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23698      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
23699      // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)  =>  (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
23700      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTh2uq,
23701      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23702      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23703      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23704      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23705      GIR_EraseFromParent, /*InsnID*/0,
23706      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23707      // GIR_Coverage, 1588,
23708      GIR_Done,
23709    // Label 1261: @60183
23710    GIM_Reject,
23711    // Label 1254: @60184
23712    GIM_Reject,
23713    // Label 29: @60185
23714    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 9, /*)*//*default:*//*Label 1269*/ 60521,
23715    /*GILLT_s16*//*Label 1262*/ 60200,
23716    /*GILLT_s32*//*Label 1263*/ 60255,
23717    /*GILLT_s64*//*Label 1264*/ 60310,
23718    /*GILLT_v2s32*//*Label 1265*/ 60365, 0,
23719    /*GILLT_v4s16*//*Label 1266*/ 60404,
23720    /*GILLT_v4s32*//*Label 1267*/ 60443, 0,
23721    /*GILLT_v8s16*//*Label 1268*/ 60482,
23722    // Label 1262: @60200
23723    GIM_Try, /*On fail goto*//*Label 1270*/ 60254, // Rule ID 2066 //
23724      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
23725      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23726      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23727      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
23728      // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a)  =>  (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
23729      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23730      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
23731      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23732      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23733      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23734      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOH,
23735      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23736      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23737      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23738      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23739      GIR_EraseFromParent, /*InsnID*/0,
23740      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23741      // GIR_Coverage, 2066,
23742      GIR_Done,
23743    // Label 1270: @60254
23744    GIM_Reject,
23745    // Label 1263: @60255
23746    GIM_Try, /*On fail goto*//*Label 1271*/ 60309, // Rule ID 2064 //
23747      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
23748      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23749      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23750      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
23751      // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
23752      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23753      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
23754      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23755      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23756      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23757      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOS,
23758      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23759      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23760      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23761      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23762      GIR_EraseFromParent, /*InsnID*/0,
23763      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23764      // GIR_Coverage, 2064,
23765      GIR_Done,
23766    // Label 1271: @60309
23767    GIM_Reject,
23768    // Label 1264: @60310
23769    GIM_Try, /*On fail goto*//*Label 1272*/ 60364, // Rule ID 2062 //
23770      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
23771      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23772      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23773      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
23774      // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a)  =>  (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
23775      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23776      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
23777      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23778      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23779      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23780      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VSITOD,
23781      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
23782      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23783      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23784      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23785      GIR_EraseFromParent, /*InsnID*/0,
23786      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23787      // GIR_Coverage, 2062,
23788      GIR_Done,
23789    // Label 1272: @60364
23790    GIM_Reject,
23791    // Label 1265: @60365
23792    GIM_Try, /*On fail goto*//*Label 1273*/ 60403, // Rule ID 1577 //
23793      GIM_CheckFeatures, GIFBS_HasNEON,
23794      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
23795      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23796      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23797      // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
23798      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fd,
23799      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23800      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23801      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23802      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23803      GIR_EraseFromParent, /*InsnID*/0,
23804      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23805      // GIR_Coverage, 1577,
23806      GIR_Done,
23807    // Label 1273: @60403
23808    GIM_Reject,
23809    // Label 1266: @60404
23810    GIM_Try, /*On fail goto*//*Label 1274*/ 60442, // Rule ID 1585 //
23811      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
23812      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
23813      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23814      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23815      // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
23816      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hd,
23817      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23818      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23819      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23820      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23821      GIR_EraseFromParent, /*InsnID*/0,
23822      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23823      // GIR_Coverage, 1585,
23824      GIR_Done,
23825    // Label 1274: @60442
23826    GIM_Reject,
23827    // Label 1267: @60443
23828    GIM_Try, /*On fail goto*//*Label 1275*/ 60481, // Rule ID 1581 //
23829      GIM_CheckFeatures, GIFBS_HasNEON,
23830      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23831      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23832      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
23833      // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
23834      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2fq,
23835      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23836      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23837      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23838      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23839      GIR_EraseFromParent, /*InsnID*/0,
23840      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23841      // GIR_Coverage, 1581,
23842      GIR_Done,
23843    // Label 1275: @60481
23844    GIM_Reject,
23845    // Label 1268: @60482
23846    GIM_Try, /*On fail goto*//*Label 1276*/ 60520, // Rule ID 1589 //
23847      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
23848      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
23849      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23850      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
23851      // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
23852      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTs2hq,
23853      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23854      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23855      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23856      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23857      GIR_EraseFromParent, /*InsnID*/0,
23858      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23859      // GIR_Coverage, 1589,
23860      GIR_Done,
23861    // Label 1276: @60520
23862    GIM_Reject,
23863    // Label 1269: @60521
23864    GIM_Reject,
23865    // Label 30: @60522
23866    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 9, /*)*//*default:*//*Label 1284*/ 60858,
23867    /*GILLT_s16*//*Label 1277*/ 60537,
23868    /*GILLT_s32*//*Label 1278*/ 60592,
23869    /*GILLT_s64*//*Label 1279*/ 60647,
23870    /*GILLT_v2s32*//*Label 1280*/ 60702, 0,
23871    /*GILLT_v4s16*//*Label 1281*/ 60741,
23872    /*GILLT_v4s32*//*Label 1282*/ 60780, 0,
23873    /*GILLT_v8s16*//*Label 1283*/ 60819,
23874    // Label 1277: @60537
23875    GIM_Try, /*On fail goto*//*Label 1285*/ 60591, // Rule ID 2071 //
23876      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
23877      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23878      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::HPRRegClassID,
23879      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
23880      // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a)  =>  (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
23881      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23882      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
23883      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23884      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23885      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23886      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOH,
23887      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23888      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23889      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23890      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23891      GIR_EraseFromParent, /*InsnID*/0,
23892      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23893      // GIR_Coverage, 2071,
23894      GIR_Done,
23895    // Label 1285: @60591
23896    GIM_Reject,
23897    // Label 1278: @60592
23898    GIM_Try, /*On fail goto*//*Label 1286*/ 60646, // Rule ID 2069 //
23899      GIM_CheckFeatures, GIFBS_DontUseNEONForFP_HasVFP2,
23900      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23901      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::SPRRegClassID,
23902      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
23903      // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a)  =>  (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
23904      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23905      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
23906      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23907      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23908      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23909      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOS,
23910      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Sd
23911      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23912      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23913      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23914      GIR_EraseFromParent, /*InsnID*/0,
23915      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23916      // GIR_Coverage, 2069,
23917      GIR_Done,
23918    // Label 1286: @60646
23919    GIM_Reject,
23920    // Label 1279: @60647
23921    GIM_Try, /*On fail goto*//*Label 1287*/ 60701, // Rule ID 2067 //
23922      GIM_CheckFeatures, GIFBS_HasDPVFP_HasVFP2,
23923      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
23924      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23925      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
23926      // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a)  =>  (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
23927      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23928      GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
23929      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
23930      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
23931      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23932      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VUITOD,
23933      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Dd
23934      GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
23935      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23936      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23937      GIR_EraseFromParent, /*InsnID*/0,
23938      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23939      // GIR_Coverage, 2067,
23940      GIR_Done,
23941    // Label 1287: @60701
23942    GIM_Reject,
23943    // Label 1280: @60702
23944    GIM_Try, /*On fail goto*//*Label 1288*/ 60740, // Rule ID 1578 //
23945      GIM_CheckFeatures, GIFBS_HasNEON,
23946      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
23947      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23948      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23949      // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)  =>  (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
23950      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fd,
23951      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23952      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23953      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23954      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23955      GIR_EraseFromParent, /*InsnID*/0,
23956      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23957      // GIR_Coverage, 1578,
23958      GIR_Done,
23959    // Label 1288: @60740
23960    GIM_Reject,
23961    // Label 1281: @60741
23962    GIM_Try, /*On fail goto*//*Label 1289*/ 60779, // Rule ID 1586 //
23963      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
23964      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
23965      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
23966      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
23967      // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)  =>  (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
23968      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hd,
23969      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23970      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23971      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23972      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23973      GIR_EraseFromParent, /*InsnID*/0,
23974      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23975      // GIR_Coverage, 1586,
23976      GIR_Done,
23977    // Label 1289: @60779
23978    GIM_Reject,
23979    // Label 1282: @60780
23980    GIM_Try, /*On fail goto*//*Label 1290*/ 60818, // Rule ID 1582 //
23981      GIM_CheckFeatures, GIFBS_HasNEON,
23982      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
23983      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
23984      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
23985      // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)  =>  (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
23986      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2fq,
23987      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
23988      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
23989      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
23990      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
23991      GIR_EraseFromParent, /*InsnID*/0,
23992      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
23993      // GIR_Coverage, 1582,
23994      GIR_Done,
23995    // Label 1290: @60818
23996    GIM_Reject,
23997    // Label 1283: @60819
23998    GIM_Try, /*On fail goto*//*Label 1291*/ 60857, // Rule ID 1590 //
23999      GIM_CheckFeatures, GIFBS_HasFullFP16_HasNEON,
24000      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
24001      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
24002      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
24003      // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)  =>  (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
24004      GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VCVTu2hq,
24005      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
24006      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vm
24007      GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24008      GIR_AddRegister, /*InsnID*/0, ::zero_reg,
24009      GIR_EraseFromParent, /*InsnID*/0,
24010      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24011      // GIR_Coverage, 1590,
24012      GIR_Done,
24013    // Label 1291: @60857
24014    GIM_Reject,
24015    // Label 1284: @60858
24016    GIM_Reject,
24017    // Label 31: @60859
24018    GIM_Try, /*On fail goto*//*Label 1292*/ 60920,
24019      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
24020      GIM_Try, /*On fail goto*//*Label 1293*/ 60875, // Rule ID 34 //
24021        GIM_CheckFeatures, GIFBS_IsARM,
24022        // (br (bb:{ *:[Other] }):$target)  =>  (B (bb:{ *:[Other] }):$target)
24023        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/ARM::B,
24024        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24025        // GIR_Coverage, 34,
24026        GIR_Done,
24027      // Label 1293: @60875
24028      GIM_Try, /*On fail goto*//*Label 1294*/ 60897, // Rule ID 291 //
24029        GIM_CheckFeatures, GIFBS_IsThumb_IsThumb1Only,
24030        // (br (bb:{ *:[Other] }):$target)  =>  (tB (bb:{ *:[Other] }):$target)
24031        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tB,
24032        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
24033        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24034        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
24035        GIR_EraseFromParent, /*InsnID*/0,
24036        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24037        // GIR_Coverage, 291,
24038        GIR_Done,
24039      // Label 1294: @60897
24040      GIM_Try, /*On fail goto*//*Label 1295*/ 60919, // Rule ID 590 //
24041        GIM_CheckFeatures, GIFBS_HasV8MBaseline_IsThumb,
24042        // (br (bb:{ *:[Other] }):$target)  =>  (t2B (bb:{ *:[Other] }):$target)
24043        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2B,
24044        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // target
24045        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24046        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
24047        GIR_EraseFromParent, /*InsnID*/0,
24048        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24049        // GIR_Coverage, 590,
24050        GIR_Done,
24051      // Label 1295: @60919
24052      GIM_Reject,
24053    // Label 1292: @60920
24054    GIM_Reject,
24055    // Label 32: @60921
24056    GIM_Try, /*On fail goto*//*Label 1296*/ 61034,
24057      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
24058      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
24059      GIM_Try, /*On fail goto*//*Label 1297*/ 60965, // Rule ID 201 //
24060        GIM_CheckFeatures, GIFBS_HasV6_IsARM,
24061        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
24062        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
24063        // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm)  =>  (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
24064        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::REV,
24065        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
24066        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
24067        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24068        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
24069        GIR_EraseFromParent, /*InsnID*/0,
24070        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24071        // GIR_Coverage, 201,
24072        GIR_Done,
24073      // Label 1297: @60965
24074      GIM_Try, /*On fail goto*//*Label 1298*/ 60999, // Rule ID 334 //
24075        GIM_CheckFeatures, GIFBS_HasV6_IsThumb_IsThumb1Only,
24076        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::tGPRRegClassID,
24077        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::tGPRRegClassID,
24078        // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)  =>  (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
24079        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::tREV,
24080        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
24081        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
24082        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24083        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
24084        GIR_EraseFromParent, /*InsnID*/0,
24085        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24086        // GIR_Coverage, 334,
24087        GIR_Done,
24088      // Label 1298: @60999
24089      GIM_Try, /*On fail goto*//*Label 1299*/ 61033, // Rule ID 540 //
24090        GIM_CheckFeatures, GIFBS_IsThumb2,
24091        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
24092        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
24093        // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)  =>  (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
24094        GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2REV,
24095        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
24096        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
24097        GIR_AddImm, /*InsnID*/0, /*Imm*/14,
24098        GIR_AddRegister, /*InsnID*/0, ::zero_reg,
24099        GIR_EraseFromParent, /*InsnID*/0,
24100        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
24101        // GIR_Coverage, 540,
24102        GIR_Done,
24103      // Label 1299: @61033
24104      GIM_Reject,
24105    // Label 1296: @61034
24106    GIM_Reject,
24107    // Label 33: @61035
24108    GIM_Reject,
24109    };
24110  return MatchTable0;
24111}
24112#endif // ifdef GET_GLOBALISEL_IMPL
24113#ifdef GET_GLOBALISEL_PREDICATES_DECL
24114PredicateBitset AvailableModuleFeatures;
24115mutable PredicateBitset AvailableFunctionFeatures;
24116PredicateBitset getAvailableFeatures() const {
24117  return AvailableModuleFeatures | AvailableFunctionFeatures;
24118}
24119PredicateBitset
24120computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const;
24121PredicateBitset
24122computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget,
24123                                 const MachineFunction *MF) const;
24124#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
24125#ifdef GET_GLOBALISEL_PREDICATES_INIT
24126AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
24127AvailableFunctionFeatures()
24128#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
24129