1 //===----------------------- DispatchStage.h --------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 ///
11 /// This file models the dispatch component of an instruction pipeline.
12 ///
13 /// The DispatchStage is responsible for updating instruction dependencies
14 /// and communicating to the simulated instruction scheduler that an instruction
15 /// is ready to be scheduled for execution.
16 ///
17 //===----------------------------------------------------------------------===//
18 
19 #ifndef LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
20 #define LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
21 
22 #include "HWEventListener.h"
23 #include "Instruction.h"
24 #include "RegisterFile.h"
25 #include "RetireControlUnit.h"
26 #include "Stage.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 
30 namespace mca {
31 
32 class Scheduler;
33 
34 // Implements the hardware dispatch logic.
35 //
36 // This class is responsible for the dispatch stage, in which instructions are
37 // dispatched in groups to the Scheduler.  An instruction can be dispatched if
38 // the following conditions are met:
39 //  1) There are enough entries in the reorder buffer (see class
40 //     RetireControlUnit) to write the opcodes associated with the instruction.
41 //  2) There are enough physical registers to rename output register operands.
42 //  3) There are enough entries available in the used buffered resource(s).
43 //
44 // The number of micro opcodes that can be dispatched in one cycle is limited by
45 // the value of field 'DispatchWidth'. A "dynamic dispatch stall" occurs when
46 // processor resources are not available. Dispatch stall events are counted
47 // during the entire execution of the code, and displayed by the performance
48 // report when flag '-dispatch-stats' is specified.
49 //
50 // If the number of micro opcodes exceedes DispatchWidth, then the instruction
51 // is dispatched in multiple cycles.
52 class DispatchStage : public Stage {
53   unsigned DispatchWidth;
54   unsigned AvailableEntries;
55   unsigned CarryOver;
56   const llvm::MCSubtargetInfo &STI;
57   RetireControlUnit &RCU;
58   RegisterFile &PRF;
59   Scheduler ≻
60 
61   bool checkRCU(const InstRef &IR);
62   bool checkPRF(const InstRef &IR);
63   bool checkScheduler(const InstRef &IR);
64   void dispatch(InstRef IR);
65   void updateRAWDependencies(ReadState &RS, const llvm::MCSubtargetInfo &STI);
66 
67   void notifyInstructionDispatched(const InstRef &IR,
68                                    llvm::ArrayRef<unsigned> UsedPhysRegs);
69 
isAvailable(unsigned NumEntries)70   bool isAvailable(unsigned NumEntries) const {
71     return NumEntries <= AvailableEntries || AvailableEntries == DispatchWidth;
72   }
73 
canDispatch(const InstRef & IR)74   bool canDispatch(const InstRef &IR) {
75     assert(isAvailable(IR.getInstruction()->getDesc().NumMicroOps));
76     return checkRCU(IR) && checkPRF(IR) && checkScheduler(IR);
77   }
78 
collectWrites(llvm::SmallVectorImpl<WriteRef> & Vec,unsigned RegID)79   void collectWrites(llvm::SmallVectorImpl<WriteRef> &Vec,
80                      unsigned RegID) const {
81     return PRF.collectWrites(Vec, RegID);
82   }
83 
84 public:
DispatchStage(const llvm::MCSubtargetInfo & Subtarget,const llvm::MCRegisterInfo & MRI,unsigned RegisterFileSize,unsigned MaxDispatchWidth,RetireControlUnit & R,RegisterFile & F,Scheduler & Sched)85   DispatchStage(const llvm::MCSubtargetInfo &Subtarget,
86                 const llvm::MCRegisterInfo &MRI, unsigned RegisterFileSize,
87                 unsigned MaxDispatchWidth, RetireControlUnit &R,
88                 RegisterFile &F, Scheduler &Sched)
89       : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
90         CarryOver(0U), STI(Subtarget), RCU(R), PRF(F), SC(Sched) {}
91 
92   // We can always try to dispatch, so returning false is okay in this case.
93   // The retire stage, which controls the RCU, might have items to complete but
94   // RetireStage::hasWorkToComplete will check for that case.
hasWorkToComplete()95   virtual bool hasWorkToComplete() const override final { return false; }
96   virtual void cycleStart() override final;
97   virtual bool execute(InstRef &IR) override final;
98   void notifyDispatchStall(const InstRef &IR, unsigned EventType);
99 
100 #ifndef NDEBUG
101   void dump() const;
102 #endif
103 };
104 } // namespace mca
105 
106 #endif // LLVM_TOOLS_LLVM_MCA_DISPATCH_STAGE_H
107