1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* "Fast" Instruction Selector for the Mips target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10// FastEmit Immediate Predicate functions. 11static bool Predicate_immZExt5(int64_t Imm) { 12return Imm == (Imm & 0x1f); 13} 14static bool Predicate_immZExt6(int64_t Imm) { 15return Imm == (Imm & 0x3f); 16} 17static bool Predicate_immSExt6(int64_t Imm) { 18return isInt<6>(Imm); 19} 20static bool Predicate_immZExt4Ptr(int64_t Imm) { 21return isUInt<4>(Imm); 22} 23static bool Predicate_immZExt3Ptr(int64_t Imm) { 24return isUInt<3>(Imm); 25} 26static bool Predicate_immZExt2Ptr(int64_t Imm) { 27return isUInt<2>(Imm); 28} 29static bool Predicate_immZExt1Ptr(int64_t Imm) { 30return isUInt<1>(Imm); 31} 32static bool Predicate_immZExt4(int64_t Imm) { 33return isUInt<4>(Imm); 34} 35static bool Predicate_immZExt3(int64_t Imm) { 36return isUInt<3>(Imm); 37} 38static bool Predicate_immZExt2(int64_t Imm) { 39return isUInt<2>(Imm); 40} 41static bool Predicate_immZExt1(int64_t Imm) { 42return isUInt<1>(Imm); 43} 44static bool Predicate_immZExt8(int64_t Imm) { 45return isUInt<8>(Imm); 46} 47static bool Predicate_immSExtAddiur2(int64_t Imm) { 48return Imm == 1 || Imm == -1 || 49 ((Imm % 4 == 0) && 50 Imm < 28 && Imm > 0); 51} 52static bool Predicate_immSExtAddius5(int64_t Imm) { 53return Imm >= -8 && Imm <= 7; 54} 55static bool Predicate_immZExtAndi16(int64_t Imm) { 56return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || 57 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || 58 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 ); 59} 60static bool Predicate_immZExt2Shift(int64_t Imm) { 61return Imm >= 1 && Imm <= 8; 62} 63 64 65// FastEmit functions for ISD::BITCAST. 66 67unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 68 if (RetVT.SimpleTy != MVT::f32) 69 return 0; 70 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 71 return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill); 72 } 73 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 74 return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 75 } 76 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 77 return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill); 78 } 79 return 0; 80} 81 82unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 83 if (RetVT.SimpleTy != MVT::f64) 84 return 0; 85 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 86 return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill); 87 } 88 return 0; 89} 90 91unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 92 if (RetVT.SimpleTy != MVT::i32) 93 return 0; 94 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 95 return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 96 } 97 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 98 return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 99 } 100 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 101 return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill); 102 } 103 return 0; 104} 105 106unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 107 if (RetVT.SimpleTy != MVT::i64) 108 return 0; 109 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 110 return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill); 111 } 112 return 0; 113} 114 115unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 116 switch (VT.SimpleTy) { 117 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill); 118 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill); 119 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill); 120 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill); 121 default: return 0; 122 } 123} 124 125// FastEmit functions for ISD::BRIND. 126 127unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 128 if (RetVT.SimpleTy != MVT::isVoid) 129 return 0; 130 if ((Subtarget->inMips16Mode())) { 131 return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill); 132 } 133 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 134 return fastEmitInst_r(Mips::PseudoIndirectBranch_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 135 } 136 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 137 return fastEmitInst_r(Mips::PseudoIndirectBranch_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 138 } 139 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 140 return fastEmitInst_r(Mips::PseudoIndrectHazardBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 141 } 142 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) { 143 return fastEmitInst_r(Mips::PseudoIndirectBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 144 } 145 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) { 146 return fastEmitInst_r(Mips::PseudoIndirectHazardBranch, &Mips::GPR32RegClass, Op0, Op0IsKill); 147 } 148 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 149 return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill); 150 } 151 return 0; 152} 153 154unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 155 if (RetVT.SimpleTy != MVT::isVoid) 156 return 0; 157 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 158 return fastEmitInst_r(Mips::PseudoIndrectHazardBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill); 159 } 160 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) { 161 return fastEmitInst_r(Mips::PseudoIndirectBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill); 162 } 163 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) { 164 return fastEmitInst_r(Mips::PseudoIndirectHazardBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill); 165 } 166 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 167 return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill); 168 } 169 return 0; 170} 171 172unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 173 switch (VT.SimpleTy) { 174 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill); 175 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill); 176 default: return 0; 177 } 178} 179 180// FastEmit functions for ISD::CTLZ. 181 182unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 183 if (RetVT.SimpleTy != MVT::i32) 184 return 0; 185 if ((Subtarget->inMicroMipsMode())) { 186 return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 187 } 188 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) { 189 return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill); 190 } 191 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 192 return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill); 193 } 194 return 0; 195} 196 197unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 198 if (RetVT.SimpleTy != MVT::i64) 199 return 0; 200 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 201 return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill); 202 } 203 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) { 204 return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill); 205 } 206 return 0; 207} 208 209unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 210 if (RetVT.SimpleTy != MVT::v16i8) 211 return 0; 212 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 213 return fastEmitInst_r(Mips::NLZC_B, &Mips::MSA128BRegClass, Op0, Op0IsKill); 214 } 215 return 0; 216} 217 218unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 219 if (RetVT.SimpleTy != MVT::v8i16) 220 return 0; 221 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 222 return fastEmitInst_r(Mips::NLZC_H, &Mips::MSA128HRegClass, Op0, Op0IsKill); 223 } 224 return 0; 225} 226 227unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 228 if (RetVT.SimpleTy != MVT::v4i32) 229 return 0; 230 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 231 return fastEmitInst_r(Mips::NLZC_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 232 } 233 return 0; 234} 235 236unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 237 if (RetVT.SimpleTy != MVT::v2i64) 238 return 0; 239 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 240 return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 241 } 242 return 0; 243} 244 245unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 246 switch (VT.SimpleTy) { 247 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill); 248 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill); 249 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 250 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 251 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 252 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 253 default: return 0; 254 } 255} 256 257// FastEmit functions for ISD::CTPOP. 258 259unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 260 if (RetVT.SimpleTy != MVT::i32) 261 return 0; 262 if ((Subtarget->hasCnMips())) { 263 return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill); 264 } 265 return 0; 266} 267 268unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 269 if (RetVT.SimpleTy != MVT::i64) 270 return 0; 271 if ((Subtarget->hasCnMips())) { 272 return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill); 273 } 274 return 0; 275} 276 277unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 278 if (RetVT.SimpleTy != MVT::v16i8) 279 return 0; 280 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 281 return fastEmitInst_r(Mips::PCNT_B, &Mips::MSA128BRegClass, Op0, Op0IsKill); 282 } 283 return 0; 284} 285 286unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 287 if (RetVT.SimpleTy != MVT::v8i16) 288 return 0; 289 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 290 return fastEmitInst_r(Mips::PCNT_H, &Mips::MSA128HRegClass, Op0, Op0IsKill); 291 } 292 return 0; 293} 294 295unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 296 if (RetVT.SimpleTy != MVT::v4i32) 297 return 0; 298 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 299 return fastEmitInst_r(Mips::PCNT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 300 } 301 return 0; 302} 303 304unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 305 if (RetVT.SimpleTy != MVT::v2i64) 306 return 0; 307 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 308 return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 309 } 310 return 0; 311} 312 313unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 314 switch (VT.SimpleTy) { 315 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill); 316 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill); 317 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 318 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 319 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 320 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 321 default: return 0; 322 } 323} 324 325// FastEmit functions for ISD::FABS. 326 327unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 328 if (RetVT.SimpleTy != MVT::f32) 329 return 0; 330 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 331 return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 332 } 333 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 334 return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill); 335 } 336 return 0; 337} 338 339unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 340 if (RetVT.SimpleTy != MVT::f64) 341 return 0; 342 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 343 return fastEmitInst_r(Mips::FABS_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill); 344 } 345 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 346 return fastEmitInst_r(Mips::FABS_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill); 347 } 348 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 349 return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 350 } 351 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 352 return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill); 353 } 354 return 0; 355} 356 357unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 358 if (RetVT.SimpleTy != MVT::v4f32) 359 return 0; 360 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 361 return fastEmitInst_r(Mips::FABS_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 362 } 363 return 0; 364} 365 366unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 367 if (RetVT.SimpleTy != MVT::v2f64) 368 return 0; 369 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 370 return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 371 } 372 return 0; 373} 374 375unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 376 switch (VT.SimpleTy) { 377 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill); 378 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill); 379 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 380 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 381 default: return 0; 382 } 383} 384 385// FastEmit functions for ISD::FEXP2. 386 387unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 388 if (RetVT.SimpleTy != MVT::v4f32) 389 return 0; 390 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 391 return fastEmitInst_r(Mips::FEXP2_W_1_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill); 392 } 393 return 0; 394} 395 396unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 397 if (RetVT.SimpleTy != MVT::v2f64) 398 return 0; 399 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 400 return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill); 401 } 402 return 0; 403} 404 405unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 406 switch (VT.SimpleTy) { 407 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 408 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 409 default: return 0; 410 } 411} 412 413// FastEmit functions for ISD::FLOG2. 414 415unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 416 if (RetVT.SimpleTy != MVT::v4f32) 417 return 0; 418 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 419 return fastEmitInst_r(Mips::FLOG2_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 420 } 421 return 0; 422} 423 424unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 425 if (RetVT.SimpleTy != MVT::v2f64) 426 return 0; 427 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 428 return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 429 } 430 return 0; 431} 432 433unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 434 switch (VT.SimpleTy) { 435 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 436 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 437 default: return 0; 438 } 439} 440 441// FastEmit functions for ISD::FNEG. 442 443unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 444 if (RetVT.SimpleTy != MVT::f32) 445 return 0; 446 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 447 return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill); 448 } 449 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 450 return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 451 } 452 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) { 453 return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill); 454 } 455 return 0; 456} 457 458unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 459 if (RetVT.SimpleTy != MVT::f64) 460 return 0; 461 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 462 return fastEmitInst_r(Mips::FNEG_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill); 463 } 464 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 465 return fastEmitInst_r(Mips::FNEG_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill); 466 } 467 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 468 return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 469 } 470 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 471 return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill); 472 } 473 return 0; 474} 475 476unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 477 switch (VT.SimpleTy) { 478 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill); 479 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill); 480 default: return 0; 481 } 482} 483 484// FastEmit functions for ISD::FP_EXTEND. 485 486unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 487 if ((Subtarget->hasMSA())) { 488 return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill); 489 } 490 return 0; 491} 492 493unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 494 if ((Subtarget->hasMSA())) { 495 return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill); 496 } 497 return 0; 498} 499 500unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 501switch (RetVT.SimpleTy) { 502 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill); 503 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill); 504 default: return 0; 505} 506} 507 508unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 509 if (RetVT.SimpleTy != MVT::f64) 510 return 0; 511 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) { 512 return fastEmitInst_r(Mips::CVT_D32_S_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill); 513 } 514 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) { 515 return fastEmitInst_r(Mips::CVT_D64_S_MM, &Mips::FGR64RegClass, Op0, Op0IsKill); 516 } 517 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 518 return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill); 519 } 520 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 521 return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill); 522 } 523 return 0; 524} 525 526unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 527 switch (VT.SimpleTy) { 528 case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill); 529 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill); 530 default: return 0; 531 } 532} 533 534// FastEmit functions for ISD::FP_ROUND. 535 536unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 537 if (RetVT.SimpleTy != MVT::f16) 538 return 0; 539 if ((Subtarget->hasMSA())) { 540 return fastEmitInst_r(Mips::MSA_FP_ROUND_W_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill); 541 } 542 return 0; 543} 544 545unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) { 546 if ((Subtarget->hasMSA())) { 547 return fastEmitInst_r(Mips::MSA_FP_ROUND_D_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill); 548 } 549 return 0; 550} 551 552unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 553 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) { 554 return fastEmitInst_r(Mips::CVT_S_D32_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 555 } 556 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) { 557 return fastEmitInst_r(Mips::CVT_S_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 558 } 559 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 560 return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill); 561 } 562 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 563 return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill); 564 } 565 return 0; 566} 567 568unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 569switch (RetVT.SimpleTy) { 570 case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill); 571 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill); 572 default: return 0; 573} 574} 575 576unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 577 switch (VT.SimpleTy) { 578 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill); 579 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill); 580 default: return 0; 581 } 582} 583 584// FastEmit functions for ISD::FP_TO_SINT. 585 586unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 587 if (RetVT.SimpleTy != MVT::v4i32) 588 return 0; 589 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 590 return fastEmitInst_r(Mips::FTRUNC_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 591 } 592 return 0; 593} 594 595unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 596 if (RetVT.SimpleTy != MVT::v2i64) 597 return 0; 598 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 599 return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 600 } 601 return 0; 602} 603 604unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 605 switch (VT.SimpleTy) { 606 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 607 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 608 default: return 0; 609 } 610} 611 612// FastEmit functions for ISD::FP_TO_UINT. 613 614unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 615 if (RetVT.SimpleTy != MVT::v4i32) 616 return 0; 617 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 618 return fastEmitInst_r(Mips::FTRUNC_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 619 } 620 return 0; 621} 622 623unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 624 if (RetVT.SimpleTy != MVT::v2i64) 625 return 0; 626 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 627 return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 628 } 629 return 0; 630} 631 632unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 633 switch (VT.SimpleTy) { 634 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 635 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 636 default: return 0; 637 } 638} 639 640// FastEmit functions for ISD::FRINT. 641 642unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 643 if (RetVT.SimpleTy != MVT::v4f32) 644 return 0; 645 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 646 return fastEmitInst_r(Mips::FRINT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 647 } 648 return 0; 649} 650 651unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 652 if (RetVT.SimpleTy != MVT::v2f64) 653 return 0; 654 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 655 return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 656 } 657 return 0; 658} 659 660unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 661 switch (VT.SimpleTy) { 662 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 663 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 664 default: return 0; 665 } 666} 667 668// FastEmit functions for ISD::FSQRT. 669 670unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 671 if (RetVT.SimpleTy != MVT::f32) 672 return 0; 673 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 674 return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 675 } 676 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 677 return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill); 678 } 679 return 0; 680} 681 682unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 683 if (RetVT.SimpleTy != MVT::f64) 684 return 0; 685 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 686 return fastEmitInst_r(Mips::FSQRT_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill); 687 } 688 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 689 return fastEmitInst_r(Mips::FSQRT_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill); 690 } 691 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 692 return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 693 } 694 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 695 return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill); 696 } 697 return 0; 698} 699 700unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 701 if (RetVT.SimpleTy != MVT::v4f32) 702 return 0; 703 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 704 return fastEmitInst_r(Mips::FSQRT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 705 } 706 return 0; 707} 708 709unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 710 if (RetVT.SimpleTy != MVT::v2f64) 711 return 0; 712 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 713 return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 714 } 715 return 0; 716} 717 718unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 719 switch (VT.SimpleTy) { 720 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill); 721 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill); 722 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill); 723 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill); 724 default: return 0; 725 } 726} 727 728// FastEmit functions for ISD::SIGN_EXTEND. 729 730unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 731 if (RetVT.SimpleTy != MVT::i64) 732 return 0; 733 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) { 734 return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill); 735 } 736 return 0; 737} 738 739unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 740 switch (VT.SimpleTy) { 741 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill); 742 default: return 0; 743 } 744} 745 746// FastEmit functions for ISD::SINT_TO_FP. 747 748unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 749 return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill); 750} 751 752unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 753 if ((Subtarget->isFP64bit())) { 754 return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill); 755 } 756 if ((!Subtarget->isFP64bit())) { 757 return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill); 758 } 759 return 0; 760} 761 762unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 763switch (RetVT.SimpleTy) { 764 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill); 765 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill); 766 default: return 0; 767} 768} 769 770unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 771 if (RetVT.SimpleTy != MVT::f64) 772 return 0; 773 if ((Subtarget->isFP64bit())) { 774 return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill); 775 } 776 return 0; 777} 778 779unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 780 if (RetVT.SimpleTy != MVT::v4f32) 781 return 0; 782 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 783 return fastEmitInst_r(Mips::FFINT_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 784 } 785 return 0; 786} 787 788unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 789 if (RetVT.SimpleTy != MVT::v2f64) 790 return 0; 791 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 792 return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 793 } 794 return 0; 795} 796 797unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 798 switch (VT.SimpleTy) { 799 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill); 800 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill); 801 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 802 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 803 default: return 0; 804 } 805} 806 807// FastEmit functions for ISD::UINT_TO_FP. 808 809unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 810 if (RetVT.SimpleTy != MVT::v4f32) 811 return 0; 812 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 813 return fastEmitInst_r(Mips::FFINT_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill); 814 } 815 return 0; 816} 817 818unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 819 if (RetVT.SimpleTy != MVT::v2f64) 820 return 0; 821 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 822 return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill); 823 } 824 return 0; 825} 826 827unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 828 switch (VT.SimpleTy) { 829 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 830 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 831 default: return 0; 832 } 833} 834 835// FastEmit functions for MipsISD::JmpLink. 836 837unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 838 if (RetVT.SimpleTy != MVT::isVoid) 839 return 0; 840 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 841 return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 842 } 843 if ((Subtarget->inMips16Mode())) { 844 return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill); 845 } 846 if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 847 return fastEmitInst_r(Mips::JALRHBPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill); 848 } 849 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) { 850 return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill); 851 } 852 return 0; 853} 854 855unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 856 if (RetVT.SimpleTy != MVT::isVoid) 857 return 0; 858 if ((!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 859 return fastEmitInst_r(Mips::JALRHB64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill); 860 } 861 if ((!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) { 862 return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill); 863 } 864 return 0; 865} 866 867unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 868 switch (VT.SimpleTy) { 869 case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0, Op0IsKill); 870 case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0, Op0IsKill); 871 default: return 0; 872 } 873} 874 875// FastEmit functions for MipsISD::MFHI. 876 877unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 878 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) { 879 return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 880 } 881 if ((Subtarget->hasDSP())) { 882 return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill); 883 } 884 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 885 return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill); 886 } 887 return 0; 888} 889 890unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 891 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 892 return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill); 893 } 894 return 0; 895} 896 897unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 898switch (RetVT.SimpleTy) { 899 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill); 900 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill); 901 default: return 0; 902} 903} 904 905unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 906 switch (VT.SimpleTy) { 907 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill); 908 default: return 0; 909 } 910} 911 912// FastEmit functions for MipsISD::MFLO. 913 914unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) { 915 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) { 916 return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 917 } 918 if ((Subtarget->hasDSP())) { 919 return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill); 920 } 921 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 922 return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill); 923 } 924 return 0; 925} 926 927unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) { 928 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 929 return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill); 930 } 931 return 0; 932} 933 934unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 935switch (RetVT.SimpleTy) { 936 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill); 937 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill); 938 default: return 0; 939} 940} 941 942unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 943 switch (VT.SimpleTy) { 944 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill); 945 default: return 0; 946 } 947} 948 949// FastEmit functions for MipsISD::MTC1_D64. 950 951unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 952 if (RetVT.SimpleTy != MVT::f64) 953 return 0; 954 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) { 955 return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 956 } 957 return 0; 958} 959 960unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 961 switch (VT.SimpleTy) { 962 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0, Op0IsKill); 963 default: return 0; 964 } 965} 966 967// FastEmit functions for MipsISD::TailCall. 968 969unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 970 if (RetVT.SimpleTy != MVT::isVoid) 971 return 0; 972 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 973 return fastEmitInst_r(Mips::TAILCALLREG_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill); 974 } 975 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 976 return fastEmitInst_r(Mips::TAILCALLREG_MM, &Mips::GPR32RegClass, Op0, Op0IsKill); 977 } 978 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 979 return fastEmitInst_r(Mips::TAILCALLHBR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill); 980 } 981 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) { 982 return fastEmitInst_r(Mips::TAILCALLR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill); 983 } 984 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) { 985 return fastEmitInst_r(Mips::TAILCALLREGHB, &Mips::GPR32RegClass, Op0, Op0IsKill); 986 } 987 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 988 return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill); 989 } 990 return 0; 991} 992 993unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 994 if (RetVT.SimpleTy != MVT::isVoid) 995 return 0; 996 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) { 997 return fastEmitInst_r(Mips::TAILCALLHB64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill); 998 } 999 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) { 1000 return fastEmitInst_r(Mips::TAILCALL64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill); 1001 } 1002 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) { 1003 return fastEmitInst_r(Mips::TAILCALLREGHB64, &Mips::GPR64RegClass, Op0, Op0IsKill); 1004 } 1005 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 1006 return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill); 1007 } 1008 return 0; 1009} 1010 1011unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1012 switch (VT.SimpleTy) { 1013 case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0, Op0IsKill); 1014 case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0, Op0IsKill); 1015 default: return 0; 1016 } 1017} 1018 1019// FastEmit functions for MipsISD::TruncIntFP. 1020 1021unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 1022 if ((Subtarget->hasStandardEncoding())) { 1023 return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill); 1024 } 1025 return 0; 1026} 1027 1028unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1029 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) { 1030 return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill); 1031 } 1032 return 0; 1033} 1034 1035unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1036switch (RetVT.SimpleTy) { 1037 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill); 1038 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0, Op0IsKill); 1039 default: return 0; 1040} 1041} 1042 1043unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) { 1044 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1045 return fastEmitInst_r(Mips::TRUNC_W_D_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill); 1046 } 1047 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) { 1048 return fastEmitInst_r(Mips::TRUNC_W_MM, &Mips::FGR32RegClass, Op0, Op0IsKill); 1049 } 1050 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) { 1051 return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill); 1052 } 1053 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1054 return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill); 1055 } 1056 return 0; 1057} 1058 1059unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0, bool Op0IsKill) { 1060 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) { 1061 return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill); 1062 } 1063 return 0; 1064} 1065 1066unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1067switch (RetVT.SimpleTy) { 1068 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill); 1069 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0, Op0IsKill); 1070 default: return 0; 1071} 1072} 1073 1074unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1075 switch (VT.SimpleTy) { 1076 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill); 1077 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0, Op0IsKill); 1078 default: return 0; 1079 } 1080} 1081 1082// FastEmit functions for MipsISD::VALL_NONZERO. 1083 1084unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1085 if (RetVT.SimpleTy != MVT::i32) 1086 return 0; 1087 return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1088} 1089 1090unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1091 if (RetVT.SimpleTy != MVT::i32) 1092 return 0; 1093 return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1094} 1095 1096unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1097 if (RetVT.SimpleTy != MVT::i32) 1098 return 0; 1099 return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1100} 1101 1102unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1103 if (RetVT.SimpleTy != MVT::i32) 1104 return 0; 1105 return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1106} 1107 1108unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1109 switch (VT.SimpleTy) { 1110 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1111 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1112 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1113 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1114 default: return 0; 1115 } 1116} 1117 1118// FastEmit functions for MipsISD::VALL_ZERO. 1119 1120unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1121 if (RetVT.SimpleTy != MVT::i32) 1122 return 0; 1123 return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1124} 1125 1126unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1127 if (RetVT.SimpleTy != MVT::i32) 1128 return 0; 1129 return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1130} 1131 1132unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1133 if (RetVT.SimpleTy != MVT::i32) 1134 return 0; 1135 return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1136} 1137 1138unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1139 if (RetVT.SimpleTy != MVT::i32) 1140 return 0; 1141 return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1142} 1143 1144unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1145 switch (VT.SimpleTy) { 1146 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1147 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill); 1148 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill); 1149 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill); 1150 default: return 0; 1151 } 1152} 1153 1154// FastEmit functions for MipsISD::VANY_NONZERO. 1155 1156unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1157 if (RetVT.SimpleTy != MVT::i32) 1158 return 0; 1159 return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1160} 1161 1162unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1163 switch (VT.SimpleTy) { 1164 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1165 default: return 0; 1166 } 1167} 1168 1169// FastEmit functions for MipsISD::VANY_ZERO. 1170 1171unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) { 1172 if (RetVT.SimpleTy != MVT::i32) 1173 return 0; 1174 return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill); 1175} 1176 1177unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) { 1178 switch (VT.SimpleTy) { 1179 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill); 1180 default: return 0; 1181 } 1182} 1183 1184// Top-level FastEmit function. 1185 1186unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override { 1187 switch (Opcode) { 1188 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill); 1189 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill); 1190 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill); 1191 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill); 1192 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill); 1193 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill); 1194 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0, Op0IsKill); 1195 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill); 1196 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 1197 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill); 1198 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill); 1199 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill); 1200 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill); 1201 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill); 1202 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill); 1203 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 1204 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill); 1205 case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0, Op0IsKill); 1206 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0, Op0IsKill); 1207 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0, Op0IsKill); 1208 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill); 1209 case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0, Op0IsKill); 1210 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0, Op0IsKill); 1211 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0, Op0IsKill); 1212 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0, Op0IsKill); 1213 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0, Op0IsKill); 1214 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0, Op0IsKill); 1215 default: return 0; 1216 } 1217} 1218 1219// FastEmit functions for ISD::ADD. 1220 1221unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1222 if (RetVT.SimpleTy != MVT::i32) 1223 return 0; 1224 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1225 return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1226 } 1227 if ((Subtarget->inMips16Mode())) { 1228 return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1229 } 1230 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 1231 return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1232 } 1233 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1234 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1235 } 1236 return 0; 1237} 1238 1239unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1240 if (RetVT.SimpleTy != MVT::i64) 1241 return 0; 1242 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1243 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1244 } 1245 return 0; 1246} 1247 1248unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1249 if (RetVT.SimpleTy != MVT::v4i8) 1250 return 0; 1251 if ((Subtarget->hasDSP())) { 1252 return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1253 } 1254 return 0; 1255} 1256 1257unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1258 if (RetVT.SimpleTy != MVT::v16i8) 1259 return 0; 1260 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1261 return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1262 } 1263 return 0; 1264} 1265 1266unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1267 if (RetVT.SimpleTy != MVT::v2i16) 1268 return 0; 1269 if ((Subtarget->hasDSP())) { 1270 return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1271 } 1272 return 0; 1273} 1274 1275unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1276 if (RetVT.SimpleTy != MVT::v8i16) 1277 return 0; 1278 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1279 return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1280 } 1281 return 0; 1282} 1283 1284unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1285 if (RetVT.SimpleTy != MVT::v4i32) 1286 return 0; 1287 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1288 return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1289 } 1290 return 0; 1291} 1292 1293unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1294 if (RetVT.SimpleTy != MVT::v2i64) 1295 return 0; 1296 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1297 return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1298 } 1299 return 0; 1300} 1301 1302unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1303 switch (VT.SimpleTy) { 1304 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1305 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1306 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1307 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1308 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1309 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1310 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1311 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1312 default: return 0; 1313 } 1314} 1315 1316// FastEmit functions for ISD::ADDC. 1317 1318unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1319 if (RetVT.SimpleTy != MVT::i32) 1320 return 0; 1321 if ((Subtarget->hasDSP())) { 1322 return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1323 } 1324 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) { 1325 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1326 } 1327 return 0; 1328} 1329 1330unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1331 if (RetVT.SimpleTy != MVT::i64) 1332 return 0; 1333 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) { 1334 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1335 } 1336 return 0; 1337} 1338 1339unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1340 switch (VT.SimpleTy) { 1341 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1342 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1343 default: return 0; 1344 } 1345} 1346 1347// FastEmit functions for ISD::ADDE. 1348 1349unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1350 if (RetVT.SimpleTy != MVT::i32) 1351 return 0; 1352 if ((Subtarget->hasDSP())) { 1353 return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1354 } 1355 return 0; 1356} 1357 1358unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1359 switch (VT.SimpleTy) { 1360 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1361 default: return 0; 1362 } 1363} 1364 1365// FastEmit functions for ISD::AND. 1366 1367unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1368 if (RetVT.SimpleTy != MVT::i32) 1369 return 0; 1370 if ((Subtarget->inMips16Mode())) { 1371 return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1372 } 1373 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1374 return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1375 } 1376 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 1377 return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1378 } 1379 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1380 return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1381 } 1382 return 0; 1383} 1384 1385unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1386 if (RetVT.SimpleTy != MVT::i64) 1387 return 0; 1388 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) { 1389 return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1390 } 1391 return 0; 1392} 1393 1394unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1395 if (RetVT.SimpleTy != MVT::v16i8) 1396 return 0; 1397 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1398 return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1399 } 1400 return 0; 1401} 1402 1403unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1404 if (RetVT.SimpleTy != MVT::v8i16) 1405 return 0; 1406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1407 return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1408 } 1409 return 0; 1410} 1411 1412unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1413 if (RetVT.SimpleTy != MVT::v4i32) 1414 return 0; 1415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1416 return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1417 } 1418 return 0; 1419} 1420 1421unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1422 if (RetVT.SimpleTy != MVT::v2i64) 1423 return 0; 1424 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1425 return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1426 } 1427 return 0; 1428} 1429 1430unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1431 switch (VT.SimpleTy) { 1432 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1433 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1434 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1435 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1436 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1437 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1438 default: return 0; 1439 } 1440} 1441 1442// FastEmit functions for ISD::FADD. 1443 1444unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1445 if (RetVT.SimpleTy != MVT::f32) 1446 return 0; 1447 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 1448 return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1449 } 1450 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1451 return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1452 } 1453 return 0; 1454} 1455 1456unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1457 if (RetVT.SimpleTy != MVT::f64) 1458 return 0; 1459 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 1460 return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1461 } 1462 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 1463 return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1464 } 1465 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1466 return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1467 } 1468 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1469 return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1470 } 1471 return 0; 1472} 1473 1474unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1475 if (RetVT.SimpleTy != MVT::v4f32) 1476 return 0; 1477 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1478 return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1479 } 1480 return 0; 1481} 1482 1483unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1484 if (RetVT.SimpleTy != MVT::v2f64) 1485 return 0; 1486 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1487 return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1488 } 1489 return 0; 1490} 1491 1492unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1493 switch (VT.SimpleTy) { 1494 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1495 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1496 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1497 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1498 default: return 0; 1499 } 1500} 1501 1502// FastEmit functions for ISD::FDIV. 1503 1504unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1505 if (RetVT.SimpleTy != MVT::f32) 1506 return 0; 1507 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 1508 return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1509 } 1510 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1511 return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1512 } 1513 return 0; 1514} 1515 1516unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1517 if (RetVT.SimpleTy != MVT::f64) 1518 return 0; 1519 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 1520 return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1521 } 1522 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 1523 return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1524 } 1525 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1526 return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1527 } 1528 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1529 return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1530 } 1531 return 0; 1532} 1533 1534unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1535 if (RetVT.SimpleTy != MVT::v4f32) 1536 return 0; 1537 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1538 return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1539 } 1540 return 0; 1541} 1542 1543unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1544 if (RetVT.SimpleTy != MVT::v2f64) 1545 return 0; 1546 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1547 return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1548 } 1549 return 0; 1550} 1551 1552unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1553 switch (VT.SimpleTy) { 1554 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1555 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1556 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1557 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1558 default: return 0; 1559 } 1560} 1561 1562// FastEmit functions for ISD::FMUL. 1563 1564unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1565 if (RetVT.SimpleTy != MVT::f32) 1566 return 0; 1567 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 1568 return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1569 } 1570 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1571 return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1572 } 1573 return 0; 1574} 1575 1576unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1577 if (RetVT.SimpleTy != MVT::f64) 1578 return 0; 1579 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 1580 return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1581 } 1582 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 1583 return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1584 } 1585 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1586 return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1587 } 1588 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1589 return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1590 } 1591 return 0; 1592} 1593 1594unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1595 if (RetVT.SimpleTy != MVT::v4f32) 1596 return 0; 1597 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1598 return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1599 } 1600 return 0; 1601} 1602 1603unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1604 if (RetVT.SimpleTy != MVT::v2f64) 1605 return 0; 1606 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1607 return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1608 } 1609 return 0; 1610} 1611 1612unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1613 switch (VT.SimpleTy) { 1614 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1615 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1616 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1617 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1618 default: return 0; 1619 } 1620} 1621 1622// FastEmit functions for ISD::FSUB. 1623 1624unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1625 if (RetVT.SimpleTy != MVT::f32) 1626 return 0; 1627 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) { 1628 return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1629 } 1630 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1631 return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1632 } 1633 return 0; 1634} 1635 1636unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1637 if (RetVT.SimpleTy != MVT::f64) 1638 return 0; 1639 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) { 1640 return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1641 } 1642 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) { 1643 return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1644 } 1645 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) { 1646 return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1647 } 1648 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) { 1649 return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1650 } 1651 return 0; 1652} 1653 1654unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1655 if (RetVT.SimpleTy != MVT::v4f32) 1656 return 0; 1657 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1658 return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1659 } 1660 return 0; 1661} 1662 1663unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1664 if (RetVT.SimpleTy != MVT::v2f64) 1665 return 0; 1666 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1667 return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1668 } 1669 return 0; 1670} 1671 1672unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1673 switch (VT.SimpleTy) { 1674 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1675 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1676 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1677 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1678 default: return 0; 1679 } 1680} 1681 1682// FastEmit functions for ISD::MUL. 1683 1684unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1685 if (RetVT.SimpleTy != MVT::i32) 1686 return 0; 1687 if ((Subtarget->inMips16Mode())) { 1688 return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1689 } 1690 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1691 return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1692 } 1693 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 1694 return fastEmitInst_rr(Mips::MUL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1695 } 1696 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1697 return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1698 } 1699 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 1700 return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1701 } 1702 return 0; 1703} 1704 1705unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1706 if (RetVT.SimpleTy != MVT::i64) 1707 return 0; 1708 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1709 return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1710 } 1711 if ((Subtarget->hasCnMips())) { 1712 return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1713 } 1714 return 0; 1715} 1716 1717unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1718 if (RetVT.SimpleTy != MVT::v16i8) 1719 return 0; 1720 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1721 return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1722 } 1723 return 0; 1724} 1725 1726unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1727 if (RetVT.SimpleTy != MVT::v2i16) 1728 return 0; 1729 if ((Subtarget->hasDSPR2())) { 1730 return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1731 } 1732 return 0; 1733} 1734 1735unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1736 if (RetVT.SimpleTy != MVT::v8i16) 1737 return 0; 1738 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1739 return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1740 } 1741 return 0; 1742} 1743 1744unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1745 if (RetVT.SimpleTy != MVT::v4i32) 1746 return 0; 1747 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1748 return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1749 } 1750 return 0; 1751} 1752 1753unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1754 if (RetVT.SimpleTy != MVT::v2i64) 1755 return 0; 1756 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1757 return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1758 } 1759 return 0; 1760} 1761 1762unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1763 switch (VT.SimpleTy) { 1764 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1765 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1766 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1767 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1768 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1769 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1770 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1771 default: return 0; 1772 } 1773} 1774 1775// FastEmit functions for ISD::MULHS. 1776 1777unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1778 if (RetVT.SimpleTy != MVT::i32) 1779 return 0; 1780 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1781 return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1782 } 1783 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1784 return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1785 } 1786 return 0; 1787} 1788 1789unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1790 if (RetVT.SimpleTy != MVT::i64) 1791 return 0; 1792 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1793 return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1794 } 1795 return 0; 1796} 1797 1798unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1799 switch (VT.SimpleTy) { 1800 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1801 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1802 default: return 0; 1803 } 1804} 1805 1806// FastEmit functions for ISD::MULHU. 1807 1808unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1809 if (RetVT.SimpleTy != MVT::i32) 1810 return 0; 1811 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1812 return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1813 } 1814 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1815 return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1816 } 1817 return 0; 1818} 1819 1820unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1821 if (RetVT.SimpleTy != MVT::i64) 1822 return 0; 1823 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1824 return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1825 } 1826 return 0; 1827} 1828 1829unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1830 switch (VT.SimpleTy) { 1831 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1832 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1833 default: return 0; 1834 } 1835} 1836 1837// FastEmit functions for ISD::OR. 1838 1839unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1840 if (RetVT.SimpleTy != MVT::i32) 1841 return 0; 1842 if ((Subtarget->inMips16Mode())) { 1843 return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1844 } 1845 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1846 return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1847 } 1848 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 1849 return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1850 } 1851 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1852 return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1853 } 1854 return 0; 1855} 1856 1857unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1858 if (RetVT.SimpleTy != MVT::i64) 1859 return 0; 1860 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) { 1861 return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1862 } 1863 return 0; 1864} 1865 1866unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1867 if (RetVT.SimpleTy != MVT::v16i8) 1868 return 0; 1869 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1870 return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1871 } 1872 return 0; 1873} 1874 1875unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1876 if (RetVT.SimpleTy != MVT::v8i16) 1877 return 0; 1878 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1879 return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1880 } 1881 return 0; 1882} 1883 1884unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1885 if (RetVT.SimpleTy != MVT::v4i32) 1886 return 0; 1887 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1888 return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1889 } 1890 return 0; 1891} 1892 1893unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1894 if (RetVT.SimpleTy != MVT::v2i64) 1895 return 0; 1896 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1897 return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1898 } 1899 return 0; 1900} 1901 1902unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1903 switch (VT.SimpleTy) { 1904 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1905 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1906 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1907 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1908 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1909 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1910 default: return 0; 1911 } 1912} 1913 1914// FastEmit functions for ISD::ROTR. 1915 1916unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1917 if (RetVT.SimpleTy != MVT::i32) 1918 return 0; 1919 if ((Subtarget->inMicroMipsMode())) { 1920 return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1921 } 1922 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1923 return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1924 } 1925 return 0; 1926} 1927 1928unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1929 switch (VT.SimpleTy) { 1930 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1931 default: return 0; 1932 } 1933} 1934 1935// FastEmit functions for ISD::SDIV. 1936 1937unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1938 if (RetVT.SimpleTy != MVT::i32) 1939 return 0; 1940 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 1941 return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1942 } 1943 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1944 return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1945 } 1946 return 0; 1947} 1948 1949unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1950 if (RetVT.SimpleTy != MVT::i64) 1951 return 0; 1952 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 1953 return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1954 } 1955 return 0; 1956} 1957 1958unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1959 if (RetVT.SimpleTy != MVT::v16i8) 1960 return 0; 1961 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1962 return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1963 } 1964 return 0; 1965} 1966 1967unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1968 if (RetVT.SimpleTy != MVT::v8i16) 1969 return 0; 1970 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1971 return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1972 } 1973 return 0; 1974} 1975 1976unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1977 if (RetVT.SimpleTy != MVT::v4i32) 1978 return 0; 1979 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1980 return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1981 } 1982 return 0; 1983} 1984 1985unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1986 if (RetVT.SimpleTy != MVT::v2i64) 1987 return 0; 1988 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 1989 return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 1990 } 1991 return 0; 1992} 1993 1994unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 1995 switch (VT.SimpleTy) { 1996 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1997 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1998 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 1999 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2000 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2001 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2002 default: return 0; 2003 } 2004} 2005 2006// FastEmit functions for ISD::SHL. 2007 2008unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2009 if (RetVT.SimpleTy != MVT::i32) 2010 return 0; 2011 if ((Subtarget->inMicroMipsMode())) { 2012 return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2013 } 2014 if ((Subtarget->inMips16Mode())) { 2015 return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2016 } 2017 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2018 return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2019 } 2020 return 0; 2021} 2022 2023unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2024 if (RetVT.SimpleTy != MVT::v16i8) 2025 return 0; 2026 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2027 return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2028 } 2029 return 0; 2030} 2031 2032unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2033 if (RetVT.SimpleTy != MVT::v8i16) 2034 return 0; 2035 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2036 return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2037 } 2038 return 0; 2039} 2040 2041unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2042 if (RetVT.SimpleTy != MVT::v4i32) 2043 return 0; 2044 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2045 return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2046 } 2047 return 0; 2048} 2049 2050unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2051 if (RetVT.SimpleTy != MVT::v2i64) 2052 return 0; 2053 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2054 return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2055 } 2056 return 0; 2057} 2058 2059unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2060 switch (VT.SimpleTy) { 2061 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2062 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2063 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2064 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2065 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2066 default: return 0; 2067 } 2068} 2069 2070// FastEmit functions for ISD::SMAX. 2071 2072unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2073 if (RetVT.SimpleTy != MVT::v16i8) 2074 return 0; 2075 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2076 return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2077 } 2078 return 0; 2079} 2080 2081unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2082 if (RetVT.SimpleTy != MVT::v8i16) 2083 return 0; 2084 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2085 return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2086 } 2087 return 0; 2088} 2089 2090unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2091 if (RetVT.SimpleTy != MVT::v4i32) 2092 return 0; 2093 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2094 return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2095 } 2096 return 0; 2097} 2098 2099unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2100 if (RetVT.SimpleTy != MVT::v2i64) 2101 return 0; 2102 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2103 return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2104 } 2105 return 0; 2106} 2107 2108unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2109 switch (VT.SimpleTy) { 2110 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2111 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2112 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2113 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2114 default: return 0; 2115 } 2116} 2117 2118// FastEmit functions for ISD::SMIN. 2119 2120unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2121 if (RetVT.SimpleTy != MVT::v16i8) 2122 return 0; 2123 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2124 return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2125 } 2126 return 0; 2127} 2128 2129unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2130 if (RetVT.SimpleTy != MVT::v8i16) 2131 return 0; 2132 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2133 return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2134 } 2135 return 0; 2136} 2137 2138unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2139 if (RetVT.SimpleTy != MVT::v4i32) 2140 return 0; 2141 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2142 return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2143 } 2144 return 0; 2145} 2146 2147unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2148 if (RetVT.SimpleTy != MVT::v2i64) 2149 return 0; 2150 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2151 return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2152 } 2153 return 0; 2154} 2155 2156unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2157 switch (VT.SimpleTy) { 2158 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2159 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2160 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2161 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2162 default: return 0; 2163 } 2164} 2165 2166// FastEmit functions for ISD::SRA. 2167 2168unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2169 if (RetVT.SimpleTy != MVT::i32) 2170 return 0; 2171 if ((Subtarget->inMicroMipsMode())) { 2172 return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2173 } 2174 if ((Subtarget->inMips16Mode())) { 2175 return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2176 } 2177 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2178 return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2179 } 2180 return 0; 2181} 2182 2183unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2184 if (RetVT.SimpleTy != MVT::v16i8) 2185 return 0; 2186 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2187 return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2188 } 2189 return 0; 2190} 2191 2192unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2193 if (RetVT.SimpleTy != MVT::v8i16) 2194 return 0; 2195 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2196 return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2197 } 2198 return 0; 2199} 2200 2201unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2202 if (RetVT.SimpleTy != MVT::v4i32) 2203 return 0; 2204 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2205 return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2206 } 2207 return 0; 2208} 2209 2210unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2211 if (RetVT.SimpleTy != MVT::v2i64) 2212 return 0; 2213 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2214 return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2215 } 2216 return 0; 2217} 2218 2219unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2220 switch (VT.SimpleTy) { 2221 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2222 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2223 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2224 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2225 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2226 default: return 0; 2227 } 2228} 2229 2230// FastEmit functions for ISD::SREM. 2231 2232unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2233 if (RetVT.SimpleTy != MVT::i32) 2234 return 0; 2235 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2236 return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2237 } 2238 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2239 return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2240 } 2241 return 0; 2242} 2243 2244unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2245 if (RetVT.SimpleTy != MVT::i64) 2246 return 0; 2247 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2248 return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2249 } 2250 return 0; 2251} 2252 2253unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2254 if (RetVT.SimpleTy != MVT::v16i8) 2255 return 0; 2256 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2257 return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2258 } 2259 return 0; 2260} 2261 2262unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2263 if (RetVT.SimpleTy != MVT::v8i16) 2264 return 0; 2265 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2266 return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2267 } 2268 return 0; 2269} 2270 2271unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2272 if (RetVT.SimpleTy != MVT::v4i32) 2273 return 0; 2274 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2275 return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2276 } 2277 return 0; 2278} 2279 2280unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2281 if (RetVT.SimpleTy != MVT::v2i64) 2282 return 0; 2283 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2284 return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2285 } 2286 return 0; 2287} 2288 2289unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2290 switch (VT.SimpleTy) { 2291 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2292 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2293 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2294 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2295 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2296 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2297 default: return 0; 2298 } 2299} 2300 2301// FastEmit functions for ISD::SRL. 2302 2303unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2304 if (RetVT.SimpleTy != MVT::i32) 2305 return 0; 2306 if ((Subtarget->inMicroMipsMode())) { 2307 return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2308 } 2309 if ((Subtarget->inMips16Mode())) { 2310 return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2311 } 2312 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2313 return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2314 } 2315 return 0; 2316} 2317 2318unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2319 if (RetVT.SimpleTy != MVT::v16i8) 2320 return 0; 2321 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2322 return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2323 } 2324 return 0; 2325} 2326 2327unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2328 if (RetVT.SimpleTy != MVT::v8i16) 2329 return 0; 2330 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2331 return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2332 } 2333 return 0; 2334} 2335 2336unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2337 if (RetVT.SimpleTy != MVT::v4i32) 2338 return 0; 2339 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2340 return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2341 } 2342 return 0; 2343} 2344 2345unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2346 if (RetVT.SimpleTy != MVT::v2i64) 2347 return 0; 2348 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2349 return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2350 } 2351 return 0; 2352} 2353 2354unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2355 switch (VT.SimpleTy) { 2356 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2357 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2358 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2359 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2360 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2361 default: return 0; 2362 } 2363} 2364 2365// FastEmit functions for ISD::SUB. 2366 2367unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2368 if (RetVT.SimpleTy != MVT::i32) 2369 return 0; 2370 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2371 return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2372 } 2373 if ((Subtarget->inMips16Mode())) { 2374 return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2375 } 2376 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 2377 return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2378 } 2379 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2380 return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2381 } 2382 return 0; 2383} 2384 2385unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2386 if (RetVT.SimpleTy != MVT::i64) 2387 return 0; 2388 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2389 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2390 } 2391 return 0; 2392} 2393 2394unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2395 if (RetVT.SimpleTy != MVT::v4i8) 2396 return 0; 2397 if ((Subtarget->hasDSP())) { 2398 return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2399 } 2400 return 0; 2401} 2402 2403unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2404 if (RetVT.SimpleTy != MVT::v16i8) 2405 return 0; 2406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2407 return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2408 } 2409 return 0; 2410} 2411 2412unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2413 if (RetVT.SimpleTy != MVT::v2i16) 2414 return 0; 2415 if ((Subtarget->hasDSP())) { 2416 return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2417 } 2418 return 0; 2419} 2420 2421unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2422 if (RetVT.SimpleTy != MVT::v8i16) 2423 return 0; 2424 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2425 return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2426 } 2427 return 0; 2428} 2429 2430unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2431 if (RetVT.SimpleTy != MVT::v4i32) 2432 return 0; 2433 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2434 return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2435 } 2436 return 0; 2437} 2438 2439unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2440 if (RetVT.SimpleTy != MVT::v2i64) 2441 return 0; 2442 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2443 return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2444 } 2445 return 0; 2446} 2447 2448unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2449 switch (VT.SimpleTy) { 2450 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2451 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2452 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2453 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2454 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2455 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2456 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2457 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2458 default: return 0; 2459 } 2460} 2461 2462// FastEmit functions for ISD::SUBC. 2463 2464unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2465 if (RetVT.SimpleTy != MVT::i32) 2466 return 0; 2467 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2468 return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2469 } 2470 if ((Subtarget->inMicroMipsMode())) { 2471 return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2472 } 2473 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2474 return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2475 } 2476 return 0; 2477} 2478 2479unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2480 if (RetVT.SimpleTy != MVT::i64) 2481 return 0; 2482 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) { 2483 return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2484 } 2485 return 0; 2486} 2487 2488unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2489 switch (VT.SimpleTy) { 2490 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2491 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2492 default: return 0; 2493 } 2494} 2495 2496// FastEmit functions for ISD::UDIV. 2497 2498unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2499 if (RetVT.SimpleTy != MVT::i32) 2500 return 0; 2501 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2502 return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2503 } 2504 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2505 return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2506 } 2507 return 0; 2508} 2509 2510unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2511 if (RetVT.SimpleTy != MVT::i64) 2512 return 0; 2513 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2514 return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2515 } 2516 return 0; 2517} 2518 2519unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2520 if (RetVT.SimpleTy != MVT::v16i8) 2521 return 0; 2522 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2523 return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2524 } 2525 return 0; 2526} 2527 2528unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2529 if (RetVT.SimpleTy != MVT::v8i16) 2530 return 0; 2531 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2532 return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2533 } 2534 return 0; 2535} 2536 2537unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2538 if (RetVT.SimpleTy != MVT::v4i32) 2539 return 0; 2540 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2541 return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2542 } 2543 return 0; 2544} 2545 2546unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2547 if (RetVT.SimpleTy != MVT::v2i64) 2548 return 0; 2549 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2550 return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2551 } 2552 return 0; 2553} 2554 2555unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2556 switch (VT.SimpleTy) { 2557 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2558 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2559 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2560 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2561 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2562 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2563 default: return 0; 2564 } 2565} 2566 2567// FastEmit functions for ISD::UMAX. 2568 2569unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2570 if (RetVT.SimpleTy != MVT::v16i8) 2571 return 0; 2572 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2573 return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2574 } 2575 return 0; 2576} 2577 2578unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2579 if (RetVT.SimpleTy != MVT::v8i16) 2580 return 0; 2581 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2582 return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2583 } 2584 return 0; 2585} 2586 2587unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2588 if (RetVT.SimpleTy != MVT::v4i32) 2589 return 0; 2590 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2591 return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2592 } 2593 return 0; 2594} 2595 2596unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2597 if (RetVT.SimpleTy != MVT::v2i64) 2598 return 0; 2599 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2600 return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2601 } 2602 return 0; 2603} 2604 2605unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2606 switch (VT.SimpleTy) { 2607 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2608 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2609 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2610 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2611 default: return 0; 2612 } 2613} 2614 2615// FastEmit functions for ISD::UMIN. 2616 2617unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2618 if (RetVT.SimpleTy != MVT::v16i8) 2619 return 0; 2620 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2621 return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2622 } 2623 return 0; 2624} 2625 2626unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2627 if (RetVT.SimpleTy != MVT::v8i16) 2628 return 0; 2629 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2630 return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2631 } 2632 return 0; 2633} 2634 2635unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2636 if (RetVT.SimpleTy != MVT::v4i32) 2637 return 0; 2638 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2639 return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2640 } 2641 return 0; 2642} 2643 2644unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2645 if (RetVT.SimpleTy != MVT::v2i64) 2646 return 0; 2647 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2648 return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2649 } 2650 return 0; 2651} 2652 2653unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2654 switch (VT.SimpleTy) { 2655 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2656 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2657 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2658 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2659 default: return 0; 2660 } 2661} 2662 2663// FastEmit functions for ISD::UREM. 2664 2665unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2666 if (RetVT.SimpleTy != MVT::i32) 2667 return 0; 2668 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2669 return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2670 } 2671 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2672 return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2673 } 2674 return 0; 2675} 2676 2677unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2678 if (RetVT.SimpleTy != MVT::i64) 2679 return 0; 2680 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2681 return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2682 } 2683 return 0; 2684} 2685 2686unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2687 if (RetVT.SimpleTy != MVT::v16i8) 2688 return 0; 2689 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2690 return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2691 } 2692 return 0; 2693} 2694 2695unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2696 if (RetVT.SimpleTy != MVT::v8i16) 2697 return 0; 2698 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2699 return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2700 } 2701 return 0; 2702} 2703 2704unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2705 if (RetVT.SimpleTy != MVT::v4i32) 2706 return 0; 2707 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2708 return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2709 } 2710 return 0; 2711} 2712 2713unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2714 if (RetVT.SimpleTy != MVT::v2i64) 2715 return 0; 2716 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2717 return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2718 } 2719 return 0; 2720} 2721 2722unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2723 switch (VT.SimpleTy) { 2724 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2725 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2726 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2727 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2728 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2729 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2730 default: return 0; 2731 } 2732} 2733 2734// FastEmit functions for ISD::XOR. 2735 2736unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2737 if (RetVT.SimpleTy != MVT::i32) 2738 return 0; 2739 if ((Subtarget->inMips16Mode())) { 2740 return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2741 } 2742 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 2743 return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2744 } 2745 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) { 2746 return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2747 } 2748 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 2749 return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2750 } 2751 return 0; 2752} 2753 2754unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2755 if (RetVT.SimpleTy != MVT::i64) 2756 return 0; 2757 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) { 2758 return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2759 } 2760 return 0; 2761} 2762 2763unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2764 if (RetVT.SimpleTy != MVT::v16i8) 2765 return 0; 2766 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2767 return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2768 } 2769 return 0; 2770} 2771 2772unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2773 if (RetVT.SimpleTy != MVT::v8i16) 2774 return 0; 2775 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2776 return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2777 } 2778 return 0; 2779} 2780 2781unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2782 if (RetVT.SimpleTy != MVT::v4i32) 2783 return 0; 2784 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2785 return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2786 } 2787 return 0; 2788} 2789 2790unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2791 if (RetVT.SimpleTy != MVT::v2i64) 2792 return 0; 2793 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2794 return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2795 } 2796 return 0; 2797} 2798 2799unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2800 switch (VT.SimpleTy) { 2801 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2802 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2803 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2804 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2805 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2806 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2807 default: return 0; 2808 } 2809} 2810 2811// FastEmit functions for MipsISD::BuildPairF64. 2812 2813unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2814 if (RetVT.SimpleTy != MVT::f64) 2815 return 0; 2816 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) { 2817 return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2818 } 2819 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) { 2820 return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2821 } 2822 return 0; 2823} 2824 2825unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2826 switch (VT.SimpleTy) { 2827 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2828 default: return 0; 2829 } 2830} 2831 2832// FastEmit functions for MipsISD::DivRem. 2833 2834unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2835 if (RetVT.SimpleTy != MVT::Untyped) 2836 return 0; 2837 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2838 return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2839 } 2840 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2841 return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2842 } 2843 return 0; 2844} 2845 2846unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2847 if (RetVT.SimpleTy != MVT::Untyped) 2848 return 0; 2849 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2850 return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2851 } 2852 return 0; 2853} 2854 2855unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2856 switch (VT.SimpleTy) { 2857 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2858 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2859 default: return 0; 2860 } 2861} 2862 2863// FastEmit functions for MipsISD::DivRem16. 2864 2865unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2866 if (RetVT.SimpleTy != MVT::isVoid) 2867 return 0; 2868 if ((Subtarget->inMips16Mode())) { 2869 return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2870 } 2871 return 0; 2872} 2873 2874unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2875 switch (VT.SimpleTy) { 2876 case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2877 default: return 0; 2878 } 2879} 2880 2881// FastEmit functions for MipsISD::DivRemU. 2882 2883unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2884 if (RetVT.SimpleTy != MVT::Untyped) 2885 return 0; 2886 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2887 return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2888 } 2889 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2890 return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2891 } 2892 return 0; 2893} 2894 2895unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2896 if (RetVT.SimpleTy != MVT::Untyped) 2897 return 0; 2898 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 2899 return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2900 } 2901 return 0; 2902} 2903 2904unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2905 switch (VT.SimpleTy) { 2906 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2907 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2908 default: return 0; 2909 } 2910} 2911 2912// FastEmit functions for MipsISD::DivRemU16. 2913 2914unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2915 if (RetVT.SimpleTy != MVT::isVoid) 2916 return 0; 2917 if ((Subtarget->inMips16Mode())) { 2918 return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2919 } 2920 return 0; 2921} 2922 2923unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2924 switch (VT.SimpleTy) { 2925 case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2926 default: return 0; 2927 } 2928} 2929 2930// FastEmit functions for MipsISD::EH_RETURN. 2931 2932unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2933 if (RetVT.SimpleTy != MVT::isVoid) 2934 return 0; 2935 return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2936} 2937 2938unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2939 if (RetVT.SimpleTy != MVT::isVoid) 2940 return 0; 2941 return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2942} 2943 2944unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2945 switch (VT.SimpleTy) { 2946 case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2947 case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2948 default: return 0; 2949 } 2950} 2951 2952// FastEmit functions for MipsISD::ILVEV. 2953 2954unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2955 if (RetVT.SimpleTy != MVT::v16i8) 2956 return 0; 2957 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2958 return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2959 } 2960 return 0; 2961} 2962 2963unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2964 if (RetVT.SimpleTy != MVT::v8i16) 2965 return 0; 2966 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2967 return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2968 } 2969 return 0; 2970} 2971 2972unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2973 if (RetVT.SimpleTy != MVT::v4i32) 2974 return 0; 2975 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2976 return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2977 } 2978 return 0; 2979} 2980 2981unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2982 if (RetVT.SimpleTy != MVT::v2i64) 2983 return 0; 2984 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 2985 return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 2986 } 2987 return 0; 2988} 2989 2990unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 2991 switch (VT.SimpleTy) { 2992 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2993 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2994 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2995 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 2996 default: return 0; 2997 } 2998} 2999 3000// FastEmit functions for MipsISD::ILVL. 3001 3002unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3003 if (RetVT.SimpleTy != MVT::v16i8) 3004 return 0; 3005 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3006 return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3007 } 3008 return 0; 3009} 3010 3011unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3012 if (RetVT.SimpleTy != MVT::v8i16) 3013 return 0; 3014 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3015 return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3016 } 3017 return 0; 3018} 3019 3020unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3021 if (RetVT.SimpleTy != MVT::v4i32) 3022 return 0; 3023 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3024 return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3025 } 3026 return 0; 3027} 3028 3029unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3030 if (RetVT.SimpleTy != MVT::v2i64) 3031 return 0; 3032 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3033 return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3034 } 3035 return 0; 3036} 3037 3038unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3039 switch (VT.SimpleTy) { 3040 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3041 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3042 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3043 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3044 default: return 0; 3045 } 3046} 3047 3048// FastEmit functions for MipsISD::ILVOD. 3049 3050unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3051 if (RetVT.SimpleTy != MVT::v16i8) 3052 return 0; 3053 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3054 return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3055 } 3056 return 0; 3057} 3058 3059unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3060 if (RetVT.SimpleTy != MVT::v8i16) 3061 return 0; 3062 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3063 return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3064 } 3065 return 0; 3066} 3067 3068unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3069 if (RetVT.SimpleTy != MVT::v4i32) 3070 return 0; 3071 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3072 return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3073 } 3074 return 0; 3075} 3076 3077unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3078 if (RetVT.SimpleTy != MVT::v2i64) 3079 return 0; 3080 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3081 return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3082 } 3083 return 0; 3084} 3085 3086unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3087 switch (VT.SimpleTy) { 3088 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3089 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3090 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3091 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3092 default: return 0; 3093 } 3094} 3095 3096// FastEmit functions for MipsISD::ILVR. 3097 3098unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3099 if (RetVT.SimpleTy != MVT::v16i8) 3100 return 0; 3101 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3102 return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3103 } 3104 return 0; 3105} 3106 3107unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3108 if (RetVT.SimpleTy != MVT::v8i16) 3109 return 0; 3110 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3111 return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3112 } 3113 return 0; 3114} 3115 3116unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3117 if (RetVT.SimpleTy != MVT::v4i32) 3118 return 0; 3119 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3120 return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3121 } 3122 return 0; 3123} 3124 3125unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3126 if (RetVT.SimpleTy != MVT::v2i64) 3127 return 0; 3128 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3129 return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3130 } 3131 return 0; 3132} 3133 3134unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3135 switch (VT.SimpleTy) { 3136 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3137 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3138 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3139 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3140 default: return 0; 3141 } 3142} 3143 3144// FastEmit functions for MipsISD::MTLOHI. 3145 3146unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3147 if (RetVT.SimpleTy != MVT::Untyped) 3148 return 0; 3149 if ((!Subtarget->inMips16Mode())) { 3150 return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3151 } 3152 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3153 return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3154 } 3155 return 0; 3156} 3157 3158unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3159 if (RetVT.SimpleTy != MVT::Untyped) 3160 return 0; 3161 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3162 return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3163 } 3164 return 0; 3165} 3166 3167unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3168 switch (VT.SimpleTy) { 3169 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3170 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3171 default: return 0; 3172 } 3173} 3174 3175// FastEmit functions for MipsISD::Mult. 3176 3177unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3178 if (RetVT.SimpleTy != MVT::Untyped) 3179 return 0; 3180 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) { 3181 return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3182 } 3183 if ((Subtarget->hasDSP())) { 3184 return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3185 } 3186 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3187 return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3188 } 3189 return 0; 3190} 3191 3192unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3193 if (RetVT.SimpleTy != MVT::Untyped) 3194 return 0; 3195 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3196 return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3197 } 3198 return 0; 3199} 3200 3201unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3202 switch (VT.SimpleTy) { 3203 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3204 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3205 default: return 0; 3206 } 3207} 3208 3209// FastEmit functions for MipsISD::Multu. 3210 3211unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3212 if (RetVT.SimpleTy != MVT::Untyped) 3213 return 0; 3214 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) { 3215 return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3216 } 3217 if ((Subtarget->hasDSP())) { 3218 return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3219 } 3220 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3221 return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3222 } 3223 return 0; 3224} 3225 3226unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3227 if (RetVT.SimpleTy != MVT::Untyped) 3228 return 0; 3229 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) { 3230 return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3231 } 3232 return 0; 3233} 3234 3235unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3236 switch (VT.SimpleTy) { 3237 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3238 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3239 default: return 0; 3240 } 3241} 3242 3243// FastEmit functions for MipsISD::PCKEV. 3244 3245unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3246 if (RetVT.SimpleTy != MVT::v16i8) 3247 return 0; 3248 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3249 return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3250 } 3251 return 0; 3252} 3253 3254unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3255 if (RetVT.SimpleTy != MVT::v8i16) 3256 return 0; 3257 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3258 return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3259 } 3260 return 0; 3261} 3262 3263unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3264 if (RetVT.SimpleTy != MVT::v4i32) 3265 return 0; 3266 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3267 return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3268 } 3269 return 0; 3270} 3271 3272unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3273 if (RetVT.SimpleTy != MVT::v2i64) 3274 return 0; 3275 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3276 return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3277 } 3278 return 0; 3279} 3280 3281unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3282 switch (VT.SimpleTy) { 3283 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3284 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3285 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3286 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3287 default: return 0; 3288 } 3289} 3290 3291// FastEmit functions for MipsISD::PCKOD. 3292 3293unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3294 if (RetVT.SimpleTy != MVT::v16i8) 3295 return 0; 3296 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3297 return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3298 } 3299 return 0; 3300} 3301 3302unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3303 if (RetVT.SimpleTy != MVT::v8i16) 3304 return 0; 3305 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3306 return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3307 } 3308 return 0; 3309} 3310 3311unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3312 if (RetVT.SimpleTy != MVT::v4i32) 3313 return 0; 3314 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3315 return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3316 } 3317 return 0; 3318} 3319 3320unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3321 if (RetVT.SimpleTy != MVT::v2i64) 3322 return 0; 3323 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3324 return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3325 } 3326 return 0; 3327} 3328 3329unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3330 switch (VT.SimpleTy) { 3331 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3332 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3333 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3334 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3335 default: return 0; 3336 } 3337} 3338 3339// FastEmit functions for MipsISD::VNOR. 3340 3341unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3342 if (RetVT.SimpleTy != MVT::v16i8) 3343 return 0; 3344 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3345 return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3346 } 3347 return 0; 3348} 3349 3350unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3351 if (RetVT.SimpleTy != MVT::v8i16) 3352 return 0; 3353 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3354 return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3355 } 3356 return 0; 3357} 3358 3359unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3360 if (RetVT.SimpleTy != MVT::v4i32) 3361 return 0; 3362 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3363 return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3364 } 3365 return 0; 3366} 3367 3368unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3369 if (RetVT.SimpleTy != MVT::v2i64) 3370 return 0; 3371 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3372 return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill); 3373 } 3374 return 0; 3375} 3376 3377unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { 3378 switch (VT.SimpleTy) { 3379 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3380 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3381 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3382 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3383 default: return 0; 3384 } 3385} 3386 3387// Top-level FastEmit function. 3388 3389unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override { 3390 switch (Opcode) { 3391 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3392 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3393 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3394 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3395 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3396 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3397 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3398 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3399 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3400 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3401 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3402 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3403 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3404 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3405 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3406 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3407 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3408 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3409 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3410 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3411 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3412 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3413 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3414 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3415 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3416 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3417 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3418 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3419 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3420 case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3421 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3422 case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3423 case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3424 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3425 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3426 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3427 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3428 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3429 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3430 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3431 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3432 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3433 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill); 3434 default: return 0; 3435 } 3436} 3437 3438// FastEmit functions for MipsISD::ExtractElementF64. 3439 3440unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3441 if (RetVT.SimpleTy != MVT::i32) 3442 return 0; 3443 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) { 3444 return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3445 } 3446 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) { 3447 return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3448 } 3449 return 0; 3450} 3451 3452unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3453 switch (VT.SimpleTy) { 3454 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1); 3455 default: return 0; 3456 } 3457} 3458 3459// FastEmit functions for MipsISD::SHLL_DSP. 3460 3461unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3462 if (RetVT.SimpleTy != MVT::v4i8) 3463 return 0; 3464 if ((Subtarget->hasDSP())) { 3465 return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3466 } 3467 return 0; 3468} 3469 3470unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3471 if (RetVT.SimpleTy != MVT::v2i16) 3472 return 0; 3473 if ((Subtarget->hasDSP())) { 3474 return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3475 } 3476 return 0; 3477} 3478 3479unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3480 switch (VT.SimpleTy) { 3481 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1); 3482 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1); 3483 default: return 0; 3484 } 3485} 3486 3487// FastEmit functions for MipsISD::SHRA_DSP. 3488 3489unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3490 if (RetVT.SimpleTy != MVT::v4i8) 3491 return 0; 3492 if ((Subtarget->hasDSPR2())) { 3493 return fastEmitInst_ri(Mips::SHRA_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3494 } 3495 return 0; 3496} 3497 3498unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3499 if (RetVT.SimpleTy != MVT::v2i16) 3500 return 0; 3501 if ((Subtarget->hasDSP())) { 3502 return fastEmitInst_ri(Mips::SHRA_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3503 } 3504 return 0; 3505} 3506 3507unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3508 switch (VT.SimpleTy) { 3509 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1); 3510 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1); 3511 default: return 0; 3512 } 3513} 3514 3515// FastEmit functions for MipsISD::SHRL_DSP. 3516 3517unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3518 if (RetVT.SimpleTy != MVT::v4i8) 3519 return 0; 3520 if ((Subtarget->hasDSP())) { 3521 return fastEmitInst_ri(Mips::SHRL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3522 } 3523 return 0; 3524} 3525 3526unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3527 if (RetVT.SimpleTy != MVT::v2i16) 3528 return 0; 3529 if ((Subtarget->hasDSPR2())) { 3530 return fastEmitInst_ri(Mips::SHRL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1); 3531 } 3532 return 0; 3533} 3534 3535unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3536 switch (VT.SimpleTy) { 3537 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1); 3538 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1); 3539 default: return 0; 3540 } 3541} 3542 3543// Top-level FastEmit function. 3544 3545unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override { 3546 if (VT == MVT::i32 && Predicate_immZExt5(imm1)) 3547 if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3548 return Reg; 3549 3550 if (VT == MVT::i32 && Predicate_immZExt6(imm1)) 3551 if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3552 return Reg; 3553 3554 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(imm1)) 3555 if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3556 return Reg; 3557 3558 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(imm1)) 3559 if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3560 return Reg; 3561 3562 if (VT == MVT::i32 && Predicate_immZExt4(imm1)) 3563 if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3564 return Reg; 3565 3566 if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1)) 3567 if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3568 return Reg; 3569 3570 if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1)) 3571 if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3572 return Reg; 3573 3574 if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1)) 3575 if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3576 return Reg; 3577 3578 if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1)) 3579 if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1)) 3580 return Reg; 3581 3582 switch (Opcode) { 3583 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3584 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3585 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3586 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1); 3587 default: return 0; 3588 } 3589} 3590 3591// FastEmit functions for ISD::ROTR. 3592 3593unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3594 if (RetVT.SimpleTy != MVT::i32) 3595 return 0; 3596 if ((Subtarget->inMicroMipsMode())) { 3597 return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3598 } 3599 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3600 return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3601 } 3602 return 0; 3603} 3604 3605unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3606 switch (VT.SimpleTy) { 3607 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1); 3608 default: return 0; 3609 } 3610} 3611 3612// FastEmit functions for ISD::SHL. 3613 3614unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3615 if (RetVT.SimpleTy != MVT::i32) 3616 return 0; 3617 if ((Subtarget->inMicroMipsMode())) { 3618 return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3619 } 3620 if ((Subtarget->inMips16Mode())) { 3621 return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1); 3622 } 3623 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3624 return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3625 } 3626 return 0; 3627} 3628 3629unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3630 switch (VT.SimpleTy) { 3631 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1); 3632 default: return 0; 3633 } 3634} 3635 3636// FastEmit functions for ISD::SRA. 3637 3638unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3639 if (RetVT.SimpleTy != MVT::i32) 3640 return 0; 3641 if ((Subtarget->inMicroMipsMode())) { 3642 return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3643 } 3644 if ((Subtarget->inMips16Mode())) { 3645 return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1); 3646 } 3647 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3648 return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3649 } 3650 return 0; 3651} 3652 3653unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3654 switch (VT.SimpleTy) { 3655 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1); 3656 default: return 0; 3657 } 3658} 3659 3660// FastEmit functions for ISD::SRL. 3661 3662unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3663 if (RetVT.SimpleTy != MVT::i32) 3664 return 0; 3665 if ((Subtarget->inMicroMipsMode())) { 3666 return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3667 } 3668 if ((Subtarget->inMips16Mode())) { 3669 return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1); 3670 } 3671 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3672 return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3673 } 3674 return 0; 3675} 3676 3677unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3678 switch (VT.SimpleTy) { 3679 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1); 3680 default: return 0; 3681 } 3682} 3683 3684// Top-level FastEmit function. 3685 3686unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3687 switch (Opcode) { 3688 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1); 3689 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1); 3690 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1); 3691 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1); 3692 default: return 0; 3693 } 3694} 3695 3696// FastEmit functions for ISD::ROTR. 3697 3698unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3699 if (RetVT.SimpleTy != MVT::i64) 3700 return 0; 3701 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3702 return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1); 3703 } 3704 return 0; 3705} 3706 3707unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3708 switch (VT.SimpleTy) { 3709 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1); 3710 default: return 0; 3711 } 3712} 3713 3714// FastEmit functions for ISD::SHL. 3715 3716unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3717 if (RetVT.SimpleTy != MVT::i64) 3718 return 0; 3719 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3720 return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1); 3721 } 3722 return 0; 3723} 3724 3725unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3726 switch (VT.SimpleTy) { 3727 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1); 3728 default: return 0; 3729 } 3730} 3731 3732// FastEmit functions for ISD::SRA. 3733 3734unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3735 if (RetVT.SimpleTy != MVT::i64) 3736 return 0; 3737 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3738 return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1); 3739 } 3740 return 0; 3741} 3742 3743unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3744 switch (VT.SimpleTy) { 3745 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1); 3746 default: return 0; 3747 } 3748} 3749 3750// FastEmit functions for ISD::SRL. 3751 3752unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3753 if (RetVT.SimpleTy != MVT::i64) 3754 return 0; 3755 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) { 3756 return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1); 3757 } 3758 return 0; 3759} 3760 3761unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3762 switch (VT.SimpleTy) { 3763 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1); 3764 default: return 0; 3765 } 3766} 3767 3768// Top-level FastEmit function. 3769 3770unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3771 switch (Opcode) { 3772 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1); 3773 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1); 3774 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1); 3775 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1); 3776 default: return 0; 3777 } 3778} 3779 3780// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 3781 3782unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3783 if (RetVT.SimpleTy != MVT::f32) 3784 return 0; 3785 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3786 return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1); 3787 } 3788 return 0; 3789} 3790 3791unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3792 switch (VT.SimpleTy) { 3793 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, Op0IsKill, imm1); 3794 default: return 0; 3795 } 3796} 3797 3798// Top-level FastEmit function. 3799 3800unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3801 switch (Opcode) { 3802 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, Op0IsKill, imm1); 3803 default: return 0; 3804 } 3805} 3806 3807// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 3808 3809unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3810 if (RetVT.SimpleTy != MVT::f64) 3811 return 0; 3812 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) { 3813 return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1); 3814 } 3815 return 0; 3816} 3817 3818unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3819 switch (VT.SimpleTy) { 3820 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, Op0IsKill, imm1); 3821 default: return 0; 3822 } 3823} 3824 3825// Top-level FastEmit function. 3826 3827unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3828 switch (Opcode) { 3829 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, Op0IsKill, imm1); 3830 default: return 0; 3831 } 3832} 3833 3834// FastEmit functions for ISD::EXTRACT_VECTOR_ELT. 3835 3836unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3837 if (RetVT.SimpleTy != MVT::i32) 3838 return 0; 3839 if ((Subtarget->hasMSA())) { 3840 return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3841 } 3842 return 0; 3843} 3844 3845unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3846 switch (VT.SimpleTy) { 3847 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, Op0IsKill, imm1); 3848 default: return 0; 3849 } 3850} 3851 3852// Top-level FastEmit function. 3853 3854unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3855 switch (Opcode) { 3856 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, Op0IsKill, imm1); 3857 default: return 0; 3858 } 3859} 3860 3861// FastEmit functions for ISD::ADD. 3862 3863unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3864 if (RetVT.SimpleTy != MVT::i32) 3865 return 0; 3866 if ((Subtarget->inMicroMipsMode())) { 3867 return fastEmitInst_ri(Mips::ADDIUR2_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3868 } 3869 return 0; 3870} 3871 3872unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3873 switch (VT.SimpleTy) { 3874 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, Op0IsKill, imm1); 3875 default: return 0; 3876 } 3877} 3878 3879// Top-level FastEmit function. 3880 3881unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3882 switch (Opcode) { 3883 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, Op0IsKill, imm1); 3884 default: return 0; 3885 } 3886} 3887 3888// FastEmit functions for ISD::ADD. 3889 3890unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3891 if (RetVT.SimpleTy != MVT::i32) 3892 return 0; 3893 if ((Subtarget->inMicroMipsMode())) { 3894 return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1); 3895 } 3896 return 0; 3897} 3898 3899unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3900 switch (VT.SimpleTy) { 3901 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, Op0IsKill, imm1); 3902 default: return 0; 3903 } 3904} 3905 3906// Top-level FastEmit function. 3907 3908unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3909 switch (Opcode) { 3910 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, Op0IsKill, imm1); 3911 default: return 0; 3912 } 3913} 3914 3915// FastEmit functions for ISD::AND. 3916 3917unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3918 if (RetVT.SimpleTy != MVT::i32) 3919 return 0; 3920 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) { 3921 return fastEmitInst_ri(Mips::ANDI16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3922 } 3923 if ((Subtarget->inMicroMipsMode())) { 3924 return fastEmitInst_ri(Mips::ANDI16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3925 } 3926 return 0; 3927} 3928 3929unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3930 switch (VT.SimpleTy) { 3931 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, Op0IsKill, imm1); 3932 default: return 0; 3933 } 3934} 3935 3936// Top-level FastEmit function. 3937 3938unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3939 switch (Opcode) { 3940 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1); 3941 default: return 0; 3942 } 3943} 3944 3945// FastEmit functions for ISD::SHL. 3946 3947unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3948 if (RetVT.SimpleTy != MVT::i32) 3949 return 0; 3950 if ((Subtarget->inMicroMipsMode())) { 3951 return fastEmitInst_ri(Mips::SLL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3952 } 3953 return 0; 3954} 3955 3956unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3957 switch (VT.SimpleTy) { 3958 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1); 3959 default: return 0; 3960 } 3961} 3962 3963// FastEmit functions for ISD::SRL. 3964 3965unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3966 if (RetVT.SimpleTy != MVT::i32) 3967 return 0; 3968 if ((Subtarget->inMicroMipsMode())) { 3969 return fastEmitInst_ri(Mips::SRL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1); 3970 } 3971 return 0; 3972} 3973 3974unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3975 switch (VT.SimpleTy) { 3976 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1); 3977 default: return 0; 3978 } 3979} 3980 3981// Top-level FastEmit function. 3982 3983unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) { 3984 switch (Opcode) { 3985 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1); 3986 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1); 3987 default: return 0; 3988 } 3989} 3990 3991// FastEmit functions for ISD::Constant. 3992 3993unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) { 3994 if (RetVT.SimpleTy != MVT::i32) 3995 return 0; 3996 if ((Subtarget->inMips16Mode())) { 3997 return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0); 3998 } 3999 return 0; 4000} 4001 4002unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) { 4003 switch (VT.SimpleTy) { 4004 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0); 4005 default: return 0; 4006 } 4007} 4008 4009// Top-level FastEmit function. 4010 4011unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override { 4012 switch (Opcode) { 4013 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0); 4014 default: return 0; 4015 } 4016} 4017 4018