1//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// These instruction format definitions are structured to match the 13// description in the RISC-V User-Level ISA specification as closely as 14// possible. For instance, the specification describes instructions with the 15// MSB (31st bit) on the left and the LSB (0th bit) on the right. This is 16// reflected in the order of parameters to each instruction class. 17// 18// One area of divergence is in the description of immediates. The 19// specification describes immediate encoding in terms of bit-slicing 20// operations on the logical value represented. The immediate argument to 21// these instruction formats instead represents the bit sequence that will be 22// inserted into the instruction. e.g. although JAL's immediate is logically 23// a 21-bit value (where the LSB is always zero), we describe it as an imm20 24// to match how it is encoded. 25// 26//===----------------------------------------------------------------------===// 27 28// Format specifies the encoding used by the instruction. This is used by 29// RISCVMCCodeEmitter to determine which form of fixup to use. These 30// definitions must be kept in-sync with RISCVBaseInfo.h. 31class InstFormat<bits<5> val> { 32 bits<5> Value = val; 33} 34def InstFormatPseudo : InstFormat<0>; 35def InstFormatR : InstFormat<1>; 36def InstFormatR4 : InstFormat<2>; 37def InstFormatI : InstFormat<3>; 38def InstFormatS : InstFormat<4>; 39def InstFormatB : InstFormat<5>; 40def InstFormatU : InstFormat<6>; 41def InstFormatJ : InstFormat<7>; 42def InstFormatCR : InstFormat<8>; 43def InstFormatCI : InstFormat<9>; 44def InstFormatCSS : InstFormat<10>; 45def InstFormatCIW : InstFormat<11>; 46def InstFormatCL : InstFormat<12>; 47def InstFormatCS : InstFormat<13>; 48def InstFormatCB : InstFormat<14>; 49def InstFormatCJ : InstFormat<15>; 50def InstFormatOther : InstFormat<16>; 51 52// The following opcode names and match those given in Table 19.1 in the 53// RISC-V User-level ISA specification ("RISC-V base opcode map"). 54class RISCVOpcode<bits<7> val> { 55 bits<7> Value = val; 56} 57def OPC_LOAD : RISCVOpcode<0b0000011>; 58def OPC_LOAD_FP : RISCVOpcode<0b0000111>; 59def OPC_MISC_MEM : RISCVOpcode<0b0001111>; 60def OPC_OP_IMM : RISCVOpcode<0b0010011>; 61def OPC_AUIPC : RISCVOpcode<0b0010111>; 62def OPC_OP_IMM_32 : RISCVOpcode<0b0011011>; 63def OPC_STORE : RISCVOpcode<0b0100011>; 64def OPC_STORE_FP : RISCVOpcode<0b0100111>; 65def OPC_AMO : RISCVOpcode<0b0101111>; 66def OPC_OP : RISCVOpcode<0b0110011>; 67def OPC_LUI : RISCVOpcode<0b0110111>; 68def OPC_OP_32 : RISCVOpcode<0b0111011>; 69def OPC_MADD : RISCVOpcode<0b1000011>; 70def OPC_MSUB : RISCVOpcode<0b1000111>; 71def OPC_NMSUB : RISCVOpcode<0b1001011>; 72def OPC_NMADD : RISCVOpcode<0b1001111>; 73def OPC_OP_FP : RISCVOpcode<0b1010011>; 74def OPC_BRANCH : RISCVOpcode<0b1100011>; 75def OPC_JALR : RISCVOpcode<0b1100111>; 76def OPC_JAL : RISCVOpcode<0b1101111>; 77def OPC_SYSTEM : RISCVOpcode<0b1110011>; 78 79class RVInst<dag outs, dag ins, string opcodestr, string argstr, 80 list<dag> pattern, InstFormat format> 81 : Instruction { 82 field bits<32> Inst; 83 // SoftFail is a field the disassembler can use to provide a way for 84 // instructions to not match without killing the whole decode process. It is 85 // mainly used for ARM, but Tablegen expects this field to exist or it fails 86 // to build the decode table. 87 field bits<32> SoftFail = 0; 88 let Size = 4; 89 90 bits<7> Opcode = 0; 91 92 let Inst{6-0} = Opcode; 93 94 let Namespace = "RISCV"; 95 96 dag OutOperandList = outs; 97 dag InOperandList = ins; 98 let AsmString = opcodestr # "\t" # argstr; 99 let Pattern = pattern; 100 101 let TSFlags{4-0} = format.Value; 102} 103 104// Pseudo instructions 105class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = ""> 106 : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> { 107 let isPseudo = 1; 108 let isCodeGenOnly = 1; 109} 110 111// Instruction formats are listed in the order they appear in the RISC-V 112// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4, 113// RVInstRAtomic) sorted alphabetically. 114 115class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs, 116 dag ins, string opcodestr, string argstr> 117 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 118 bits<5> rs2; 119 bits<5> rs1; 120 bits<5> rd; 121 122 let Inst{31-25} = funct7; 123 let Inst{24-20} = rs2; 124 let Inst{19-15} = rs1; 125 let Inst{14-12} = funct3; 126 let Inst{11-7} = rd; 127 let Opcode = opcode.Value; 128} 129 130class RVInstR4<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins, 131 string opcodestr, string argstr> 132 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> { 133 bits<5> rs3; 134 bits<5> rs2; 135 bits<5> rs1; 136 bits<3> funct3; 137 bits<5> rd; 138 139 let Inst{31-27} = rs3; 140 let Inst{26-25} = funct2; 141 let Inst{24-20} = rs2; 142 let Inst{19-15} = rs1; 143 let Inst{14-12} = funct3; 144 let Inst{11-7} = rd; 145 let Opcode = opcode.Value; 146} 147 148class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3, 149 RISCVOpcode opcode, dag outs, dag ins, string opcodestr, 150 string argstr> 151 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 152 bits<5> rs2; 153 bits<5> rs1; 154 bits<5> rd; 155 156 let Inst{31-27} = funct5; 157 let Inst{26} = aq; 158 let Inst{25} = rl; 159 let Inst{24-20} = rs2; 160 let Inst{19-15} = rs1; 161 let Inst{14-12} = funct3; 162 let Inst{11-7} = rd; 163 let Opcode = opcode.Value; 164} 165 166class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins, 167 string opcodestr, string argstr> 168 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { 169 bits<5> rs2; 170 bits<5> rs1; 171 bits<3> funct3; 172 bits<5> rd; 173 174 let Inst{31-25} = funct7; 175 let Inst{24-20} = rs2; 176 let Inst{19-15} = rs1; 177 let Inst{14-12} = funct3; 178 let Inst{11-7} = rd; 179 let Opcode = opcode.Value; 180} 181 182class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, 183 string opcodestr, string argstr> 184 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 185 bits<12> imm12; 186 bits<5> rs1; 187 bits<5> rd; 188 189 let Inst{31-20} = imm12; 190 let Inst{19-15} = rs1; 191 let Inst{14-12} = funct3; 192 let Inst{11-7} = rd; 193 let Opcode = opcode.Value; 194} 195 196class RVInstIShift<bit arithshift, bits<3> funct3, RISCVOpcode opcode, 197 dag outs, dag ins, string opcodestr, string argstr> 198 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 199 bits<6> shamt; 200 bits<5> rs1; 201 bits<5> rd; 202 203 let Inst{31} = 0; 204 let Inst{30} = arithshift; 205 let Inst{29-26} = 0; 206 let Inst{25-20} = shamt; 207 let Inst{19-15} = rs1; 208 let Inst{14-12} = funct3; 209 let Inst{11-7} = rd; 210 let Opcode = opcode.Value; 211} 212 213class RVInstIShiftW<bit arithshift, bits<3> funct3, RISCVOpcode opcode, 214 dag outs, dag ins, string opcodestr, string argstr> 215 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { 216 bits<5> shamt; 217 bits<5> rs1; 218 bits<5> rd; 219 220 let Inst{31} = 0; 221 let Inst{30} = arithshift; 222 let Inst{29-25} = 0; 223 let Inst{24-20} = shamt; 224 let Inst{19-15} = rs1; 225 let Inst{14-12} = funct3; 226 let Inst{11-7} = rd; 227 let Opcode = opcode.Value; 228} 229 230class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, 231 string opcodestr, string argstr> 232 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> { 233 bits<12> imm12; 234 bits<5> rs2; 235 bits<5> rs1; 236 237 let Inst{31-25} = imm12{11-5}; 238 let Inst{24-20} = rs2; 239 let Inst{19-15} = rs1; 240 let Inst{14-12} = funct3; 241 let Inst{11-7} = imm12{4-0}; 242 let Opcode = opcode.Value; 243} 244 245class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, 246 string opcodestr, string argstr> 247 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> { 248 bits<12> imm12; 249 bits<5> rs2; 250 bits<5> rs1; 251 252 let Inst{31} = imm12{11}; 253 let Inst{30-25} = imm12{9-4}; 254 let Inst{24-20} = rs2; 255 let Inst{19-15} = rs1; 256 let Inst{14-12} = funct3; 257 let Inst{11-8} = imm12{3-0}; 258 let Inst{7} = imm12{10}; 259 let Opcode = opcode.Value; 260} 261 262class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr, 263 string argstr> 264 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> { 265 bits<20> imm20; 266 bits<5> rd; 267 268 let Inst{31-12} = imm20; 269 let Inst{11-7} = rd; 270 let Opcode = opcode.Value; 271} 272 273class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr, 274 string argstr> 275 : RVInst<outs, ins, opcodestr, argstr, [], InstFormatJ> { 276 bits<20> imm20; 277 bits<5> rd; 278 279 let Inst{31} = imm20{19}; 280 let Inst{30-21} = imm20{9-0}; 281 let Inst{20} = imm20{10}; 282 let Inst{19-12} = imm20{18-11}; 283 let Inst{11-7} = rd; 284 let Opcode = opcode.Value; 285} 286