1 /*
2  * Copyright (C) 2014 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #include <math.h>
18 #include <string.h>
19 
20 #include "arch/arm64/asm_support_arm64.h"
21 #include "base/bit_utils.h"
22 #include "entrypoints/entrypoint_utils.h"
23 #include "entrypoints/jni/jni_entrypoints.h"
24 #include "entrypoints/math_entrypoints.h"
25 #include "entrypoints/quick/quick_alloc_entrypoints.h"
26 #include "entrypoints/quick/quick_default_externs.h"
27 #include "entrypoints/quick/quick_default_init_entrypoints.h"
28 #include "entrypoints/quick/quick_entrypoints.h"
29 #include "entrypoints/runtime_asm_entrypoints.h"
30 #include "interpreter/interpreter.h"
31 
32 namespace art {
33 
34 // Cast entrypoints.
35 extern "C" size_t artInstanceOfFromCode(mirror::Object* obj, mirror::Class* ref_class);
36 
37 // Read barrier entrypoints.
38 // art_quick_read_barrier_mark_regX uses an non-standard calling
39 // convention: it expects its input in register X and returns its
40 // result in that same register, and saves and restores all
41 // caller-save registers.
42 extern "C" mirror::Object* art_quick_read_barrier_mark_reg00(mirror::Object*);
43 extern "C" mirror::Object* art_quick_read_barrier_mark_reg01(mirror::Object*);
44 extern "C" mirror::Object* art_quick_read_barrier_mark_reg02(mirror::Object*);
45 extern "C" mirror::Object* art_quick_read_barrier_mark_reg03(mirror::Object*);
46 extern "C" mirror::Object* art_quick_read_barrier_mark_reg04(mirror::Object*);
47 extern "C" mirror::Object* art_quick_read_barrier_mark_reg05(mirror::Object*);
48 extern "C" mirror::Object* art_quick_read_barrier_mark_reg06(mirror::Object*);
49 extern "C" mirror::Object* art_quick_read_barrier_mark_reg07(mirror::Object*);
50 extern "C" mirror::Object* art_quick_read_barrier_mark_reg08(mirror::Object*);
51 extern "C" mirror::Object* art_quick_read_barrier_mark_reg09(mirror::Object*);
52 extern "C" mirror::Object* art_quick_read_barrier_mark_reg10(mirror::Object*);
53 extern "C" mirror::Object* art_quick_read_barrier_mark_reg11(mirror::Object*);
54 extern "C" mirror::Object* art_quick_read_barrier_mark_reg12(mirror::Object*);
55 extern "C" mirror::Object* art_quick_read_barrier_mark_reg12(mirror::Object*);
56 extern "C" mirror::Object* art_quick_read_barrier_mark_reg13(mirror::Object*);
57 extern "C" mirror::Object* art_quick_read_barrier_mark_reg14(mirror::Object*);
58 extern "C" mirror::Object* art_quick_read_barrier_mark_reg15(mirror::Object*);
59 extern "C" mirror::Object* art_quick_read_barrier_mark_reg16(mirror::Object*);
60 extern "C" mirror::Object* art_quick_read_barrier_mark_reg17(mirror::Object*);
61 extern "C" mirror::Object* art_quick_read_barrier_mark_reg18(mirror::Object*);
62 extern "C" mirror::Object* art_quick_read_barrier_mark_reg19(mirror::Object*);
63 extern "C" mirror::Object* art_quick_read_barrier_mark_reg20(mirror::Object*);
64 extern "C" mirror::Object* art_quick_read_barrier_mark_reg21(mirror::Object*);
65 extern "C" mirror::Object* art_quick_read_barrier_mark_reg22(mirror::Object*);
66 extern "C" mirror::Object* art_quick_read_barrier_mark_reg22(mirror::Object*);
67 extern "C" mirror::Object* art_quick_read_barrier_mark_reg23(mirror::Object*);
68 extern "C" mirror::Object* art_quick_read_barrier_mark_reg24(mirror::Object*);
69 extern "C" mirror::Object* art_quick_read_barrier_mark_reg25(mirror::Object*);
70 extern "C" mirror::Object* art_quick_read_barrier_mark_reg26(mirror::Object*);
71 extern "C" mirror::Object* art_quick_read_barrier_mark_reg27(mirror::Object*);
72 extern "C" mirror::Object* art_quick_read_barrier_mark_reg28(mirror::Object*);
73 extern "C" mirror::Object* art_quick_read_barrier_mark_reg29(mirror::Object*);
74 
75 extern "C" mirror::Object* art_quick_read_barrier_mark_introspection(mirror::Object*);
76 extern "C" mirror::Object* art_quick_read_barrier_mark_introspection_arrays(mirror::Object*);
77 extern "C" mirror::Object* art_quick_read_barrier_mark_introspection_gc_roots(mirror::Object*);
78 
UpdateReadBarrierEntrypoints(QuickEntryPoints * qpoints,bool is_active)79 void UpdateReadBarrierEntrypoints(QuickEntryPoints* qpoints, bool is_active) {
80   // ARM64 is the architecture with the largest number of core
81   // registers (32) that supports the read barrier configuration.
82   // Because registers 30 (LR) and 31 (SP/XZR) cannot be used to pass
83   // arguments, only define ReadBarrierMarkRegX entrypoints for the
84   // first 30 registers.  This limitation is not a problem on other
85   // supported architectures (ARM, x86 and x86-64) either, as they
86   // have less core registers (resp. 16, 8 and 16).  (We may have to
87   // revise that design choice if read barrier support is added for
88   // MIPS and/or MIPS64.)
89   qpoints->pReadBarrierMarkReg00 = is_active ? art_quick_read_barrier_mark_reg00 : nullptr;
90   qpoints->pReadBarrierMarkReg01 = is_active ? art_quick_read_barrier_mark_reg01 : nullptr;
91   qpoints->pReadBarrierMarkReg02 = is_active ? art_quick_read_barrier_mark_reg02 : nullptr;
92   qpoints->pReadBarrierMarkReg03 = is_active ? art_quick_read_barrier_mark_reg03 : nullptr;
93   qpoints->pReadBarrierMarkReg04 = is_active ? art_quick_read_barrier_mark_reg04 : nullptr;
94   qpoints->pReadBarrierMarkReg05 = is_active ? art_quick_read_barrier_mark_reg05 : nullptr;
95   qpoints->pReadBarrierMarkReg06 = is_active ? art_quick_read_barrier_mark_reg06 : nullptr;
96   qpoints->pReadBarrierMarkReg07 = is_active ? art_quick_read_barrier_mark_reg07 : nullptr;
97   qpoints->pReadBarrierMarkReg08 = is_active ? art_quick_read_barrier_mark_reg08 : nullptr;
98   qpoints->pReadBarrierMarkReg09 = is_active ? art_quick_read_barrier_mark_reg09 : nullptr;
99   qpoints->pReadBarrierMarkReg10 = is_active ? art_quick_read_barrier_mark_reg10 : nullptr;
100   qpoints->pReadBarrierMarkReg11 = is_active ? art_quick_read_barrier_mark_reg11 : nullptr;
101   qpoints->pReadBarrierMarkReg12 = is_active ? art_quick_read_barrier_mark_reg12 : nullptr;
102   qpoints->pReadBarrierMarkReg13 = is_active ? art_quick_read_barrier_mark_reg13 : nullptr;
103   qpoints->pReadBarrierMarkReg14 = is_active ? art_quick_read_barrier_mark_reg14 : nullptr;
104   qpoints->pReadBarrierMarkReg15 = is_active ? art_quick_read_barrier_mark_reg15 : nullptr;
105   qpoints->pReadBarrierMarkReg17 = is_active ? art_quick_read_barrier_mark_reg17 : nullptr;
106   qpoints->pReadBarrierMarkReg19 = is_active ? art_quick_read_barrier_mark_reg19 : nullptr;
107   qpoints->pReadBarrierMarkReg20 = is_active ? art_quick_read_barrier_mark_reg20 : nullptr;
108   qpoints->pReadBarrierMarkReg21 = is_active ? art_quick_read_barrier_mark_reg21 : nullptr;
109   qpoints->pReadBarrierMarkReg22 = is_active ? art_quick_read_barrier_mark_reg22 : nullptr;
110   qpoints->pReadBarrierMarkReg23 = is_active ? art_quick_read_barrier_mark_reg23 : nullptr;
111   qpoints->pReadBarrierMarkReg24 = is_active ? art_quick_read_barrier_mark_reg24 : nullptr;
112   qpoints->pReadBarrierMarkReg25 = is_active ? art_quick_read_barrier_mark_reg25 : nullptr;
113   qpoints->pReadBarrierMarkReg26 = is_active ? art_quick_read_barrier_mark_reg26 : nullptr;
114   qpoints->pReadBarrierMarkReg27 = is_active ? art_quick_read_barrier_mark_reg27 : nullptr;
115   qpoints->pReadBarrierMarkReg28 = is_active ? art_quick_read_barrier_mark_reg28 : nullptr;
116   qpoints->pReadBarrierMarkReg29 = is_active ? art_quick_read_barrier_mark_reg29 : nullptr;
117 
118   // Check that array switch cases are at appropriate offsets from the introspection entrypoint.
119   DCHECK_ALIGNED(art_quick_read_barrier_mark_introspection, 512u);
120   intptr_t array_diff =
121       reinterpret_cast<intptr_t>(art_quick_read_barrier_mark_introspection_arrays) -
122       reinterpret_cast<intptr_t>(art_quick_read_barrier_mark_introspection);
123   DCHECK_EQ(BAKER_MARK_INTROSPECTION_ARRAY_SWITCH_OFFSET, array_diff);
124   // Check that the GC root entrypoint is at appropriate offset from the introspection entrypoint.
125   intptr_t gc_roots_diff =
126       reinterpret_cast<intptr_t>(art_quick_read_barrier_mark_introspection_gc_roots) -
127       reinterpret_cast<intptr_t>(art_quick_read_barrier_mark_introspection);
128   DCHECK_EQ(BAKER_MARK_INTROSPECTION_GC_ROOT_ENTRYPOINT_OFFSET, gc_roots_diff);
129   // The register 16, i.e. IP0, is reserved, so there is no art_quick_read_barrier_mark_reg16.
130   // We're using the entry to hold a pointer to the introspection entrypoint instead.
131   qpoints->pReadBarrierMarkReg16 = is_active ? art_quick_read_barrier_mark_introspection : nullptr;
132 }
133 
InitEntryPoints(JniEntryPoints * jpoints,QuickEntryPoints * qpoints)134 void InitEntryPoints(JniEntryPoints* jpoints, QuickEntryPoints* qpoints) {
135   DefaultInitEntryPoints(jpoints, qpoints);
136 
137   // Cast
138   qpoints->pInstanceofNonTrivial = artInstanceOfFromCode;
139   qpoints->pCheckInstanceOf = art_quick_check_instance_of;
140 
141   // Math
142   // TODO null entrypoints not needed for ARM64 - generate inline.
143   qpoints->pCmpgDouble = nullptr;
144   qpoints->pCmpgFloat = nullptr;
145   qpoints->pCmplDouble = nullptr;
146   qpoints->pCmplFloat = nullptr;
147   qpoints->pFmod = fmod;
148   qpoints->pL2d = nullptr;
149   qpoints->pFmodf = fmodf;
150   qpoints->pL2f = nullptr;
151   qpoints->pD2iz = nullptr;
152   qpoints->pF2iz = nullptr;
153   qpoints->pIdivmod = nullptr;
154   qpoints->pD2l = nullptr;
155   qpoints->pF2l = nullptr;
156   qpoints->pLdiv = nullptr;
157   qpoints->pLmod = nullptr;
158   qpoints->pLmul = nullptr;
159   qpoints->pShlLong = nullptr;
160   qpoints->pShrLong = nullptr;
161   qpoints->pUshrLong = nullptr;
162 
163   // More math.
164   qpoints->pCos = cos;
165   qpoints->pSin = sin;
166   qpoints->pAcos = acos;
167   qpoints->pAsin = asin;
168   qpoints->pAtan = atan;
169   qpoints->pAtan2 = atan2;
170   qpoints->pPow = pow;
171   qpoints->pCbrt = cbrt;
172   qpoints->pCosh = cosh;
173   qpoints->pExp = exp;
174   qpoints->pExpm1 = expm1;
175   qpoints->pHypot = hypot;
176   qpoints->pLog = log;
177   qpoints->pLog10 = log10;
178   qpoints->pNextAfter = nextafter;
179   qpoints->pSinh = sinh;
180   qpoints->pTan = tan;
181   qpoints->pTanh = tanh;
182 
183   // Intrinsics
184   qpoints->pIndexOf = art_quick_indexof;
185   // The ARM64 StringCompareTo intrinsic does not call the runtime.
186   qpoints->pStringCompareTo = nullptr;
187   qpoints->pMemcpy = memcpy;
188 
189   // Read barrier.
190   qpoints->pReadBarrierJni = ReadBarrierJni;
191   qpoints->pReadBarrierMarkReg16 = nullptr;  // IP0 is used as a temp by the asm stub.
192   UpdateReadBarrierEntrypoints(qpoints, /*is_active=*/ false);
193   qpoints->pReadBarrierSlow = artReadBarrierSlow;
194   qpoints->pReadBarrierForRootSlow = artReadBarrierForRootSlow;
195 }
196 
197 }  // namespace art
198