1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 */
7
8 #include <common.h>
9 #include <asm/processor.h>
10
11 #include <asm/immap.h>
12 #include <asm/io.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 /*
17 * Low Power Divider specifications
18 */
19 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
20 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
21
22 #define CLOCK_PLL_FVCO_MAX 540000000
23 #define CLOCK_PLL_FVCO_MIN 300000000
24
25 #define CLOCK_PLL_FSYS_MAX 266666666
26 #define CLOCK_PLL_FSYS_MIN 100000000
27 #define MHZ 1000000
28
clock_enter_limp(int lpdiv)29 void clock_enter_limp(int lpdiv)
30 {
31 ccm_t *ccm = (ccm_t *)MMAP_CCM;
32 int i, j;
33
34 /* Check bounds of divider */
35 if (lpdiv < CLOCK_LPD_MIN)
36 lpdiv = CLOCK_LPD_MIN;
37 if (lpdiv > CLOCK_LPD_MAX)
38 lpdiv = CLOCK_LPD_MAX;
39
40 /* Round divider down to nearest power of two */
41 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
42
43 /* Apply the divider to the system clock */
44 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
45
46 /* Enable Limp Mode */
47 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
48 }
49
50 /*
51 * brief Exit Limp mode
52 * warning The PLL should be set and locked prior to exiting Limp mode
53 */
clock_exit_limp(void)54 void clock_exit_limp(void)
55 {
56 ccm_t *ccm = (ccm_t *)MMAP_CCM;
57 pll_t *pll = (pll_t *)MMAP_PLL;
58
59 /* Exit Limp mode */
60 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
61
62 /* Wait for the PLL to lock */
63 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
64 ;
65 }
66
67 /*
68 * get_clocks() fills in gd->cpu_clock and gd->bus_clk
69 */
get_clocks(void)70 int get_clocks(void)
71 {
72
73 ccm_t *ccm = (ccm_t *)MMAP_CCM;
74 pll_t *pll = (pll_t *)MMAP_PLL;
75 int vco, temp, pcrvalue, pfdr;
76 u8 bootmode;
77
78 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
79 pfdr = pcrvalue >> 24;
80
81 if (pfdr == 0x1E)
82 bootmode = 0; /* Normal Mode */
83
84 #ifdef CONFIG_CF_SBF
85 bootmode = 3; /* Serial Mode */
86 #endif
87
88 if (bootmode == 0) {
89 /* Normal mode */
90 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
91 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
92 /* Default value */
93 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
94 pcrvalue |= 0x1E << 24;
95 out_be32(&pll->pcr, pcrvalue);
96 vco =
97 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
98 CONFIG_SYS_INPUT_CLKSRC;
99 }
100 gd->arch.vco_clk = vco; /* Vco clock */
101 } else if (bootmode == 3) {
102 /* serial mode */
103 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
104 gd->arch.vco_clk = vco; /* Vco clock */
105 }
106
107 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
108 /* Limp mode */
109 } else {
110 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
111
112 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
113 gd->cpu_clk = vco / temp; /* cpu clock */
114
115 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
116 gd->arch.flb_clk = vco / temp; /* flexbus clock */
117 gd->bus_clk = gd->arch.flb_clk;
118 }
119
120 #ifdef CONFIG_SYS_I2C_FSL
121 gd->arch.i2c1_clk = gd->bus_clk;
122 #endif
123
124 return (0);
125 }
126