1 /*
2  * Copyright (C) 2011 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
18 #define ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
19 
20 #include <vector>
21 
22 #include "base/arena_containers.h"
23 #include "base/array_ref.h"
24 #include "base/bit_utils.h"
25 #include "base/enums.h"
26 #include "base/globals.h"
27 #include "base/macros.h"
28 #include "constants_x86.h"
29 #include "heap_poisoning.h"
30 #include "managed_register_x86.h"
31 #include "offsets.h"
32 #include "utils/assembler.h"
33 
34 namespace art {
35 namespace x86 {
36 
37 class Immediate : public ValueObject {
38  public:
Immediate(int32_t value_in)39   explicit Immediate(int32_t value_in) : value_(value_in) {}
40 
value()41   int32_t value() const { return value_; }
42 
is_int8()43   bool is_int8() const { return IsInt<8>(value_); }
is_uint8()44   bool is_uint8() const { return IsUint<8>(value_); }
is_int16()45   bool is_int16() const { return IsInt<16>(value_); }
is_uint16()46   bool is_uint16() const { return IsUint<16>(value_); }
47 
48  private:
49   const int32_t value_;
50 };
51 
52 
53 class Operand : public ValueObject {
54  public:
mod()55   uint8_t mod() const {
56     return (encoding_at(0) >> 6) & 3;
57   }
58 
rm()59   Register rm() const {
60     return static_cast<Register>(encoding_at(0) & 7);
61   }
62 
scale()63   ScaleFactor scale() const {
64     return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
65   }
66 
index()67   Register index() const {
68     return static_cast<Register>((encoding_at(1) >> 3) & 7);
69   }
70 
base()71   Register base() const {
72     return static_cast<Register>(encoding_at(1) & 7);
73   }
74 
disp8()75   int8_t disp8() const {
76     CHECK_GE(length_, 2);
77     return static_cast<int8_t>(encoding_[length_ - 1]);
78   }
79 
disp32()80   int32_t disp32() const {
81     CHECK_GE(length_, 5);
82     int32_t value;
83     memcpy(&value, &encoding_[length_ - 4], sizeof(value));
84     return value;
85   }
86 
IsRegister(Register reg)87   bool IsRegister(Register reg) const {
88     return ((encoding_[0] & 0xF8) == 0xC0)  // Addressing mode is register only.
89         && ((encoding_[0] & 0x07) == reg);  // Register codes match.
90   }
91 
92  protected:
93   // Operand can be sub classed (e.g: Address).
Operand()94   Operand() : length_(0), fixup_(nullptr) { }
95 
SetModRM(int mod_in,Register rm_in)96   void SetModRM(int mod_in, Register rm_in) {
97     CHECK_EQ(mod_in & ~3, 0);
98     encoding_[0] = (mod_in << 6) | rm_in;
99     length_ = 1;
100   }
101 
SetSIB(ScaleFactor scale_in,Register index_in,Register base_in)102   void SetSIB(ScaleFactor scale_in, Register index_in, Register base_in) {
103     CHECK_EQ(length_, 1);
104     CHECK_EQ(scale_in & ~3, 0);
105     encoding_[1] = (scale_in << 6) | (index_in << 3) | base_in;
106     length_ = 2;
107   }
108 
SetDisp8(int8_t disp)109   void SetDisp8(int8_t disp) {
110     CHECK(length_ == 1 || length_ == 2);
111     encoding_[length_++] = static_cast<uint8_t>(disp);
112   }
113 
SetDisp32(int32_t disp)114   void SetDisp32(int32_t disp) {
115     CHECK(length_ == 1 || length_ == 2);
116     int disp_size = sizeof(disp);
117     memmove(&encoding_[length_], &disp, disp_size);
118     length_ += disp_size;
119   }
120 
GetFixup()121   AssemblerFixup* GetFixup() const {
122     return fixup_;
123   }
124 
SetFixup(AssemblerFixup * fixup)125   void SetFixup(AssemblerFixup* fixup) {
126     fixup_ = fixup;
127   }
128 
129  private:
130   uint8_t length_;
131   uint8_t encoding_[6];
132 
133   // A fixup can be associated with the operand, in order to be applied after the
134   // code has been generated. This is used for constant area fixups.
135   AssemblerFixup* fixup_;
136 
Operand(Register reg)137   explicit Operand(Register reg) : fixup_(nullptr) { SetModRM(3, reg); }
138 
139   // Get the operand encoding byte at the given index.
encoding_at(int index_in)140   uint8_t encoding_at(int index_in) const {
141     CHECK_GE(index_in, 0);
142     CHECK_LT(index_in, length_);
143     return encoding_[index_in];
144   }
145 
146   friend class X86Assembler;
147 };
148 
149 
150 class Address : public Operand {
151  public:
Address(Register base_in,int32_t disp)152   Address(Register base_in, int32_t disp) {
153     Init(base_in, disp);
154   }
155 
Address(Register base_in,int32_t disp,AssemblerFixup * fixup)156   Address(Register base_in, int32_t disp, AssemblerFixup *fixup) {
157     Init(base_in, disp);
158     SetFixup(fixup);
159   }
160 
Address(Register base_in,Offset disp)161   Address(Register base_in, Offset disp) {
162     Init(base_in, disp.Int32Value());
163   }
164 
Address(Register base_in,FrameOffset disp)165   Address(Register base_in, FrameOffset disp) {
166     CHECK_EQ(base_in, ESP);
167     Init(ESP, disp.Int32Value());
168   }
169 
Address(Register base_in,MemberOffset disp)170   Address(Register base_in, MemberOffset disp) {
171     Init(base_in, disp.Int32Value());
172   }
173 
Address(Register index_in,ScaleFactor scale_in,int32_t disp)174   Address(Register index_in, ScaleFactor scale_in, int32_t disp) {
175     CHECK_NE(index_in, ESP);  // Illegal addressing mode.
176     SetModRM(0, ESP);
177     SetSIB(scale_in, index_in, EBP);
178     SetDisp32(disp);
179   }
180 
Address(Register base_in,Register index_in,ScaleFactor scale_in,int32_t disp)181   Address(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) {
182     Init(base_in, index_in, scale_in, disp);
183   }
184 
Address(Register base_in,Register index_in,ScaleFactor scale_in,int32_t disp,AssemblerFixup * fixup)185   Address(Register base_in,
186           Register index_in,
187           ScaleFactor scale_in,
188           int32_t disp, AssemblerFixup *fixup) {
189     Init(base_in, index_in, scale_in, disp);
190     SetFixup(fixup);
191   }
192 
Absolute(uintptr_t addr)193   static Address Absolute(uintptr_t addr) {
194     Address result;
195     result.SetModRM(0, EBP);
196     result.SetDisp32(addr);
197     return result;
198   }
199 
Absolute(ThreadOffset32 addr)200   static Address Absolute(ThreadOffset32 addr) {
201     return Absolute(addr.Int32Value());
202   }
203 
204  private:
Address()205   Address() {}
206 
Init(Register base_in,int32_t disp)207   void Init(Register base_in, int32_t disp) {
208     if (disp == 0 && base_in != EBP) {
209       SetModRM(0, base_in);
210       if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
211     } else if (disp >= -128 && disp <= 127) {
212       SetModRM(1, base_in);
213       if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
214       SetDisp8(disp);
215     } else {
216       SetModRM(2, base_in);
217       if (base_in == ESP) SetSIB(TIMES_1, ESP, base_in);
218       SetDisp32(disp);
219     }
220   }
221 
Init(Register base_in,Register index_in,ScaleFactor scale_in,int32_t disp)222   void Init(Register base_in, Register index_in, ScaleFactor scale_in, int32_t disp) {
223     CHECK_NE(index_in, ESP);  // Illegal addressing mode.
224     if (disp == 0 && base_in != EBP) {
225       SetModRM(0, ESP);
226       SetSIB(scale_in, index_in, base_in);
227     } else if (disp >= -128 && disp <= 127) {
228       SetModRM(1, ESP);
229       SetSIB(scale_in, index_in, base_in);
230       SetDisp8(disp);
231     } else {
232       SetModRM(2, ESP);
233       SetSIB(scale_in, index_in, base_in);
234       SetDisp32(disp);
235     }
236   }
237 };
238 
239 std::ostream& operator<<(std::ostream& os, const Address& addr);
240 
241 // This is equivalent to the Label class, used in a slightly different context. We
242 // inherit the functionality of the Label class, but prevent unintended
243 // derived-to-base conversions by making the base class private.
244 class NearLabel : private Label {
245  public:
NearLabel()246   NearLabel() : Label() {}
247 
248   // Expose the Label routines that we need.
249   using Label::Position;
250   using Label::LinkPosition;
251   using Label::IsBound;
252   using Label::IsUnused;
253   using Label::IsLinked;
254 
255  private:
256   using Label::BindTo;
257   using Label::LinkTo;
258 
259   friend class x86::X86Assembler;
260 
261   DISALLOW_COPY_AND_ASSIGN(NearLabel);
262 };
263 
264 /**
265  * Class to handle constant area values.
266  */
267 class ConstantArea {
268  public:
ConstantArea(ArenaAllocator * allocator)269   explicit ConstantArea(ArenaAllocator* allocator)
270       : buffer_(allocator->Adapter(kArenaAllocAssembler)) {}
271 
272   // Add a double to the constant area, returning the offset into
273   // the constant area where the literal resides.
274   size_t AddDouble(double v);
275 
276   // Add a float to the constant area, returning the offset into
277   // the constant area where the literal resides.
278   size_t AddFloat(float v);
279 
280   // Add an int32_t to the constant area, returning the offset into
281   // the constant area where the literal resides.
282   size_t AddInt32(int32_t v);
283 
284   // Add an int32_t to the end of the constant area, returning the offset into
285   // the constant area where the literal resides.
286   size_t AppendInt32(int32_t v);
287 
288   // Add an int64_t to the constant area, returning the offset into
289   // the constant area where the literal resides.
290   size_t AddInt64(int64_t v);
291 
IsEmpty()292   bool IsEmpty() const {
293     return buffer_.size() == 0;
294   }
295 
GetSize()296   size_t GetSize() const {
297     return buffer_.size() * elem_size_;
298   }
299 
GetBuffer()300   ArrayRef<const int32_t> GetBuffer() const {
301     return ArrayRef<const int32_t>(buffer_);
302   }
303 
304  private:
305   static constexpr size_t elem_size_ = sizeof(int32_t);
306   ArenaVector<int32_t> buffer_;
307 };
308 
309 class X86Assembler final : public Assembler {
310  public:
X86Assembler(ArenaAllocator * allocator)311   explicit X86Assembler(ArenaAllocator* allocator)
312       : Assembler(allocator), constant_area_(allocator) {}
~X86Assembler()313   virtual ~X86Assembler() {}
314 
315   /*
316    * Emit Machine Instructions.
317    */
318   void call(Register reg);
319   void call(const Address& address);
320   void call(Label* label);
321   void call(const ExternalLabel& label);
322 
323   void pushl(Register reg);
324   void pushl(const Address& address);
325   void pushl(const Immediate& imm);
326 
327   void popl(Register reg);
328   void popl(const Address& address);
329 
330   void movl(Register dst, const Immediate& src);
331   void movl(Register dst, Register src);
332 
333   void movl(Register dst, const Address& src);
334   void movl(const Address& dst, Register src);
335   void movl(const Address& dst, const Immediate& imm);
336   void movl(const Address& dst, Label* lbl);
337 
338   void movntl(const Address& dst, Register src);
339 
340   void blsi(Register dst, Register src);  // no addr variant (for now)
341   void blsmsk(Register dst, Register src);  // no addr variant (for now)
342   void blsr(Register dst, Register src);  // no addr varianr (for now)
343 
344   void bswapl(Register dst);
345 
346   void bsfl(Register dst, Register src);
347   void bsfl(Register dst, const Address& src);
348   void bsrl(Register dst, Register src);
349   void bsrl(Register dst, const Address& src);
350 
351   void popcntl(Register dst, Register src);
352   void popcntl(Register dst, const Address& src);
353 
354   void rorl(Register reg, const Immediate& imm);
355   void rorl(Register operand, Register shifter);
356   void roll(Register reg, const Immediate& imm);
357   void roll(Register operand, Register shifter);
358 
359   void movzxb(Register dst, ByteRegister src);
360   void movzxb(Register dst, const Address& src);
361   void movsxb(Register dst, ByteRegister src);
362   void movsxb(Register dst, const Address& src);
363   void movb(Register dst, const Address& src);
364   void movb(const Address& dst, ByteRegister src);
365   void movb(const Address& dst, const Immediate& imm);
366 
367   void movzxw(Register dst, Register src);
368   void movzxw(Register dst, const Address& src);
369   void movsxw(Register dst, Register src);
370   void movsxw(Register dst, const Address& src);
371   void movw(Register dst, const Address& src);
372   void movw(const Address& dst, Register src);
373   void movw(const Address& dst, const Immediate& imm);
374 
375   void leal(Register dst, const Address& src);
376 
377   void cmovl(Condition condition, Register dst, Register src);
378   void cmovl(Condition condition, Register dst, const Address& src);
379 
380   void setb(Condition condition, Register dst);
381 
382   void movaps(XmmRegister dst, XmmRegister src);     // move
383   void movaps(XmmRegister dst, const Address& src);  // load aligned
384   void movups(XmmRegister dst, const Address& src);  // load unaligned
385   void movaps(const Address& dst, XmmRegister src);  // store aligned
386   void movups(const Address& dst, XmmRegister src);  // store unaligned
387 
388   void movss(XmmRegister dst, const Address& src);
389   void movss(const Address& dst, XmmRegister src);
390   void movss(XmmRegister dst, XmmRegister src);
391 
392   void movd(XmmRegister dst, Register src);
393   void movd(Register dst, XmmRegister src);
394 
395   void addss(XmmRegister dst, XmmRegister src);
396   void addss(XmmRegister dst, const Address& src);
397   void subss(XmmRegister dst, XmmRegister src);
398   void subss(XmmRegister dst, const Address& src);
399   void mulss(XmmRegister dst, XmmRegister src);
400   void mulss(XmmRegister dst, const Address& src);
401   void divss(XmmRegister dst, XmmRegister src);
402   void divss(XmmRegister dst, const Address& src);
403 
404   void addps(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
405   void subps(XmmRegister dst, XmmRegister src);
406   void mulps(XmmRegister dst, XmmRegister src);
407   void divps(XmmRegister dst, XmmRegister src);
408 
409   void movapd(XmmRegister dst, XmmRegister src);     // move
410   void movapd(XmmRegister dst, const Address& src);  // load aligned
411   void movupd(XmmRegister dst, const Address& src);  // load unaligned
412   void movapd(const Address& dst, XmmRegister src);  // store aligned
413   void movupd(const Address& dst, XmmRegister src);  // store unaligned
414 
415   void movsd(XmmRegister dst, const Address& src);
416   void movsd(const Address& dst, XmmRegister src);
417   void movsd(XmmRegister dst, XmmRegister src);
418 
419   void movhpd(XmmRegister dst, const Address& src);
420   void movhpd(const Address& dst, XmmRegister src);
421 
422   void addsd(XmmRegister dst, XmmRegister src);
423   void addsd(XmmRegister dst, const Address& src);
424   void subsd(XmmRegister dst, XmmRegister src);
425   void subsd(XmmRegister dst, const Address& src);
426   void mulsd(XmmRegister dst, XmmRegister src);
427   void mulsd(XmmRegister dst, const Address& src);
428   void divsd(XmmRegister dst, XmmRegister src);
429   void divsd(XmmRegister dst, const Address& src);
430 
431   void addpd(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
432   void subpd(XmmRegister dst, XmmRegister src);
433   void mulpd(XmmRegister dst, XmmRegister src);
434   void divpd(XmmRegister dst, XmmRegister src);
435 
436   void movdqa(XmmRegister dst, XmmRegister src);     // move
437   void movdqa(XmmRegister dst, const Address& src);  // load aligned
438   void movdqu(XmmRegister dst, const Address& src);  // load unaligned
439   void movdqa(const Address& dst, XmmRegister src);  // store aligned
440   void movdqu(const Address& dst, XmmRegister src);  // store unaligned
441 
442   void paddb(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
443   void psubb(XmmRegister dst, XmmRegister src);
444 
445   void paddw(XmmRegister dst, XmmRegister src);
446   void psubw(XmmRegister dst, XmmRegister src);
447   void pmullw(XmmRegister dst, XmmRegister src);
448 
449   void paddd(XmmRegister dst, XmmRegister src);
450   void psubd(XmmRegister dst, XmmRegister src);
451   void pmulld(XmmRegister dst, XmmRegister src);
452 
453   void paddq(XmmRegister dst, XmmRegister src);
454   void psubq(XmmRegister dst, XmmRegister src);
455 
456   void paddusb(XmmRegister dst, XmmRegister src);
457   void paddsb(XmmRegister dst, XmmRegister src);
458   void paddusw(XmmRegister dst, XmmRegister src);
459   void paddsw(XmmRegister dst, XmmRegister src);
460   void psubusb(XmmRegister dst, XmmRegister src);
461   void psubsb(XmmRegister dst, XmmRegister src);
462   void psubusw(XmmRegister dst, XmmRegister src);
463   void psubsw(XmmRegister dst, XmmRegister src);
464 
465   void cvtsi2ss(XmmRegister dst, Register src);
466   void cvtsi2sd(XmmRegister dst, Register src);
467 
468   void cvtss2si(Register dst, XmmRegister src);
469   void cvtss2sd(XmmRegister dst, XmmRegister src);
470 
471   void cvtsd2si(Register dst, XmmRegister src);
472   void cvtsd2ss(XmmRegister dst, XmmRegister src);
473 
474   void cvttss2si(Register dst, XmmRegister src);
475   void cvttsd2si(Register dst, XmmRegister src);
476 
477   void cvtdq2ps(XmmRegister dst, XmmRegister src);
478   void cvtdq2pd(XmmRegister dst, XmmRegister src);
479 
480   void comiss(XmmRegister a, XmmRegister b);
481   void comiss(XmmRegister a, const Address& b);
482   void comisd(XmmRegister a, XmmRegister b);
483   void comisd(XmmRegister a, const Address& b);
484   void ucomiss(XmmRegister a, XmmRegister b);
485   void ucomiss(XmmRegister a, const Address& b);
486   void ucomisd(XmmRegister a, XmmRegister b);
487   void ucomisd(XmmRegister a, const Address& b);
488 
489   void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm);
490   void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm);
491 
492   void sqrtsd(XmmRegister dst, XmmRegister src);
493   void sqrtss(XmmRegister dst, XmmRegister src);
494 
495   void xorpd(XmmRegister dst, const Address& src);
496   void xorpd(XmmRegister dst, XmmRegister src);
497   void xorps(XmmRegister dst, const Address& src);
498   void xorps(XmmRegister dst, XmmRegister src);
499   void pxor(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
500 
501   void andpd(XmmRegister dst, XmmRegister src);
502   void andpd(XmmRegister dst, const Address& src);
503   void andps(XmmRegister dst, XmmRegister src);
504   void andps(XmmRegister dst, const Address& src);
505   void pand(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
506 
507   void andn(Register dst, Register src1, Register src2);  // no addr variant (for now)
508   void andnpd(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
509   void andnps(XmmRegister dst, XmmRegister src);
510   void pandn(XmmRegister dst, XmmRegister src);
511 
512   void orpd(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
513   void orps(XmmRegister dst, XmmRegister src);
514   void por(XmmRegister dst, XmmRegister src);
515 
516   void pavgb(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
517   void pavgw(XmmRegister dst, XmmRegister src);
518   void psadbw(XmmRegister dst, XmmRegister src);
519   void pmaddwd(XmmRegister dst, XmmRegister src);
520   void phaddw(XmmRegister dst, XmmRegister src);
521   void phaddd(XmmRegister dst, XmmRegister src);
522   void haddps(XmmRegister dst, XmmRegister src);
523   void haddpd(XmmRegister dst, XmmRegister src);
524   void phsubw(XmmRegister dst, XmmRegister src);
525   void phsubd(XmmRegister dst, XmmRegister src);
526   void hsubps(XmmRegister dst, XmmRegister src);
527   void hsubpd(XmmRegister dst, XmmRegister src);
528 
529   void pminsb(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
530   void pmaxsb(XmmRegister dst, XmmRegister src);
531   void pminsw(XmmRegister dst, XmmRegister src);
532   void pmaxsw(XmmRegister dst, XmmRegister src);
533   void pminsd(XmmRegister dst, XmmRegister src);
534   void pmaxsd(XmmRegister dst, XmmRegister src);
535 
536   void pminub(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
537   void pmaxub(XmmRegister dst, XmmRegister src);
538   void pminuw(XmmRegister dst, XmmRegister src);
539   void pmaxuw(XmmRegister dst, XmmRegister src);
540   void pminud(XmmRegister dst, XmmRegister src);
541   void pmaxud(XmmRegister dst, XmmRegister src);
542 
543   void minps(XmmRegister dst, XmmRegister src);  // no addr variant (for now)
544   void maxps(XmmRegister dst, XmmRegister src);
545   void minpd(XmmRegister dst, XmmRegister src);
546   void maxpd(XmmRegister dst, XmmRegister src);
547 
548   void pcmpeqb(XmmRegister dst, XmmRegister src);
549   void pcmpeqw(XmmRegister dst, XmmRegister src);
550   void pcmpeqd(XmmRegister dst, XmmRegister src);
551   void pcmpeqq(XmmRegister dst, XmmRegister src);
552 
553   void pcmpgtb(XmmRegister dst, XmmRegister src);
554   void pcmpgtw(XmmRegister dst, XmmRegister src);
555   void pcmpgtd(XmmRegister dst, XmmRegister src);
556   void pcmpgtq(XmmRegister dst, XmmRegister src);  // SSE4.2
557 
558   void shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm);
559   void shufps(XmmRegister dst, XmmRegister src, const Immediate& imm);
560   void pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm);
561 
562   void punpcklbw(XmmRegister dst, XmmRegister src);
563   void punpcklwd(XmmRegister dst, XmmRegister src);
564   void punpckldq(XmmRegister dst, XmmRegister src);
565   void punpcklqdq(XmmRegister dst, XmmRegister src);
566 
567   void punpckhbw(XmmRegister dst, XmmRegister src);
568   void punpckhwd(XmmRegister dst, XmmRegister src);
569   void punpckhdq(XmmRegister dst, XmmRegister src);
570   void punpckhqdq(XmmRegister dst, XmmRegister src);
571 
572   void psllw(XmmRegister reg, const Immediate& shift_count);
573   void pslld(XmmRegister reg, const Immediate& shift_count);
574   void psllq(XmmRegister reg, const Immediate& shift_count);
575 
576   void psraw(XmmRegister reg, const Immediate& shift_count);
577   void psrad(XmmRegister reg, const Immediate& shift_count);
578   // no psraq
579 
580   void psrlw(XmmRegister reg, const Immediate& shift_count);
581   void psrld(XmmRegister reg, const Immediate& shift_count);
582   void psrlq(XmmRegister reg, const Immediate& shift_count);
583   void psrldq(XmmRegister reg, const Immediate& shift_count);
584 
585   void flds(const Address& src);
586   void fstps(const Address& dst);
587   void fsts(const Address& dst);
588 
589   void fldl(const Address& src);
590   void fstpl(const Address& dst);
591   void fstl(const Address& dst);
592 
593   void fstsw();
594 
595   void fucompp();
596 
597   void fnstcw(const Address& dst);
598   void fldcw(const Address& src);
599 
600   void fistpl(const Address& dst);
601   void fistps(const Address& dst);
602   void fildl(const Address& src);
603   void filds(const Address& src);
604 
605   void fincstp();
606   void ffree(const Immediate& index);
607 
608   void fsin();
609   void fcos();
610   void fptan();
611   void fprem();
612 
613   void xchgl(Register dst, Register src);
614   void xchgl(Register reg, const Address& address);
615 
616   void cmpb(const Address& address, const Immediate& imm);
617   void cmpw(const Address& address, const Immediate& imm);
618 
619   void cmpl(Register reg, const Immediate& imm);
620   void cmpl(Register reg0, Register reg1);
621   void cmpl(Register reg, const Address& address);
622 
623   void cmpl(const Address& address, Register reg);
624   void cmpl(const Address& address, const Immediate& imm);
625 
626   void testl(Register reg1, Register reg2);
627   void testl(Register reg, const Immediate& imm);
628   void testl(Register reg1, const Address& address);
629 
630   void testb(const Address& dst, const Immediate& imm);
631   void testl(const Address& dst, const Immediate& imm);
632 
633   void andl(Register dst, const Immediate& imm);
634   void andl(Register dst, Register src);
635   void andl(Register dst, const Address& address);
636 
637   void orl(Register dst, const Immediate& imm);
638   void orl(Register dst, Register src);
639   void orl(Register dst, const Address& address);
640 
641   void xorl(Register dst, Register src);
642   void xorl(Register dst, const Immediate& imm);
643   void xorl(Register dst, const Address& address);
644 
645   void addl(Register dst, Register src);
646   void addl(Register reg, const Immediate& imm);
647   void addl(Register reg, const Address& address);
648 
649   void addl(const Address& address, Register reg);
650   void addl(const Address& address, const Immediate& imm);
651   void addw(const Address& address, const Immediate& imm);
652 
653   void adcl(Register dst, Register src);
654   void adcl(Register reg, const Immediate& imm);
655   void adcl(Register dst, const Address& address);
656 
657   void subl(Register dst, Register src);
658   void subl(Register reg, const Immediate& imm);
659   void subl(Register reg, const Address& address);
660   void subl(const Address& address, Register src);
661 
662   void cdq();
663 
664   void idivl(Register reg);
665 
666   void imull(Register dst, Register src);
667   void imull(Register reg, const Immediate& imm);
668   void imull(Register dst, Register src, const Immediate& imm);
669   void imull(Register reg, const Address& address);
670 
671   void imull(Register reg);
672   void imull(const Address& address);
673 
674   void mull(Register reg);
675   void mull(const Address& address);
676 
677   void sbbl(Register dst, Register src);
678   void sbbl(Register reg, const Immediate& imm);
679   void sbbl(Register reg, const Address& address);
680   void sbbl(const Address& address, Register src);
681 
682   void incl(Register reg);
683   void incl(const Address& address);
684 
685   void decl(Register reg);
686   void decl(const Address& address);
687 
688   void shll(Register reg, const Immediate& imm);
689   void shll(Register operand, Register shifter);
690   void shll(const Address& address, const Immediate& imm);
691   void shll(const Address& address, Register shifter);
692   void shrl(Register reg, const Immediate& imm);
693   void shrl(Register operand, Register shifter);
694   void shrl(const Address& address, const Immediate& imm);
695   void shrl(const Address& address, Register shifter);
696   void sarl(Register reg, const Immediate& imm);
697   void sarl(Register operand, Register shifter);
698   void sarl(const Address& address, const Immediate& imm);
699   void sarl(const Address& address, Register shifter);
700   void shld(Register dst, Register src, Register shifter);
701   void shld(Register dst, Register src, const Immediate& imm);
702   void shrd(Register dst, Register src, Register shifter);
703   void shrd(Register dst, Register src, const Immediate& imm);
704 
705   void negl(Register reg);
706   void notl(Register reg);
707 
708   void enter(const Immediate& imm);
709   void leave();
710 
711   void ret();
712   void ret(const Immediate& imm);
713 
714   void nop();
715   void int3();
716   void hlt();
717 
718   void j(Condition condition, Label* label);
719   void j(Condition condition, NearLabel* label);
720   void jecxz(NearLabel* label);
721 
722   void jmp(Register reg);
723   void jmp(const Address& address);
724   void jmp(Label* label);
725   void jmp(NearLabel* label);
726 
727   void repne_scasb();
728   void repne_scasw();
729   void repe_cmpsb();
730   void repe_cmpsw();
731   void repe_cmpsl();
732   void rep_movsb();
733   void rep_movsw();
734 
735   X86Assembler* lock();
736   void cmpxchgl(const Address& address, Register reg);
737   void cmpxchg8b(const Address& address);
738 
739   void mfence();
740 
741   X86Assembler* fs();
742   X86Assembler* gs();
743 
744   //
745   // Macros for High-level operations.
746   //
747 
748   void AddImmediate(Register reg, const Immediate& imm);
749 
750   void LoadLongConstant(XmmRegister dst, int64_t value);
751   void LoadDoubleConstant(XmmRegister dst, double value);
752 
LockCmpxchgl(const Address & address,Register reg)753   void LockCmpxchgl(const Address& address, Register reg) {
754     lock()->cmpxchgl(address, reg);
755   }
756 
LockCmpxchg8b(const Address & address)757   void LockCmpxchg8b(const Address& address) {
758     lock()->cmpxchg8b(address);
759   }
760 
761   //
762   // Misc. functionality
763   //
PreferredLoopAlignment()764   int PreferredLoopAlignment() { return 16; }
765   void Align(int alignment, int offset);
766   void Bind(Label* label) override;
Jump(Label * label)767   void Jump(Label* label) override {
768     jmp(label);
769   }
770   void Bind(NearLabel* label);
771 
772   //
773   // Heap poisoning.
774   //
775 
776   // Poison a heap reference contained in `reg`.
PoisonHeapReference(Register reg)777   void PoisonHeapReference(Register reg) { negl(reg); }
778   // Unpoison a heap reference contained in `reg`.
UnpoisonHeapReference(Register reg)779   void UnpoisonHeapReference(Register reg) { negl(reg); }
780   // Poison a heap reference contained in `reg` if heap poisoning is enabled.
MaybePoisonHeapReference(Register reg)781   void MaybePoisonHeapReference(Register reg) {
782     if (kPoisonHeapReferences) {
783       PoisonHeapReference(reg);
784     }
785   }
786   // Unpoison a heap reference contained in `reg` if heap poisoning is enabled.
MaybeUnpoisonHeapReference(Register reg)787   void MaybeUnpoisonHeapReference(Register reg) {
788     if (kPoisonHeapReferences) {
789       UnpoisonHeapReference(reg);
790     }
791   }
792 
793   // Add a double to the constant area, returning the offset into
794   // the constant area where the literal resides.
AddDouble(double v)795   size_t AddDouble(double v) { return constant_area_.AddDouble(v); }
796 
797   // Add a float to the constant area, returning the offset into
798   // the constant area where the literal resides.
AddFloat(float v)799   size_t AddFloat(float v)   { return constant_area_.AddFloat(v); }
800 
801   // Add an int32_t to the constant area, returning the offset into
802   // the constant area where the literal resides.
AddInt32(int32_t v)803   size_t AddInt32(int32_t v) {
804     return constant_area_.AddInt32(v);
805   }
806 
807   // Add an int32_t to the end of the constant area, returning the offset into
808   // the constant area where the literal resides.
AppendInt32(int32_t v)809   size_t AppendInt32(int32_t v) {
810     return constant_area_.AppendInt32(v);
811   }
812 
813   // Add an int64_t to the constant area, returning the offset into
814   // the constant area where the literal resides.
AddInt64(int64_t v)815   size_t AddInt64(int64_t v) { return constant_area_.AddInt64(v); }
816 
817   // Add the contents of the constant area to the assembler buffer.
818   void AddConstantArea();
819 
820   // Is the constant area empty? Return true if there are no literals in the constant area.
IsConstantAreaEmpty()821   bool IsConstantAreaEmpty() const { return constant_area_.IsEmpty(); }
822 
823   // Return the current size of the constant area.
ConstantAreaSize()824   size_t ConstantAreaSize() const { return constant_area_.GetSize(); }
825 
826  private:
827   inline void EmitUint8(uint8_t value);
828   inline void EmitInt32(int32_t value);
829   inline void EmitRegisterOperand(int rm, int reg);
830   inline void EmitXmmRegisterOperand(int rm, XmmRegister reg);
831   inline void EmitFixup(AssemblerFixup* fixup);
832   inline void EmitOperandSizeOverride();
833 
834   void EmitOperand(int rm, const Operand& operand);
835   void EmitImmediate(const Immediate& imm, bool is_16_op = false);
836   void EmitComplex(
837       int rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
838   void EmitLabel(Label* label, int instruction_size);
839   void EmitLabelLink(Label* label);
840   void EmitLabelLink(NearLabel* label);
841 
842   void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm);
843   void EmitGenericShift(int rm, const Operand& operand, Register shifter);
844 
845   // Emit a 3 byte VEX Prefix
846   uint8_t EmitVexByteZero(bool is_two_byte);
847   uint8_t EmitVexByte1(bool r, bool x, bool b, int mmmmm);
848   uint8_t EmitVexByte2(bool w , int l , X86ManagedRegister operand, int pp);
849 
850   ConstantArea constant_area_;
851 
852   DISALLOW_COPY_AND_ASSIGN(X86Assembler);
853 };
854 
EmitUint8(uint8_t value)855 inline void X86Assembler::EmitUint8(uint8_t value) {
856   buffer_.Emit<uint8_t>(value);
857 }
858 
EmitInt32(int32_t value)859 inline void X86Assembler::EmitInt32(int32_t value) {
860   buffer_.Emit<int32_t>(value);
861 }
862 
EmitRegisterOperand(int rm,int reg)863 inline void X86Assembler::EmitRegisterOperand(int rm, int reg) {
864   CHECK_GE(rm, 0);
865   CHECK_LT(rm, 8);
866   buffer_.Emit<uint8_t>(0xC0 + (rm << 3) + reg);
867 }
868 
EmitXmmRegisterOperand(int rm,XmmRegister reg)869 inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) {
870   EmitRegisterOperand(rm, static_cast<Register>(reg));
871 }
872 
EmitFixup(AssemblerFixup * fixup)873 inline void X86Assembler::EmitFixup(AssemblerFixup* fixup) {
874   buffer_.EmitFixup(fixup);
875 }
876 
EmitOperandSizeOverride()877 inline void X86Assembler::EmitOperandSizeOverride() {
878   EmitUint8(0x66);
879 }
880 
881 }  // namespace x86
882 }  // namespace art
883 
884 #endif  // ART_COMPILER_UTILS_X86_ASSEMBLER_X86_H_
885