1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
4 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 *
6 * This file is based on: drivers/i2c/zynq_i2c.c,
7 * with added driver-model support and code cleanup.
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <linux/types.h>
13 #include <linux/io.h>
14 #include <linux/errno.h>
15 #include <dm/root.h>
16 #include <i2c.h>
17 #include <fdtdec.h>
18 #include <mapmem.h>
19 #include <wait_bit.h>
20
21 /* i2c register set */
22 struct cdns_i2c_regs {
23 u32 control;
24 u32 status;
25 u32 address;
26 u32 data;
27 u32 interrupt_status;
28 u32 transfer_size;
29 u32 slave_mon_pause;
30 u32 time_out;
31 u32 interrupt_mask;
32 u32 interrupt_enable;
33 u32 interrupt_disable;
34 };
35
36 /* Control register fields */
37 #define CDNS_I2C_CONTROL_RW 0x00000001
38 #define CDNS_I2C_CONTROL_MS 0x00000002
39 #define CDNS_I2C_CONTROL_NEA 0x00000004
40 #define CDNS_I2C_CONTROL_ACKEN 0x00000008
41 #define CDNS_I2C_CONTROL_HOLD 0x00000010
42 #define CDNS_I2C_CONTROL_SLVMON 0x00000020
43 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
44 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
45 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
46 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
47 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
48
49 /* Status register values */
50 #define CDNS_I2C_STATUS_RXDV 0x00000020
51 #define CDNS_I2C_STATUS_TXDV 0x00000040
52 #define CDNS_I2C_STATUS_RXOVF 0x00000080
53 #define CDNS_I2C_STATUS_BA 0x00000100
54
55 /* Interrupt register fields */
56 #define CDNS_I2C_INTERRUPT_COMP 0x00000001
57 #define CDNS_I2C_INTERRUPT_DATA 0x00000002
58 #define CDNS_I2C_INTERRUPT_NACK 0x00000004
59 #define CDNS_I2C_INTERRUPT_TO 0x00000008
60 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
61 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
62 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
63 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
64 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
65
66 #define CDNS_I2C_FIFO_DEPTH 16
67 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
68 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
69
70 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
71
72 #ifdef DEBUG
cdns_i2c_debug_status(struct cdns_i2c_regs * cdns_i2c)73 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
74 {
75 int int_status;
76 int status;
77 int_status = readl(&cdns_i2c->interrupt_status);
78
79 status = readl(&cdns_i2c->status);
80 if (int_status || status) {
81 debug("Status: ");
82 if (int_status & CDNS_I2C_INTERRUPT_COMP)
83 debug("COMP ");
84 if (int_status & CDNS_I2C_INTERRUPT_DATA)
85 debug("DATA ");
86 if (int_status & CDNS_I2C_INTERRUPT_NACK)
87 debug("NACK ");
88 if (int_status & CDNS_I2C_INTERRUPT_TO)
89 debug("TO ");
90 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
91 debug("SLVRDY ");
92 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
93 debug("RXOVF ");
94 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
95 debug("TXOVF ");
96 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
97 debug("RXUNF ");
98 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
99 debug("ARBLOST ");
100 if (status & CDNS_I2C_STATUS_RXDV)
101 debug("RXDV ");
102 if (status & CDNS_I2C_STATUS_TXDV)
103 debug("TXDV ");
104 if (status & CDNS_I2C_STATUS_RXOVF)
105 debug("RXOVF ");
106 if (status & CDNS_I2C_STATUS_BA)
107 debug("BA ");
108 debug("TS%d ", readl(&cdns_i2c->transfer_size));
109 debug("\n");
110 }
111 }
112 #endif
113
114 struct i2c_cdns_bus {
115 int id;
116 unsigned int input_freq;
117 struct cdns_i2c_regs __iomem *regs; /* register base */
118
119 int hold_flag;
120 u32 quirks;
121 };
122
123 struct cdns_i2c_platform_data {
124 u32 quirks;
125 };
126
127 /* Wait for an interrupt */
cdns_i2c_wait(struct cdns_i2c_regs * cdns_i2c,u32 mask)128 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
129 {
130 int timeout, int_status;
131
132 for (timeout = 0; timeout < 100; timeout++) {
133 int_status = readl(&cdns_i2c->interrupt_status);
134 if (int_status & mask)
135 break;
136 udelay(100);
137 }
138
139 /* Clear interrupt status flags */
140 writel(int_status & mask, &cdns_i2c->interrupt_status);
141
142 return int_status & mask;
143 }
144
145 #define CDNS_I2C_DIVA_MAX 4
146 #define CDNS_I2C_DIVB_MAX 64
147
cdns_i2c_calc_divs(unsigned long * f,unsigned long input_clk,unsigned int * a,unsigned int * b)148 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
149 unsigned int *a, unsigned int *b)
150 {
151 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
152 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
153 unsigned int last_error, current_error;
154
155 /* calculate (divisor_a+1) x (divisor_b+1) */
156 temp = input_clk / (22 * fscl);
157
158 /*
159 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
160 * the fscl input is out of range. Return error.
161 */
162 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
163 return -EINVAL;
164
165 last_error = -1;
166 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
167 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
168
169 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
170 continue;
171 div_b--;
172
173 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
174
175 if (actual_fscl > fscl)
176 continue;
177
178 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
179 (fscl - actual_fscl));
180
181 if (last_error > current_error) {
182 calc_div_a = div_a;
183 calc_div_b = div_b;
184 best_fscl = actual_fscl;
185 last_error = current_error;
186 }
187 }
188
189 *a = calc_div_a;
190 *b = calc_div_b;
191 *f = best_fscl;
192
193 return 0;
194 }
195
cdns_i2c_set_bus_speed(struct udevice * dev,unsigned int speed)196 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
197 {
198 struct i2c_cdns_bus *bus = dev_get_priv(dev);
199 u32 div_a = 0, div_b = 0;
200 unsigned long speed_p = speed;
201 int ret = 0;
202
203 if (speed > 400000) {
204 debug("%s, failed to set clock speed to %u\n", __func__,
205 speed);
206 return -EINVAL;
207 }
208
209 ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
210 if (ret)
211 return ret;
212
213 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
214 __func__, div_a, div_b, bus->input_freq, speed, speed_p);
215
216 writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
217 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
218
219 /* Enable master mode, ack, and 7-bit addressing */
220 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
221 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
222
223 return 0;
224 }
225
cdns_i2c_write_data(struct i2c_cdns_bus * i2c_bus,u32 addr,u8 * data,u32 len)226 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
227 u32 len)
228 {
229 u8 *cur_data = data;
230 struct cdns_i2c_regs *regs = i2c_bus->regs;
231
232 /* Set the controller in Master transmit mode and clear FIFO */
233 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
234 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
235
236 /* Check message size against FIFO depth, and set hold bus bit
237 * if it is greater than FIFO depth
238 */
239 if (len > CDNS_I2C_FIFO_DEPTH)
240 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
241
242 /* Clear the interrupts in status register */
243 writel(0xFF, ®s->interrupt_status);
244
245 writel(addr, ®s->address);
246
247 while (len--) {
248 writel(*(cur_data++), ®s->data);
249 if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
250 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
251 /* Release the bus */
252 clrbits_le32(®s->control,
253 CDNS_I2C_CONTROL_HOLD);
254 return -ETIMEDOUT;
255 }
256 }
257 }
258
259 /* All done... release the bus */
260 if (!i2c_bus->hold_flag)
261 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
262
263 /* Wait for the address and data to be sent */
264 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
265 return -ETIMEDOUT;
266 return 0;
267 }
268
cdns_is_hold_quirk(int hold_quirk,int curr_recv_count)269 static inline bool cdns_is_hold_quirk(int hold_quirk, int curr_recv_count)
270 {
271 return hold_quirk && (curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1);
272 }
273
cdns_i2c_read_data(struct i2c_cdns_bus * i2c_bus,u32 addr,u8 * data,u32 recv_count)274 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
275 u32 recv_count)
276 {
277 u8 *cur_data = data;
278 struct cdns_i2c_regs *regs = i2c_bus->regs;
279 int curr_recv_count;
280 int updatetx, hold_quirk;
281
282 /* Check the hardware can handle the requested bytes */
283 if ((recv_count < 0))
284 return -EINVAL;
285
286 curr_recv_count = recv_count;
287
288 /* Check for the message size against the FIFO depth */
289 if (recv_count > CDNS_I2C_FIFO_DEPTH)
290 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
291
292 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
293 CDNS_I2C_CONTROL_RW);
294
295 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
296 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
297 writel(curr_recv_count, ®s->transfer_size);
298 } else {
299 writel(recv_count, ®s->transfer_size);
300 }
301
302 /* Start reading data */
303 writel(addr, ®s->address);
304
305 updatetx = recv_count > curr_recv_count;
306
307 hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
308
309 while (recv_count) {
310 while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
311 if (recv_count < CDNS_I2C_FIFO_DEPTH &&
312 !i2c_bus->hold_flag) {
313 clrbits_le32(®s->control,
314 CDNS_I2C_CONTROL_HOLD);
315 }
316 *(cur_data)++ = readl(®s->data);
317 recv_count--;
318 curr_recv_count--;
319
320 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count))
321 break;
322 }
323
324 if (cdns_is_hold_quirk(hold_quirk, curr_recv_count)) {
325 /* wait while fifo is full */
326 while (readl(®s->transfer_size) !=
327 (curr_recv_count - CDNS_I2C_FIFO_DEPTH))
328 ;
329 /*
330 * Check number of bytes to be received against maximum
331 * transfer size and update register accordingly.
332 */
333 if ((recv_count - CDNS_I2C_FIFO_DEPTH) >
334 CDNS_I2C_TRANSFER_SIZE) {
335 writel(CDNS_I2C_TRANSFER_SIZE,
336 ®s->transfer_size);
337 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
338 CDNS_I2C_FIFO_DEPTH;
339 } else {
340 writel(recv_count - CDNS_I2C_FIFO_DEPTH,
341 ®s->transfer_size);
342 curr_recv_count = recv_count;
343 }
344 } else if (recv_count && !hold_quirk && !curr_recv_count) {
345 writel(addr, ®s->address);
346 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
347 writel(CDNS_I2C_TRANSFER_SIZE,
348 ®s->transfer_size);
349 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
350 } else {
351 writel(recv_count, ®s->transfer_size);
352 curr_recv_count = recv_count;
353 }
354 }
355 }
356
357 /* Wait for the address and data to be sent */
358 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
359 return -ETIMEDOUT;
360
361 return 0;
362 }
363
cdns_i2c_xfer(struct udevice * dev,struct i2c_msg * msg,int nmsgs)364 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
365 int nmsgs)
366 {
367 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
368 int ret, count;
369 bool hold_quirk;
370
371 hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
372
373 if (nmsgs > 1) {
374 /*
375 * This controller does not give completion interrupt after a
376 * master receive message if HOLD bit is set (repeated start),
377 * resulting in SW timeout. Hence, if a receive message is
378 * followed by any other message, an error is returned
379 * indicating that this sequence is not supported.
380 */
381 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
382 if (msg[count].flags & I2C_M_RD) {
383 printf("Can't do repeated start after a receive message\n");
384 return -EOPNOTSUPP;
385 }
386 }
387
388 i2c_bus->hold_flag = 1;
389 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
390 } else {
391 i2c_bus->hold_flag = 0;
392 }
393
394 debug("i2c_xfer: %d messages\n", nmsgs);
395 for (; nmsgs > 0; nmsgs--, msg++) {
396 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
397 if (msg->flags & I2C_M_RD) {
398 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
399 msg->len);
400 } else {
401 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
402 msg->len);
403 }
404 if (ret) {
405 debug("i2c_write: error sending\n");
406 return -EREMOTEIO;
407 }
408 }
409
410 return 0;
411 }
412
cdns_i2c_ofdata_to_platdata(struct udevice * dev)413 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
414 {
415 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
416 struct cdns_i2c_platform_data *pdata =
417 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
418
419 i2c_bus->regs = (struct cdns_i2c_regs *)devfdt_get_addr(dev);
420 if (!i2c_bus->regs)
421 return -ENOMEM;
422
423 if (pdata)
424 i2c_bus->quirks = pdata->quirks;
425
426 i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
427
428 return 0;
429 }
430
431 static const struct dm_i2c_ops cdns_i2c_ops = {
432 .xfer = cdns_i2c_xfer,
433 .set_bus_speed = cdns_i2c_set_bus_speed,
434 };
435
436 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
437 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
438 };
439
440 static const struct udevice_id cdns_i2c_of_match[] = {
441 { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
442 { .compatible = "cdns,i2c-r1p14" },
443 { /* end of table */ }
444 };
445
446 U_BOOT_DRIVER(cdns_i2c) = {
447 .name = "i2c-cdns",
448 .id = UCLASS_I2C,
449 .of_match = cdns_i2c_of_match,
450 .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
451 .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
452 .ops = &cdns_i2c_ops,
453 };
454