1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file declares the API of helper functions used throughout the
11 /// GlobalISel pipeline.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
17 
18 #include "llvm/ADT/StringRef.h"
19 
20 namespace llvm {
21 
22 class AnalysisUsage;
23 class MachineFunction;
24 class MachineInstr;
25 class MachineOperand;
26 class MachineOptimizationRemarkEmitter;
27 class MachineOptimizationRemarkMissed;
28 class MachineRegisterInfo;
29 class MCInstrDesc;
30 class RegisterBankInfo;
31 class TargetInstrInfo;
32 class TargetPassConfig;
33 class TargetRegisterInfo;
34 class TargetRegisterClass;
35 class Twine;
36 class ConstantFP;
37 class APFloat;
38 
39 /// Try to constrain Reg to the specified register class. If this fails,
40 /// create a new virtual register in the correct class and insert a COPY before
41 /// \p InsertPt. The debug location of \p InsertPt is used for the new copy.
42 ///
43 /// \return The virtual register constrained to the right register class.
44 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
45                              const TargetInstrInfo &TII,
46                              const RegisterBankInfo &RBI,
47                              MachineInstr &InsertPt, unsigned Reg,
48                              const TargetRegisterClass &RegClass);
49 
50 /// Try to constrain Reg so that it is usable by argument OpIdx of the
51 /// provided MCInstrDesc \p II. If this fails, create a new virtual
52 /// register in the correct class and insert a COPY before \p InsertPt.
53 /// This is equivalent to constrainRegToClass() with RegClass obtained from the
54 /// MCInstrDesc. The debug location of \p InsertPt is used for the new copy.
55 ///
56 /// \return The virtual register constrained to the right register class.
57 unsigned constrainOperandRegClass(const MachineFunction &MF,
58                                   const TargetRegisterInfo &TRI,
59                                   MachineRegisterInfo &MRI,
60                                   const TargetInstrInfo &TII,
61                                   const RegisterBankInfo &RBI,
62                                   MachineInstr &InsertPt, const MCInstrDesc &II,
63                                   const MachineOperand &RegMO, unsigned OpIdx);
64 
65 /// Mutate the newly-selected instruction \p I to constrain its (possibly
66 /// generic) virtual register operands to the instruction's register class.
67 /// This could involve inserting COPYs before (for uses) or after (for defs).
68 /// This requires the number of operands to match the instruction description.
69 /// \returns whether operand regclass constraining succeeded.
70 ///
71 // FIXME: Not all instructions have the same number of operands. We should
72 // probably expose a constrain helper per operand and let the target selector
73 // constrain individual registers, like fast-isel.
74 bool constrainSelectedInstRegOperands(MachineInstr &I,
75                                       const TargetInstrInfo &TII,
76                                       const TargetRegisterInfo &TRI,
77                                       const RegisterBankInfo &RBI);
78 /// Check whether an instruction \p MI is dead: it only defines dead virtual
79 /// registers, and doesn't have other side effects.
80 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
81 
82 /// Report an ISel error as a missed optimization remark to the LLVMContext's
83 /// diagnostic stream.  Set the FailedISel MachineFunction property.
84 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
85                         MachineOptimizationRemarkEmitter &MORE,
86                         MachineOptimizationRemarkMissed &R);
87 
88 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
89                         MachineOptimizationRemarkEmitter &MORE,
90                         const char *PassName, StringRef Msg,
91                         const MachineInstr &MI);
92 
93 Optional<int64_t> getConstantVRegVal(unsigned VReg,
94                                      const MachineRegisterInfo &MRI);
95 const ConstantFP* getConstantFPVRegVal(unsigned VReg,
96                                        const MachineRegisterInfo &MRI);
97 
98 /// See if Reg is defined by an single def instruction that is
99 /// Opcode. Also try to do trivial folding if it's a COPY with
100 /// same types. Returns null otherwise.
101 MachineInstr *getOpcodeDef(unsigned Opcode, unsigned Reg,
102                            const MachineRegisterInfo &MRI);
103 
104 /// Returns an APFloat from Val converted to the appropriate size.
105 APFloat getAPFloatFromSize(double Val, unsigned Size);
106 
107 /// Modify analysis usage so it preserves passes required for the SelectionDAG
108 /// fallback.
109 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
110 
111 } // End namespace llvm.
112 #endif
113