1 //===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the subtarget options of a Target machine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
15 #define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/PBQPRAConstraint.h"
21 #include "llvm/CodeGen/ScheduleDAGMutation.h"
22 #include "llvm/CodeGen/SchedulerRegistry.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/CodeGen.h"
25 #include <memory>
26 #include <vector>
27 
28 
29 namespace llvm {
30 
31 class CallLowering;
32 class InstrItineraryData;
33 struct InstrStage;
34 class InstructionSelector;
35 class LegalizerInfo;
36 class MachineInstr;
37 struct MachineSchedPolicy;
38 struct MCReadAdvanceEntry;
39 struct MCWriteLatencyEntry;
40 struct MCWriteProcResEntry;
41 class RegisterBankInfo;
42 class SDep;
43 class SelectionDAGTargetInfo;
44 struct SubtargetFeatureKV;
45 struct SubtargetInfoKV;
46 class SUnit;
47 class TargetFrameLowering;
48 class TargetInstrInfo;
49 class TargetLowering;
50 class TargetRegisterClass;
51 class TargetRegisterInfo;
52 class TargetSchedModel;
53 class Triple;
54 
55 //===----------------------------------------------------------------------===//
56 ///
57 /// TargetSubtargetInfo - Generic base class for all target subtargets.  All
58 /// Target-specific options that control code generation and printing should
59 /// be exposed through a TargetSubtargetInfo-derived class.
60 ///
61 class TargetSubtargetInfo : public MCSubtargetInfo {
62 protected: // Can only create subclasses...
63   TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
64                       ArrayRef<SubtargetFeatureKV> PF,
65                       ArrayRef<SubtargetFeatureKV> PD,
66                       const SubtargetInfoKV *ProcSched,
67                       const MCWriteProcResEntry *WPR,
68                       const MCWriteLatencyEntry *WL,
69                       const MCReadAdvanceEntry *RA, const InstrStage *IS,
70                       const unsigned *OC, const unsigned *FP);
71 
72 public:
73   // AntiDepBreakMode - Type of anti-dependence breaking that should
74   // be performed before post-RA scheduling.
75   using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
76   using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
77 
78   TargetSubtargetInfo() = delete;
79   TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
80   TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
81   ~TargetSubtargetInfo() override;
82 
isXRaySupported()83   virtual bool isXRaySupported() const { return false; }
84 
85   // Interfaces to the major aspects of target machine information:
86   //
87   // -- Instruction opcode and operand information
88   // -- Pipelines and scheduling information
89   // -- Stack frame information
90   // -- Selection DAG lowering information
91   // -- Call lowering information
92   //
93   // N.B. These objects may change during compilation. It's not safe to cache
94   // them between functions.
getInstrInfo()95   virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
getFrameLowering()96   virtual const TargetFrameLowering *getFrameLowering() const {
97     return nullptr;
98   }
getTargetLowering()99   virtual const TargetLowering *getTargetLowering() const { return nullptr; }
getSelectionDAGInfo()100   virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const {
101     return nullptr;
102   }
getCallLowering()103   virtual const CallLowering *getCallLowering() const { return nullptr; }
104 
105   // FIXME: This lets targets specialize the selector by subtarget (which lets
106   // us do things like a dedicated avx512 selector).  However, we might want
107   // to also specialize selectors by MachineFunction, which would let us be
108   // aware of optsize/optnone and such.
getInstructionSelector()109   virtual const InstructionSelector *getInstructionSelector() const {
110     return nullptr;
111   }
112 
getHwMode()113   virtual unsigned getHwMode() const { return 0; }
114 
115   /// Target can subclass this hook to select a different DAG scheduler.
116   virtual RegisterScheduler::FunctionPassCtor
getDAGScheduler(CodeGenOpt::Level)117       getDAGScheduler(CodeGenOpt::Level) const {
118     return nullptr;
119   }
120 
getLegalizerInfo()121   virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
122 
123   /// getRegisterInfo - If register information is available, return it.  If
124   /// not, return null.
getRegisterInfo()125   virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
126 
127   /// If the information for the register banks is available, return it.
128   /// Otherwise return nullptr.
getRegBankInfo()129   virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
130 
131   /// getInstrItineraryData - Returns instruction itinerary data for the target
132   /// or specific subtarget.
getInstrItineraryData()133   virtual const InstrItineraryData *getInstrItineraryData() const {
134     return nullptr;
135   }
136 
137   /// Resolve a SchedClass at runtime, where SchedClass identifies an
138   /// MCSchedClassDesc with the isVariant property. This may return the ID of
139   /// another variant SchedClass, but repeated invocation must quickly terminate
140   /// in a nonvariant SchedClass.
resolveSchedClass(unsigned SchedClass,const MachineInstr * MI,const TargetSchedModel * SchedModel)141   virtual unsigned resolveSchedClass(unsigned SchedClass,
142                                      const MachineInstr *MI,
143                                      const TargetSchedModel *SchedModel) const {
144     return 0;
145   }
146 
147   /// True if the subtarget should run MachineScheduler after aggressive
148   /// coalescing.
149   ///
150   /// This currently replaces the SelectionDAG scheduler with the "source" order
151   /// scheduler (though see below for an option to turn this off and use the
152   /// TargetLowering preference). It does not yet disable the postRA scheduler.
153   virtual bool enableMachineScheduler() const;
154 
155   /// Support printing of [latency:throughput] comment in output .S file.
supportPrintSchedInfo()156   virtual bool supportPrintSchedInfo() const { return false; }
157 
158   /// True if the machine scheduler should disable the TLI preference
159   /// for preRA scheduling with the source level scheduler.
enableMachineSchedDefaultSched()160   virtual bool enableMachineSchedDefaultSched() const { return true; }
161 
162   /// True if the subtarget should enable joining global copies.
163   ///
164   /// By default this is enabled if the machine scheduler is enabled, but
165   /// can be overridden.
166   virtual bool enableJoinGlobalCopies() const;
167 
168   /// True if the subtarget should run a scheduler after register allocation.
169   ///
170   /// By default this queries the PostRAScheduling bit in the scheduling model
171   /// which is the preferred way to influence this.
172   virtual bool enablePostRAScheduler() const;
173 
174   /// True if the subtarget should run the atomic expansion pass.
175   virtual bool enableAtomicExpand() const;
176 
177   /// True if the subtarget should run the indirectbr expansion pass.
178   virtual bool enableIndirectBrExpand() const;
179 
180   /// Override generic scheduling policy within a region.
181   ///
182   /// This is a convenient way for targets that don't provide any custom
183   /// scheduling heuristics (no custom MachineSchedStrategy) to make
184   /// changes to the generic scheduling policy.
overrideSchedPolicy(MachineSchedPolicy & Policy,unsigned NumRegionInstrs)185   virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
186                                    unsigned NumRegionInstrs) const {}
187 
188   // Perform target specific adjustments to the latency of a schedule
189   // dependency.
adjustSchedDependency(SUnit * def,SUnit * use,SDep & dep)190   virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
191 
192   // For use with PostRAScheduling: get the anti-dependence breaking that should
193   // be performed before post-RA scheduling.
getAntiDepBreakMode()194   virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
195 
196   // For use with PostRAScheduling: in CriticalPathRCs, return any register
197   // classes that should only be considered for anti-dependence breaking if they
198   // are on the critical path.
getCriticalPathRCs(RegClassVector & CriticalPathRCs)199   virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
200     return CriticalPathRCs.clear();
201   }
202 
203   // Provide an ordered list of schedule DAG mutations for the post-RA
204   // scheduler.
getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>> & Mutations)205   virtual void getPostRAMutations(
206       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
207   }
208 
209   // Provide an ordered list of schedule DAG mutations for the machine
210   // pipeliner.
getSMSMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>> & Mutations)211   virtual void getSMSMutations(
212       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
213   }
214 
215   // For use with PostRAScheduling: get the minimum optimization level needed
216   // to enable post-RA scheduling.
getOptLevelToEnablePostRAScheduler()217   virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
218     return CodeGenOpt::Default;
219   }
220 
221   /// True if the subtarget should run the local reassignment
222   /// heuristic of the register allocator.
223   /// This heuristic may be compile time intensive, \p OptLevel provides
224   /// a finer grain to tune the register allocator.
225   virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
226 
227   /// True if the subtarget should consider the cost of local intervals
228   /// created by a split candidate when choosing the best split candidate. This
229   /// heuristic may be compile time intensive.
230   virtual bool enableAdvancedRASplitCost() const;
231 
232   /// Enable use of alias analysis during code generation (during MI
233   /// scheduling, DAGCombine, etc.).
234   virtual bool useAA() const;
235 
236   /// Enable the use of the early if conversion pass.
enableEarlyIfConversion()237   virtual bool enableEarlyIfConversion() const { return false; }
238 
239   /// Return PBQPConstraint(s) for the target.
240   ///
241   /// Override to provide custom PBQP constraints.
getCustomPBQPConstraints()242   virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
243     return nullptr;
244   }
245 
246   /// Enable tracking of subregister liveness in register allocator.
247   /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
248   /// possible.
enableSubRegLiveness()249   virtual bool enableSubRegLiveness() const { return false; }
250 
251   /// Returns string representation of scheduler comment
252   std::string getSchedInfoStr(const MachineInstr &MI) const;
253   std::string getSchedInfoStr(MCInst const &MCI) const override;
254 
255   /// This is called after a .mir file was loaded.
256   virtual void mirFileLoaded(MachineFunction &MF) const;
257 };
258 
259 } // end namespace llvm
260 
261 #endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H
262