1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck %s
3
4declare i32 @llvm.amdgcn.writelane(i32, i32, i32) #0
5
6; CHECK-LABEL: {{^}}test_writelane_sreg:
7; CHECK: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
8define amdgpu_kernel void @test_writelane_sreg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
9  %oldval = load i32, i32 addrspace(1)* %out
10  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
11  store i32 %writelane, i32 addrspace(1)* %out, align 4
12  ret void
13}
14
15; CHECK-LABEL: {{^}}test_writelane_imm_sreg:
16; CHECK: v_writelane_b32 v{{[0-9]+}}, 32, s{{[0-9]+}}
17define amdgpu_kernel void @test_writelane_imm_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
18  %oldval = load i32, i32 addrspace(1)* %out
19  %writelane = call i32 @llvm.amdgcn.writelane(i32 32, i32 %src1, i32 %oldval)
20  store i32 %writelane, i32 addrspace(1)* %out, align 4
21  ret void
22}
23
24; CHECK-LABEL: {{^}}test_writelane_vreg_lane:
25; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
26; CHECK: v_writelane_b32 v{{[0-9]+}}, 12, [[LANE]]
27define amdgpu_kernel void @test_writelane_vreg_lane(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 {
28  %tid = call i32 @llvm.amdgcn.workitem.id.x()
29  %gep.in = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 %tid
30  %args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in
31  %oldval = load i32, i32 addrspace(1)* %out
32  %lane = extractelement <2 x i32> %args, i32 1
33  %writelane = call i32 @llvm.amdgcn.writelane(i32 12, i32 %lane, i32 %oldval)
34  store i32 %writelane, i32 addrspace(1)* %out, align 4
35  ret void
36}
37
38; TODO: m0 should be folded.
39; CHECK-LABEL: {{^}}test_writelane_m0_sreg:
40; CHECK: s_mov_b32 m0, -1
41; CHECK: s_mov_b32 [[COPY_M0:s[0-9]+]], m0
42; CHECK: v_writelane_b32 v{{[0-9]+}}, [[COPY_M0]], s{{[0-9]+}}
43define amdgpu_kernel void @test_writelane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
44  %oldval = load i32, i32 addrspace(1)* %out
45  %m0 = call i32 asm "s_mov_b32 m0, -1", "={M0}"()
46  %writelane = call i32 @llvm.amdgcn.writelane(i32 %m0, i32 %src1, i32 %oldval)
47  store i32 %writelane, i32 addrspace(1)* %out, align 4
48  ret void
49}
50
51; CHECK-LABEL: {{^}}test_writelane_imm:
52; CHECK: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 32
53define amdgpu_kernel void @test_writelane_imm(i32 addrspace(1)* %out, i32 %src0) #1 {
54  %oldval = load i32, i32 addrspace(1)* %out
55  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 32, i32 %oldval) #0
56  store i32 %writelane, i32 addrspace(1)* %out, align 4
57  ret void
58}
59
60; CHECK-LABEL: {{^}}test_writelane_sreg_oldval:
61; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], s{{[0-9]+}}
62; CHECK: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
63define amdgpu_kernel void @test_writelane_sreg_oldval(i32 inreg %oldval, i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
64  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
65  store i32 %writelane, i32 addrspace(1)* %out, align 4
66  ret void
67}
68
69; CHECK-LABEL: {{^}}test_writelane_imm_oldval:
70; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], 42
71; CHECK: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
72define amdgpu_kernel void @test_writelane_imm_oldval(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
73  %writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 42)
74  store i32 %writelane, i32 addrspace(1)* %out, align 4
75  ret void
76}
77
78declare i32 @llvm.amdgcn.workitem.id.x() #2
79
80attributes #0 = { nounwind readnone convergent }
81attributes #1 = { nounwind }
82attributes #2 = { nounwind readnone }
83