1 // Copyright 2006-2013 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 // This module contains the architecture-specific code. This make the rest of 6 // the code less dependent on differences between different processor 7 // architecture. 8 // The classes have the same definition for all architectures. The 9 // implementation for a particular architecture is put in cpu_<arch>.cc. 10 // The build system then uses the implementation for the target architecture. 11 // 12 13 #ifndef V8_BASE_CPU_H_ 14 #define V8_BASE_CPU_H_ 15 16 #include "src/base/base-export.h" 17 #include "src/base/macros.h" 18 19 namespace v8 { 20 namespace base { 21 22 // ---------------------------------------------------------------------------- 23 // CPU 24 // 25 // Query information about the processor. 26 // 27 // This class also has static methods for the architecture specific functions. 28 // Add methods here to cope with differences between the supported 29 // architectures. For each architecture the file cpu_<arch>.cc contains the 30 // implementation of these static functions. 31 32 class V8_BASE_EXPORT CPU final { 33 public: 34 CPU(); 35 36 // x86 CPUID information vendor()37 const char* vendor() const { return vendor_; } stepping()38 int stepping() const { return stepping_; } model()39 int model() const { return model_; } ext_model()40 int ext_model() const { return ext_model_; } family()41 int family() const { return family_; } ext_family()42 int ext_family() const { return ext_family_; } type()43 int type() const { return type_; } 44 45 // arm implementer/part information implementer()46 int implementer() const { return implementer_; } 47 static const int ARM = 0x41; 48 static const int NVIDIA = 0x4e; 49 static const int QUALCOMM = 0x51; architecture()50 int architecture() const { return architecture_; } variant()51 int variant() const { return variant_; } 52 static const int NVIDIA_DENVER = 0x0; part()53 int part() const { return part_; } 54 55 // ARM-specific part codes 56 static const int ARM_CORTEX_A5 = 0xc05; 57 static const int ARM_CORTEX_A7 = 0xc07; 58 static const int ARM_CORTEX_A8 = 0xc08; 59 static const int ARM_CORTEX_A9 = 0xc09; 60 static const int ARM_CORTEX_A12 = 0xc0c; 61 static const int ARM_CORTEX_A15 = 0xc0f; 62 63 // Denver-specific part code 64 static const int NVIDIA_DENVER_V10 = 0x002; 65 66 // PPC-specific part codes 67 enum { 68 PPC_POWER5, 69 PPC_POWER6, 70 PPC_POWER7, 71 PPC_POWER8, 72 PPC_POWER9, 73 PPC_G4, 74 PPC_G5, 75 PPC_PA6T 76 }; 77 78 // General features has_fpu()79 bool has_fpu() const { return has_fpu_; } icache_line_size()80 int icache_line_size() const { return icache_line_size_; } dcache_line_size()81 int dcache_line_size() const { return dcache_line_size_; } 82 static const int UNKNOWN_CACHE_LINE_SIZE = 0; 83 84 // x86 features has_cmov()85 bool has_cmov() const { return has_cmov_; } has_sahf()86 bool has_sahf() const { return has_sahf_; } has_mmx()87 bool has_mmx() const { return has_mmx_; } has_sse()88 bool has_sse() const { return has_sse_; } has_sse2()89 bool has_sse2() const { return has_sse2_; } has_sse3()90 bool has_sse3() const { return has_sse3_; } has_ssse3()91 bool has_ssse3() const { return has_ssse3_; } has_sse41()92 bool has_sse41() const { return has_sse41_; } has_sse42()93 bool has_sse42() const { return has_sse42_; } has_osxsave()94 bool has_osxsave() const { return has_osxsave_; } has_avx()95 bool has_avx() const { return has_avx_; } has_fma3()96 bool has_fma3() const { return has_fma3_; } has_bmi1()97 bool has_bmi1() const { return has_bmi1_; } has_bmi2()98 bool has_bmi2() const { return has_bmi2_; } has_lzcnt()99 bool has_lzcnt() const { return has_lzcnt_; } has_popcnt()100 bool has_popcnt() const { return has_popcnt_; } is_atom()101 bool is_atom() const { return is_atom_; } has_non_stop_time_stamp_counter()102 bool has_non_stop_time_stamp_counter() const { 103 return has_non_stop_time_stamp_counter_; 104 } 105 106 // arm features has_idiva()107 bool has_idiva() const { return has_idiva_; } has_neon()108 bool has_neon() const { return has_neon_; } has_thumb2()109 bool has_thumb2() const { return has_thumb2_; } has_vfp()110 bool has_vfp() const { return has_vfp_; } has_vfp3()111 bool has_vfp3() const { return has_vfp3_; } has_vfp3_d32()112 bool has_vfp3_d32() const { return has_vfp3_d32_; } 113 114 // mips features is_fp64_mode()115 bool is_fp64_mode() const { return is_fp64_mode_; } has_msa()116 bool has_msa() const { return has_msa_; } 117 118 private: 119 char vendor_[13]; 120 int stepping_; 121 int model_; 122 int ext_model_; 123 int family_; 124 int ext_family_; 125 int type_; 126 int implementer_; 127 int architecture_; 128 int variant_; 129 int part_; 130 int icache_line_size_; 131 int dcache_line_size_; 132 bool has_fpu_; 133 bool has_cmov_; 134 bool has_sahf_; 135 bool has_mmx_; 136 bool has_sse_; 137 bool has_sse2_; 138 bool has_sse3_; 139 bool has_ssse3_; 140 bool has_sse41_; 141 bool has_sse42_; 142 bool is_atom_; 143 bool has_osxsave_; 144 bool has_avx_; 145 bool has_fma3_; 146 bool has_bmi1_; 147 bool has_bmi2_; 148 bool has_lzcnt_; 149 bool has_popcnt_; 150 bool has_idiva_; 151 bool has_neon_; 152 bool has_thumb2_; 153 bool has_vfp_; 154 bool has_vfp3_; 155 bool has_vfp3_d32_; 156 bool is_fp64_mode_; 157 bool has_non_stop_time_stamp_counter_; 158 bool has_msa_; 159 }; 160 161 } // namespace base 162 } // namespace v8 163 164 #endif // V8_BASE_CPU_H_ 165