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Searched refs:A3 (Results 1 – 13 of 13) sorted by relevance

/art/runtime/arch/mips/
Dregisters_mips.h35 A3 = 7, enumerator
Dcallee_save_frame_mips.h37 (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3) | (1 << art::mips::T0) |
59 (1 << art::mips::A0) | (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3) |
Dcontext_mips.cc87 gprs_[A3] = nullptr; in SmashCallerSaves()
/art/runtime/arch/mips64/
Dregisters_mips64.h35 A3 = 7, enumerator
Dcallee_save_frame_mips64.h38 (1 << art::mips64::A1) | (1 << art::mips64::A2) | (1 << art::mips64::A3) |
46 (1 << art::mips64::A3) | (1 << art::mips64::A4) | (1 << art::mips64::A5) |
Dcontext_mips64.cc79 gprs_[A3] = nullptr; in SmashCallerSaves()
/art/compiler/jni/quick/mips/
Dcalling_convention_mips.cc39 static const Register kJniCoreArgumentRegisters[] = { A0, A1, A2, A3 };
47 static const Register kManagedCoreArgumentRegisters[] = { A0, A1, A2, A3, T0, T1 };
/art/compiler/jni/quick/mips64/
Dcalling_convention_mips64.cc32 A0, A1, A2, A3, A4, A5, A6, A7
/art/compiler/optimizing/
Dcode_generator_mips.h35 { A1, A2, A3, T0, T1 };
46 { A0, A1, A2, A3 };
126 ? Location::RegisterPairLocation(A2, A3) in GetSetValueLocation()
Dcode_generator_mips64.h33 { A1, A2, A3, A4, A5, A6, A7 };
44 { A0, A1, A2, A3, A4, A5, A6, A7 };
Dcode_generator_mips.cc114 if (reg == A1 || reg == A3) { in GetNextLocation()
/art/compiler/utils/mips/
Dassembler_mips32r5_test.cc98 registers_.push_back(new mips::Register(mips::A3)); in SetUpHelpers()
131 secondary_register_names_.emplace(mips::Register(mips::A3), "a3"); in SetUpHelpers()
Dassembler_mips32r6_test.cc111 registers_.push_back(new mips::Register(mips::A3)); in SetUpHelpers()
144 secondary_register_names_.emplace(mips::Register(mips::A3), "a3"); in SetUpHelpers()
368 (Base::GetAssembler()->*f)(mips::A2, mips::A3, &label, is_bare); in BranchCondTwoRegsHelper()
1332 __ Beqc(mips::A2, mips::A3, &label); in TEST_F()