Searched refs:A3 (Results 1 – 13 of 13) sorted by relevance
/art/runtime/arch/mips/ |
D | registers_mips.h | 35 A3 = 7, enumerator
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D | callee_save_frame_mips.h | 37 (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3) | (1 << art::mips::T0) | 59 (1 << art::mips::A0) | (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3) |
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D | context_mips.cc | 87 gprs_[A3] = nullptr; in SmashCallerSaves()
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/art/runtime/arch/mips64/ |
D | registers_mips64.h | 35 A3 = 7, enumerator
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D | callee_save_frame_mips64.h | 38 (1 << art::mips64::A1) | (1 << art::mips64::A2) | (1 << art::mips64::A3) | 46 (1 << art::mips64::A3) | (1 << art::mips64::A4) | (1 << art::mips64::A5) |
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D | context_mips64.cc | 79 gprs_[A3] = nullptr; in SmashCallerSaves()
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/art/compiler/jni/quick/mips/ |
D | calling_convention_mips.cc | 39 static const Register kJniCoreArgumentRegisters[] = { A0, A1, A2, A3 }; 47 static const Register kManagedCoreArgumentRegisters[] = { A0, A1, A2, A3, T0, T1 };
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/art/compiler/jni/quick/mips64/ |
D | calling_convention_mips64.cc | 32 A0, A1, A2, A3, A4, A5, A6, A7
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/art/compiler/optimizing/ |
D | code_generator_mips.h | 35 { A1, A2, A3, T0, T1 }; 46 { A0, A1, A2, A3 }; 126 ? Location::RegisterPairLocation(A2, A3) in GetSetValueLocation()
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D | code_generator_mips64.h | 33 { A1, A2, A3, A4, A5, A6, A7 }; 44 { A0, A1, A2, A3, A4, A5, A6, A7 };
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D | code_generator_mips.cc | 114 if (reg == A1 || reg == A3) { in GetNextLocation()
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/art/compiler/utils/mips/ |
D | assembler_mips32r5_test.cc | 98 registers_.push_back(new mips::Register(mips::A3)); in SetUpHelpers() 131 secondary_register_names_.emplace(mips::Register(mips::A3), "a3"); in SetUpHelpers()
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D | assembler_mips32r6_test.cc | 111 registers_.push_back(new mips::Register(mips::A3)); in SetUpHelpers() 144 secondary_register_names_.emplace(mips::Register(mips::A3), "a3"); in SetUpHelpers() 368 (Base::GetAssembler()->*f)(mips::A2, mips::A3, &label, is_bare); in BranchCondTwoRegsHelper() 1332 __ Beqc(mips::A2, mips::A3, &label); in TEST_F()
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