| /art/compiler/utils/mips/ |
| D | assembler_mips32r5_test.cc | 157 fp_registers_.push_back(new mips::FRegister(mips::F0)); in SetUpHelpers()
280 __ LoadQFromOffset(mips::F0, mips::A0, 0); in TEST_F()
281 __ LoadQFromOffset(mips::F0, mips::A0, 1); in TEST_F()
282 __ LoadQFromOffset(mips::F0, mips::A0, 2); in TEST_F()
283 __ LoadQFromOffset(mips::F0, mips::A0, 4); in TEST_F()
284 __ LoadQFromOffset(mips::F0, mips::A0, 8); in TEST_F()
285 __ LoadQFromOffset(mips::F0, mips::A0, 511); in TEST_F()
286 __ LoadQFromOffset(mips::F0, mips::A0, 512); in TEST_F()
287 __ LoadQFromOffset(mips::F0, mips::A0, 513); in TEST_F()
288 __ LoadQFromOffset(mips::F0, mips::A0, 514); in TEST_F()
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| D | assembler_mips32r6_test.cc | 170 fp_registers_.push_back(new mips::FRegister(mips::F0)); in SetUpHelpers()
391 (Base::GetAssembler()->*f)(mips::F0, &label, is_bare); in BranchFpuCondHelper()
673 __ LoadDFromOffset(mips::F0, mips::A0, -0x8000); in TEST_F()
674 __ LoadDFromOffset(mips::F0, mips::A0, +0); in TEST_F()
675 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FF8); in TEST_F()
676 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFB); in TEST_F()
677 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFC); in TEST_F()
678 __ LoadDFromOffset(mips::F0, mips::A0, +0x7FFF); in TEST_F()
679 __ LoadDFromOffset(mips::F0, mips::A0, -0xFFF0); in TEST_F()
680 __ LoadDFromOffset(mips::F0, mips::A0, -0x8008); in TEST_F()
[all …]
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| /art/compiler/utils/mips64/ |
| D | managed_register_mips64_test.cc | 111 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); in TEST()
118 EXPECT_EQ(F0, reg.AsFpuRegister()); in TEST()
120 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
158 Mips64ManagedRegister freg = Mips64ManagedRegister::FromFpuRegister(F0); in TEST()
165 EXPECT_EQ(F0, reg.AsOverlappingFpuRegister()); in TEST()
208 EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
216 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
225 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
234 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromFpuRegister(F0))); in TEST()
237 Mips64ManagedRegister reg_F0 = Mips64ManagedRegister::FromFpuRegister(F0); in TEST()
[all …]
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.cc | 41 if (rhs >= F0 && rhs < kNumberOfFpuRegisters) { in operator <<()
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| D | registers_mips64.h | 70 F0 = 0, enumerator
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| D | context_mips64.cc | 86 fprs_[F0] = nullptr; in SmashCallerSaves()
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| D | callee_save_frame_mips64.h | 63 (1 << art::mips64::F0) | (1 << art::mips64::F1) | (1 << art::mips64::F2) |
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| /art/runtime/arch/mips/ |
| D | registers_mips.cc | 40 if (rhs >= F0 && rhs < kNumberOfFRegisters) { in operator <<()
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| D | registers_mips.h | 69 F0 = 0, enumerator
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| D | callee_save_frame_mips.h | 75 (1 << art::mips::F0) | (1 << art::mips::F1) | (1 << art::mips::F2) | (1 << art::mips::F3) |
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 77 return Mips64ManagedRegister::FromFpuRegister(F0); in ReturnRegisterForShorty()
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 88 return MipsManagedRegister::FromFRegister(F0); in ReturnRegisterForShorty()
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| /art/compiler/optimizing/ |
| D | code_generator_mips.h | 130 return Location::FpuRegisterLocation(F0); in GetFpuLocation()
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| D | code_generator_mips64.h | 127 return Location::FpuRegisterLocation(F0); in GetFpuLocation()
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| D | code_generator_mips64.cc | 68 return Location::FpuRegisterLocation(F0); in Mips64ReturnLocation()
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| D | code_generator_mips.cc | 72 return Location::FpuRegisterLocation(F0); in MipsReturnLocation()
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