Searched refs:T0 (Results 1 – 11 of 11) sorted by relevance
| /art/runtime/arch/mips/ |
| D | registers_mips.h | 36 T0 = 8, // Two extra arguments / temporaries. enumerator
|
| D | callee_save_frame_mips.h | 37 (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3) | (1 << art::mips::T0) |
60 (1 << art::mips::T0) | (1 << art::mips::T1) | (1 << art::mips::T2) | (1 << art::mips::T3) |
|
| D | context_mips.cc | 88 gprs_[T0] = nullptr; in SmashCallerSaves()
|
| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 40 T0 = 12, // Temporaries. enumerator
|
| D | callee_save_frame_mips64.h | 47 (1 << art::mips64::A6) | (1 << art::mips64::A7) | (1 << art::mips64::T0) |
|
| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 47 static const Register kManagedCoreArgumentRegisters[] = { A0, A1, A2, A3, T0, T1 };
|
| /art/compiler/utils/mips/ |
| D | assembler_mips32r6_test.cc | 112 registers_.push_back(new mips::Register(mips::T0)); in SetUpHelpers()
145 secondary_register_names_.emplace(mips::Register(mips::T0), "t0"); in SetUpHelpers()
1509 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
1514 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
1519 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
1524 __ Addu(mips::T0, mips::T1, mips::T2); in TEST_F()
1604 __ Addiu(mips::T0, mips::T1, 0x5678, &patcher_label1); in TEST_F()
1615 __ Addiu(mips::T0, mips::T1, 0x5678, &patcher_label2); in TEST_F()
|
| D | assembler_mips32r5_test.cc | 99 registers_.push_back(new mips::Register(mips::T0)); in SetUpHelpers()
132 secondary_register_names_.emplace(mips::Register(mips::T0), "t0"); in SetUpHelpers()
|
| /art/compiler/utils/mips64/ |
| D | managed_register_mips64_test.cc | 67 reg = Mips64ManagedRegister::FromGpuRegister(T0); in TEST()
72 EXPECT_EQ(T0, reg.AsGpuRegister()); in TEST()
|
| /art/compiler/optimizing/ |
| D | code_generator_mips.h | 35 { A1, A2, A3, T0, T1 };
|
| D | code_generator_mips64.cc | 5919 invoke->GetLocations()->AddTemp(Location::RegisterLocation(T0)); in VisitInvokeInterface()
|