Searched refs:T3 (Results 1 – 8 of 8) sorted by relevance
| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 43 T3 = 15, enumerator
62 TMP2 = T3, // scratch register (in addition to AT, reserved for assembler)
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| D | callee_save_frame_mips64.h | 48 (1 << art::mips64::T1) | (1 << art::mips64::T2) | (1 << art::mips64::T3) |
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 39 T3 = 11, enumerator
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| D | callee_save_frame_mips.h | 60 (1 << art::mips::T0) | (1 << art::mips::T1) | (1 << art::mips::T2) | (1 << art::mips::T3) |
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| /art/runtime/verifier/ |
| D | verifier_deps.cc | 632 template<typename T1, typename T2, typename T3>
633 static inline void EncodeTuple(std::vector<uint8_t>* out, const std::tuple<T1, T2, T3>& t) { in EncodeTuple()
639 template<typename T1, typename T2, typename T3>
640 static inline void DecodeTuple(const uint8_t** in, const uint8_t* end, std::tuple<T1, T2, T3>* t) { in DecodeTuple()
643 T3 v3 = Decode<T3>(DecodeUint32WithOverflowCheck(in, end)); in DecodeTuple()
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| /art/compiler/utils/mips/ |
| D | assembler_mips32r5_test.cc | 102 registers_.push_back(new mips::Register(mips::T3)); in SetUpHelpers()
135 secondary_register_names_.emplace(mips::Register(mips::T3), "t3"); in SetUpHelpers()
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| D | assembler_mips32r6_test.cc | 115 registers_.push_back(new mips::Register(mips::T3)); in SetUpHelpers()
148 secondary_register_names_.emplace(mips::Register(mips::T3), "t3"); in SetUpHelpers()
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| /art/compiler/utils/mips64/ |
| D | managed_register_mips64_test.cc | 74 reg = Mips64ManagedRegister::FromGpuRegister(T3); in TEST()
79 EXPECT_EQ(T3, reg.AsGpuRegister()); in TEST()
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