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Searched refs:false_src (Results 1 – 2 of 2) sorted by relevance

/art/compiler/optimizing/
Dcode_generator_mips64.cc4661 Location false_src = locations->InAt(0); in GenConditionalMove() local
4704 if (false_src.IsConstant()) { in GenConditionalMove()
4705 DCHECK(false_src.GetConstant()->IsZeroBitPattern()); in GenConditionalMove()
4715 __ Selnez(dst.AsRegister<GpuRegister>(), false_src.AsRegister<GpuRegister>(), cond_reg); in GenConditionalMove()
4717 __ Seleqz(dst.AsRegister<GpuRegister>(), false_src.AsRegister<GpuRegister>(), cond_reg); in GenConditionalMove()
4719 } else if (false_src.IsConstant()) { in GenConditionalMove()
4729 __ Selnez(TMP, false_src.AsRegister<GpuRegister>(), cond_reg); in GenConditionalMove()
4732 __ Seleqz(TMP, false_src.AsRegister<GpuRegister>(), cond_reg); in GenConditionalMove()
4745 FpuRegister src_reg = false_src.AsFpuRegister<FpuRegister>(); in GenConditionalMove()
4751 } else if (false_src.IsConstant()) { in GenConditionalMove()
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Dcode_generator_mips.cc6338 Location false_src = locations->InAt(0); in GenConditionalMoveR6() local
6373 if (false_src.IsConstant()) { in GenConditionalMoveR6()
6374 DCHECK(false_src.GetConstant()->IsZeroBitPattern()); in GenConditionalMoveR6()
6384 __ Selnez(dst.AsRegister<Register>(), false_src.AsRegister<Register>(), cond_reg); in GenConditionalMoveR6()
6386 __ Seleqz(dst.AsRegister<Register>(), false_src.AsRegister<Register>(), cond_reg); in GenConditionalMoveR6()
6388 } else if (false_src.IsConstant()) { in GenConditionalMoveR6()
6398 __ Selnez(TMP, false_src.AsRegister<Register>(), cond_reg); in GenConditionalMoveR6()
6401 __ Seleqz(TMP, false_src.AsRegister<Register>(), cond_reg); in GenConditionalMoveR6()
6413 Register src_lo = false_src.AsRegisterPairLow<Register>(); in GenConditionalMoveR6()
6414 Register src_hi = false_src.AsRegisterPairHigh<Register>(); in GenConditionalMoveR6()
[all …]