| /art/compiler/utils/arm/ |
| D | managed_register_arm.cc | 29 Register low = AsRegisterPairLow(); in Overlaps() local
31 return ArmManagedRegister::FromCoreRegister(low).Overlaps(other) || in Overlaps()
37 SRegister low = AsOverlappingDRegisterLow(); in Overlaps() local
40 return (low == other_sreg) || (high == other_sreg); in Overlaps()
54 int low; in AllocIdLow() local
57 low = (r * 2) + kNumberOfCoreRegIds; // Return a SRegister. in AllocIdLow()
60 low = (r - kNumberOfDRegIds) * 2; // Return a Register. in AllocIdLow()
61 if (low > 6) { in AllocIdLow()
63 low = 1; in AllocIdLow()
66 return low; in AllocIdLow()
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| /art/compiler/utils/mips/ |
| D | managed_register_mips.cc | 30 Register low = AsRegisterPairLow(); in Overlaps() local
32 return MipsManagedRegister::FromCoreRegister(low).Overlaps(other) || in Overlaps()
38 FRegister low = AsOverlappingDRegisterLow(); in Overlaps() local
41 return (low == other_freg) || (high == other_freg); in Overlaps()
55 int low; in AllocIdLow() local
58 low = (r * 2) + kNumberOfCoreRegIds; // Return an FRegister. in AllocIdLow()
61 low = (r - kNumberOfDRegIds) * 2 + 2; // Return a Register. in AllocIdLow()
62 if (low >= 24) { in AllocIdLow()
64 low = 5; in AllocIdLow()
67 return low; in AllocIdLow()
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| /art/tools/ahat/src/main/com/android/ahat/ |
| D | HtmlEscaper.java | 27 int low = 0; in escape() local
34 sb.append(text.substring(low, i)); in escape()
36 low = i + 1; in escape()
43 sb.append(text.substring(low)); in escape()
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| /art/compiler/utils/x86_64/ |
| D | managed_register_x86_64.cc | 41 Register low; member
47 #define REGISTER_PAIR_ENUMERATION(low, high) { low##_##high, low, high }, argument
63 Register low = AsRegisterPairLow().AsRegister(); in Overlaps() local
65 return X86_64ManagedRegister::FromCpuRegister(low).Overlaps(other) || in Overlaps()
80 return kRegisterPairs[r].low; in AllocIdLow()
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| /art/compiler/utils/x86/ |
| D | managed_register_x86.cc | 42 Register low; member
48 #define REGISTER_PAIR_ENUMERATION(low, high) { low##_##high, low, high }, argument
68 Register low = AsRegisterPairLow(); in Overlaps() local
70 return X86ManagedRegister::FromCpuRegister(low).Overlaps(other) || in Overlaps()
85 return kRegisterPairs[r].low; in AllocIdLow()
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64.cc | 67 int low = RegNo(); in RegIdLow() local
69 low += kNumberOfXRegIds; in RegIdLow()
71 low += kNumberOfXRegIds + kNumberOfWRegIds + kNumberOfDRegIds; in RegIdLow()
73 return low; in RegIdLow()
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| /art/compiler/optimizing/ |
| D | intrinsics.cc | 121 int32_t low = GetIntegerCacheField(cache_class, kLowFieldName); in CheckIntegerCache() local
123 if (boot_image_cache->GetLength() != high - low + 1) { in CheckIntegerCache()
140 if (value_field->GetInt(boot_image_object) != low + i) { in CheckIntegerCache()
183 int32_t low = GetIntegerCacheField(cache_class, kLowFieldName); in ComputeIntegerValueOfLocations() local
188 CHECK_EQ(current_cache->GetLength(), high - low + 1); in ComputeIntegerValueOfLocations()
194 CHECK_EQ(value_field->GetInt(current_object), low + i); in ComputeIntegerValueOfLocations()
199 if (static_cast<uint32_t>(value) - static_cast<uint32_t>(low) < in ComputeIntegerValueOfLocations()
200 static_cast<uint32_t>(high - low + 1)) { in ComputeIntegerValueOfLocations()
234 int32_t low = value_field->GetInt(low_integer); in ComputeIntegerValueOfLocations() local
235 if (static_cast<uint32_t>(value) - static_cast<uint32_t>(low) < in ComputeIntegerValueOfLocations()
[all …]
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| D | locations.h | 137 static Location RegisterPairLocation(int low, int high) { in RegisterPairLocation() argument
138 return Location(kRegisterPair, low << 16 | high); in RegisterPairLocation()
141 static Location FpuRegisterPairLocation(int low, int high) { in FpuRegisterPairLocation() argument
142 return Location(kFpuRegisterPair, low << 16 | high); in FpuRegisterPairLocation()
170 int low() const { in low() function
195 return static_cast<T>(low()); in AsRegisterPairLow()
207 return static_cast<T>(low()); in AsFpuRegisterPairLow()
222 return Location::RegisterLocation(low()); in ToLow()
224 return Location::FpuRegisterLocation(low()); in ToLow()
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| D | common_arm.h | 86 int reg_code = location.low(); in DRegisterFrom()
220 inline Location LocationFrom(const vixl::aarch32::Register& low, in LocationFrom() argument
222 return Location::RegisterPairLocation(low.GetCode(), high.GetCode()); in LocationFrom()
225 inline Location LocationFrom(const vixl::aarch32::SRegister& low, in LocationFrom() argument
227 return Location::FpuRegisterPairLocation(low.GetCode(), high.GetCode()); in LocationFrom()
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| D | register_allocator.cc | 234 LiveInterval* low = interval->GetLowInterval()->SplitAt(position); in Split() local
235 new_interval->SetLowInterval(low); in Split()
236 low->SetHighInterval(new_interval); in Split()
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| D | locations.cc | 103 os << location.low() << ":" << location.high(); in operator <<()
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| D | code_generator.cc | 1343 int low = location.low(); in EmitEnvironment() local
1345 if (slow_path != nullptr && slow_path->IsFpuRegisterSaved(low)) { in EmitEnvironment()
1346 uint32_t offset = slow_path->GetStackOffsetOfFpuRegister(low); in EmitEnvironment()
1349 stack_map_stream->AddDexRegisterEntry(Kind::kInFpuRegister, low); in EmitEnvironment()
1364 int low = location.low(); in EmitEnvironment() local
1366 if (slow_path != nullptr && slow_path->IsCoreRegisterSaved(low)) { in EmitEnvironment()
1367 uint32_t offset = slow_path->GetStackOffsetOfCoreRegister(low); in EmitEnvironment()
1370 stack_map_stream->AddDexRegisterEntry(Kind::kInRegister, low); in EmitEnvironment()
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| D | parallel_move_resolver.cc | 82 return Location::RegisterLocation(location.low()); in LowOf()
84 return Location::FpuRegisterLocation(location.low()); in LowOf()
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| D | register_allocator_linear_scan.cc | 39 static bool IsLowOfUnalignedPairInterval(LiveInterval* low) { in IsLowOfUnalignedPairInterval() argument
40 return GetHighForLowRegister(low->GetRegister()) != low->GetHighInterval()->GetRegister(); in IsLowOfUnalignedPairInterval()
352 current->SetRegister(first.low()); in ProcessInstruction()
364 current->SetRegister(output.low()); in ProcessInstruction()
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| /art/test/717-integer-value-of/src/ |
| D | Main.java | 95 int low = (int) lowField.get(integerCacheClass); in testValueOfConst() local
96 Integer old42 = cache[42 - low]; in testValueOfConst()
97 cache[42 - low] = new Integer(42); in testValueOfConst()
105 cache[42 - low] = old42; in testValueOfConst()
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| /art/test/568-checker-onebit/ |
| D | info.txt | 1 Unit test for 32-bit and 64-bit high/low-bit operations.
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| /art/test/550-checker-regression-wide-store/ |
| D | info.txt | 2 would not invalidate the low vreg. The resulting environment would generate
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| /art/runtime/native/ |
| D | libcore_util_CharsetUtils.cc | 224 jchar low = (i + 1 != end) ? string->CharAt(i + 1) : 0; in CharsetUtils_toUtf8Bytes() local
225 if (!U16_IS_SURROGATE_LEAD(high) || !U16_IS_SURROGATE_TRAIL(low)) { in CharsetUtils_toUtf8Bytes()
233 ch = U16_GET_SUPPLEMENTARY(high, low); in CharsetUtils_toUtf8Bytes()
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| /art/runtime/jdwp/ |
| D | jdwp_request.cc | 180 uint64_t low = Read4BE(); in Read8BE() local
181 return (high << 32) | low; in Read8BE()
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| /art/runtime/interpreter/mterp/mips/ |
| D | other.S | 28 FETCH(a0, 1) # a0 <- bbbb (low)
77 FETCH(a0, 1) # a0 <- bbbb (low)
92 FETCH(a0, 1) # a0 <- bbbb (low)
93 FETCH(a1, 2) # a1 <- BBBB (low middle)
95 INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb (low word)
114 FETCH(a0, 1) # a0 <- 0000bbbb (low)
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| D | arithmetic.S | 448 SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high)
458 LOAD64(a0, a1, t0) # vAA.low / high
462 LOAD64(a2, a3, t1) # vBB.low / high
479 SET_VREG64_GOTO(v0, v1, rOBJ, t1) # vA/vA+1 <- v0(low)/v1(high)
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| /art/runtime/interpreter/mterp/arm/ |
| D | other.S | 29 FETCH r0, 1 @ r0<- bbbb (low)
80 FETCH r0, 1 @ r0<- bbbb (low)
96 FETCH r0, 1 @ r0<- bbbb (low)
97 FETCH r1, 2 @ r1<- BBBB (low middle)
99 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
124 FETCH r0, 1 @ r0<- 0000bbbb (low)
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| /art/runtime/interpreter/mterp/mips64/ |
| D | other.S | 28 lh a0, 2(rPC) # a0 <- bbbb (low)
81 lh a0, 2(rPC) # a0 <- bbbb (low)
97 lh a0, 2(rPC) # a0 <- bbbb (low)
98 lh a1, 4(rPC) # a1 <- BBBB (low middle)
121 lh a0, 2(rPC) # a0 <- bbbb (low)
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| D | control_flow.S | 75 lh rINST, 2(rPC) # rINST <- aaaa (low)
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| /art/tools/ahat/src/main/com/android/ahat/dominators/ |
| D | Dominators.java | 208 public boolean hasIdInRange(long low, long high) { in hasIdInRange() argument
210 if (low <= ids[i] && ids[i] <= high) { in hasIdInRange()
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