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Searched refs:out_high (Results 1 – 2 of 2) sorted by relevance

/art/compiler/optimizing/
Dcode_generator_mips.cc3866 Register out_high = locations->Out().AsRegisterPairHigh<Register>(); in DivRemOneOrMinusOne() local
3872 __ Move(out_high, ZERO); in DivRemOneOrMinusOne()
3878 __ Subu(out_high, ZERO, in_high); in DivRemOneOrMinusOne()
3879 __ Subu(out_high, out_high, AT); in DivRemOneOrMinusOne()
3882 __ Move(out_high, in_high); in DivRemOneOrMinusOne()
3943 Register out_high = locations->Out().AsRegisterPairHigh<Register>(); in DivRemByPowerOfTwo() local
3961 __ Addu(out_high, in_high, TMP); in DivRemByPowerOfTwo()
3964 __ Ins(out_low, out_high, 32 - ctz_imm, ctz_imm); in DivRemByPowerOfTwo()
3965 __ Sra(out_high, out_high, ctz_imm); in DivRemByPowerOfTwo()
3967 __ Sll(AT, out_high, 32 - ctz_imm); in DivRemByPowerOfTwo()
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Dcode_generator_arm_vixl.cc8002 vixl32::Register out_high = HighRegisterFrom(out); in VisitBitwiseNegatedRight() local
8007 __ Bic(out_high, first_high, second_high); in VisitBitwiseNegatedRight()
8011 __ Orn(out_high, first_high, second_high); in VisitBitwiseNegatedRight()
8164 vixl32::Register out_high = HighRegisterFrom(out); in GenerateAddLongConst() local
8173 __ Add(out_high, first_high, value_high); in GenerateAddLongConst()
8178 __ Adc(out_high, first_high, value_high); in GenerateAddLongConst()
8181 __ Sbc(out_high, first_high, ~value_high); in GenerateAddLongConst()
8211 vixl32::Register out_high = HighRegisterFrom(out); in HandleBitwiseOperation() local
8214 GenerateAndConst(out_high, first_high, value_high); in HandleBitwiseOperation()
8217 GenerateOrrConst(out_high, first_high, value_high); in HandleBitwiseOperation()
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