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Searched refs:out_low (Results 1 – 2 of 2) sorted by relevance

/art/compiler/optimizing/
Dcode_generator_mips.cc3867 Register out_low = locations->Out().AsRegisterPairLow<Register>(); in DivRemOneOrMinusOne() local
3873 __ Move(out_low, ZERO); in DivRemOneOrMinusOne()
3876 __ Subu(out_low, ZERO, in_low); in DivRemOneOrMinusOne()
3877 __ Sltu(AT, ZERO, out_low); in DivRemOneOrMinusOne()
3881 __ Move(out_low, in_low); in DivRemOneOrMinusOne()
3944 Register out_low = locations->Out().AsRegisterPairLow<Register>(); in DivRemByPowerOfTwo() local
3962 __ Srl(out_low, AT, ctz_imm); in DivRemByPowerOfTwo()
3964 __ Ins(out_low, out_high, 32 - ctz_imm, ctz_imm); in DivRemByPowerOfTwo()
3969 __ Or(out_low, out_low, AT); in DivRemByPowerOfTwo()
3972 __ Subu(out_low, ZERO, out_low); in DivRemByPowerOfTwo()
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Dcode_generator_arm_vixl.cc8001 vixl32::Register out_low = LowRegisterFrom(out); in VisitBitwiseNegatedRight() local
8006 __ Bic(out_low, first_low, second_low); in VisitBitwiseNegatedRight()
8010 __ Orn(out_low, first_low, second_low); in VisitBitwiseNegatedRight()
8163 vixl32::Register out_low = LowRegisterFrom(out); in GenerateAddLongConst() local
8170 if (!out_low.Is(first_low)) { in GenerateAddLongConst()
8171 __ Mov(out_low, first_low); in GenerateAddLongConst()
8176 __ Adds(out_low, first_low, value_low); in GenerateAddLongConst()
8210 vixl32::Register out_low = LowRegisterFrom(out); in HandleBitwiseOperation() local
8213 GenerateAndConst(out_low, first_low, value_low); in HandleBitwiseOperation()
8216 GenerateOrrConst(out_low, first_low, value_low); in HandleBitwiseOperation()
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