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Searched refs:out_reg (Results 1 – 19 of 19) sorted by relevance

/art/tools/dexanalyze/
Ddexanalyze_bytecode.cc266 uint32_t out_reg = inst->VRegA_22c(); in ProcessCodeItem() local
274 ExtendPrefix(&out_reg, &field_idx); in ProcessCodeItem()
275 CHECK(InstNibbles(new_opcode, {out_reg, field_idx})); in ProcessCodeItem()
286 CHECK(InstNibbles(new_opcode, {out_reg, receiver, type_idx, field_idx})); in ProcessCodeItem()
296 uint32_t out_reg = is_jumbo ? inst->VRegA_31c() : inst->VRegA_21c(); in ProcessCodeItem() local
303 ExtendPrefix(&out_reg, &idx); in ProcessCodeItem()
304 CHECK(InstNibbles(opcode, {out_reg, idx})); in ProcessCodeItem()
324 uint32_t out_reg = inst->VRegA_21c(); in ProcessCodeItem() local
334 ExtendPrefix(&out_reg, &field_idx); in ProcessCodeItem()
335 if (InstNibbles(new_opcode, {out_reg, field_idx})) { in ProcessCodeItem()
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/art/compiler/jni/quick/
Djni_compiler.cc351 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
352 __ CreateHandleScopeEntry(out_reg, class_handle_scope_offset, in ArtJniCompileMethodInternal()
398 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
399 __ CreateHandleScopeEntry(out_reg, locked_object_handle_scope_offset, in ArtJniCompileMethodInternal()
473 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
474 __ CreateHandleScopeEntry(out_reg, handle_scope_offset, in ArtJniCompileMethodInternal()
593 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
594 __ Load(out_reg, saved_cookie_offset, 4); in ArtJniCompileMethodInternal()
605 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
606 __ CreateHandleScopeEntry(out_reg, locked_object_handle_scope_offset, in ArtJniCompileMethodInternal()
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/art/compiler/utils/x86/
Djni_macro_assembler_x86.cc427 X86ManagedRegister out_reg = mout_reg.AsX86(); in CreateHandleScopeEntry() local
430 CHECK(out_reg.IsCpuRegister()); in CreateHandleScopeEntry()
434 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
435 __ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); in CreateHandleScopeEntry()
439 __ leal(out_reg.AsCpuRegister(), Address(ESP, handle_scope_offset)); in CreateHandleScopeEntry()
442 __ leal(out_reg.AsCpuRegister(), Address(ESP, handle_scope_offset)); in CreateHandleScopeEntry()
468 X86ManagedRegister out_reg = mout_reg.AsX86(); in LoadReferenceFromHandleScope() local
470 CHECK(out_reg.IsCpuRegister()); in LoadReferenceFromHandleScope()
473 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
474 __ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); in LoadReferenceFromHandleScope()
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Djni_macro_assembler_x86.h133 void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset,
/art/compiler/utils/x86_64/
Djni_macro_assembler_x86_64.cc478 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); in CreateHandleScopeEntry() local
482 in_reg = out_reg; in CreateHandleScopeEntry()
487 CHECK(out_reg.IsCpuRegister()); in CreateHandleScopeEntry()
491 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
492 __ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); in CreateHandleScopeEntry()
496 __ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); in CreateHandleScopeEntry()
499 __ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); in CreateHandleScopeEntry()
525 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); in LoadReferenceFromHandleScope() local
527 CHECK(out_reg.IsCpuRegister()); in LoadReferenceFromHandleScope()
530 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
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Djni_macro_assembler_x86_64.h155 void CreateHandleScopeEntry(ManagedRegister out_reg,
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc561 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); in CreateHandleScopeEntry() local
565 CHECK(out_reg.IsXRegister()) << out_reg; in CreateHandleScopeEntry()
571 LoadWFromOffset(kLoadWord, out_reg.AsOverlappingWRegister(), SP, in CreateHandleScopeEntry()
573 in_reg = out_reg; in CreateHandleScopeEntry()
576 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
577 LoadImmediate(out_reg.AsXRegister(), 0, eq); in CreateHandleScopeEntry()
579 AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), ne); in CreateHandleScopeEntry()
581 AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), al); in CreateHandleScopeEntry()
608 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); in LoadReferenceFromHandleScope() local
610 CHECK(out_reg.IsXRegister()) << out_reg; in LoadReferenceFromHandleScope()
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Djni_macro_assembler_arm64.h145 void CreateHandleScopeEntry(ManagedRegister out_reg,
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc486 vixl::aarch32::Register out_reg = AsVIXLRegister(mout_reg.AsArm()); in CreateHandleScopeEntry() local
490 temps.Exclude(out_reg); in CreateHandleScopeEntry()
496 asm_.LoadFromOffset(kLoadWord, out_reg, sp, handle_scope_offset.Int32Value()); in CreateHandleScopeEntry()
497 in_reg = out_reg; in CreateHandleScopeEntry()
504 if (!out_reg.Is(in_reg)) { in CreateHandleScopeEntry()
509 ___ mov(eq, out_reg, 0); in CreateHandleScopeEntry()
510 asm_.AddConstantInIt(out_reg, sp, handle_scope_offset.Int32Value(), ne); in CreateHandleScopeEntry()
516 asm_.AddConstantInIt(out_reg, sp, handle_scope_offset.Int32Value(), ne); in CreateHandleScopeEntry()
523 asm_.AddConstant(out_reg, sp, handle_scope_offset.Int32Value()); in CreateHandleScopeEntry()
Djni_macro_assembler_arm_vixl.h163 void CreateHandleScopeEntry(ManagedRegister out_reg,
/art/compiler/optimizing/
Dcode_generator_arm_vixl.cc4264 vixl32::Register out_reg = OutputRegister(rem); in VisitRem() local
4274 __ Mls(out_reg, temp, reg2, reg1); in VisitRem()
4279 DCHECK(out_reg.Is(r1)); in VisitRem()
4572 vixl32::Register out_reg = RegisterFrom(locations->Out()); in VisitAbs() local
4575 __ Add(out_reg, in_reg, mask); in VisitAbs()
4576 __ Eor(out_reg, out_reg, mask); in VisitAbs()
4841 vixl32::Register out_reg = OutputRegister(op); in HandleShift() local
4846 __ And(out_reg, second_reg, kMaxIntShiftDistance); in HandleShift()
4848 __ Lsl(out_reg, first_reg, out_reg); in HandleShift()
4850 __ Asr(out_reg, first_reg, out_reg); in HandleShift()
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Dinstruction_builder.h133 void BuildCheckedDivRem(uint16_t out_reg,
Dintrinsics_arm64.cc596 Register out_reg = is_double ? XRegisterFrom(l->Out()) : WRegisterFrom(l->Out()); in GenMathRound() local
600 __ Fcvtas(out_reg, in_reg); in GenMathRound()
603 __ Tbz(out_reg, out_reg.GetSizeInBits() - 1, &done); in GenMathRound()
611 __ Cinc(out_reg, out_reg, eq); in GenMathRound()
Dcode_generator_mips64.cc5090 GpuRegister out_reg = out.AsRegister<GpuRegister>(); in GenerateReferenceLoadOneRegister() local
5101 out_reg, in GenerateReferenceLoadOneRegister()
5110 __ Move(maybe_temp.AsRegister<GpuRegister>(), out_reg); in GenerateReferenceLoadOneRegister()
5112 __ LoadFromOffset(kLoadUnsignedWord, out_reg, out_reg, offset); in GenerateReferenceLoadOneRegister()
5118 __ LoadFromOffset(kLoadUnsignedWord, out_reg, out_reg, offset); in GenerateReferenceLoadOneRegister()
5119 __ MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadOneRegister()
5130 GpuRegister out_reg = out.AsRegister<GpuRegister>(); in GenerateReferenceLoadTwoRegisters() local
5149 __ LoadFromOffset(kLoadUnsignedWord, out_reg, obj_reg, offset); in GenerateReferenceLoadTwoRegisters()
5155 __ LoadFromOffset(kLoadUnsignedWord, out_reg, obj_reg, offset); in GenerateReferenceLoadTwoRegisters()
5156 __ MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadTwoRegisters()
Dintrinsics_arm_vixl.cc467 vixl32::Register out_reg = OutputRegister(invoke); in VisitMathRoundFloat() local
475 __ Vmov(out_reg, temp1); in VisitMathRoundFloat()
478 __ Cmp(out_reg, 0); in VisitMathRoundFloat()
495 __ add(eq, out_reg, out_reg, 1); in VisitMathRoundFloat()
Dcode_generator_mips.cc6918 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadOneRegister() local
6929 out_reg, in GenerateReferenceLoadOneRegister()
6938 __ Move(maybe_temp.AsRegister<Register>(), out_reg); in GenerateReferenceLoadOneRegister()
6940 __ LoadFromOffset(kLoadWord, out_reg, out_reg, offset); in GenerateReferenceLoadOneRegister()
6946 __ LoadFromOffset(kLoadWord, out_reg, out_reg, offset); in GenerateReferenceLoadOneRegister()
6947 __ MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadOneRegister()
6958 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadTwoRegisters() local
6977 __ LoadFromOffset(kLoadWord, out_reg, obj_reg, offset); in GenerateReferenceLoadTwoRegisters()
6983 __ LoadFromOffset(kLoadWord, out_reg, obj_reg, offset); in GenerateReferenceLoadTwoRegisters()
6984 __ MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadTwoRegisters()
/art/compiler/utils/
Djni_macro_assembler.h180 virtual void CreateHandleScopeEntry(ManagedRegister out_reg,
/art/oatdump/
Doatdump.cc1457 for (size_t out_reg = 0; out_reg < num_outs; out_reg++) { in DumpVregLocations() local
1458 if (out_reg == 0) { in DumpVregLocations()
1462 uint32_t offset = GetOutVROffset(out_reg, GetInstructionSet()); in DumpVregLocations()
1463 os << " v" << out_reg << "[sp + #" << offset << "]"; in DumpVregLocations()
/art/compiler/utils/mips/
Dassembler_mips.h1342 void CreateHandleScopeEntry(ManagedRegister out_reg,