| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 25 ADDC = 0x01, enumerator
81 case ADDC: in lanaiAluCodeToString()
107 .Case("addc", ADDC) in stringToLanaiAluCode()
124 return AluCode::ADDC; in isdToLanaiAluCode()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 25 ADDC = 0x01, enumerator
81 case ADDC: in lanaiAluCodeToString()
107 .Case("addc", ADDC) in stringToLanaiAluCode()
124 return AluCode::ADDC; in isdToLanaiAluCode()
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Alpha/ |
| D | add128.ll | 1 ;test for ADDC and ADDE expansion
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/ |
| D | addc-adde-sube-subc.ll | 5 ; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/ |
| D | long.ll | 100 define i64 @f9a(i64 %x, i64 %y) { ; ADDC with small negative imm => SUBS imm
112 define i64 @f9b(i64 %x, i64 %y) { ; ADDC with big negative imm => SUBS reg
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 208 ADDC, SUBC, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 214 ADDC, SUBC, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 223 ADDC, SUBC, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeDelaySlotFiller.cpp | 196 op == MBlaze::ADDC || op == MBlaze::ADDIC || in hasUnknownSideEffects()
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 199 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in trySelect()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelDAGToDAG.cpp | 213 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in Select()
|
| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4.h | 227 EMIT2(ADDC)
|
| D | brw_vec4_builder.h | 397 ALU2_ACC(ADDC) in ALU2_ACC() argument
|
| D | brw_eu.h | 199 ALU2(ADDC)
|
| D | brw_fs_builder.h | 451 ALU2_ACC(ADDC) in ALU2_ACC() argument
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_32.c | 99 …return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(… in emit_single_op()
|
| D | sljitNativePPC_32.c | 125 return push_inst(compiler, ADDC | RC(ALT_SET_FLAGS) | D(dst) | A(src1) | B(src2)); in emit_single_op()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 74 ADDC, // Add with carry enumerator
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 1142 case ISD::ADDC: in ExpandIntegerResult()
1277 TLI.isOperationLegalOrCustom(ISD::ADDC, in ExpandShiftByConstant()
1282 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2); in ExpandShiftByConstant()
1519 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
1525 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); in ExpandIntRes_ADDSUB()
1573 if (N->getOpcode() == ISD::ADDC) { in ExpandIntRes_ADDSUBC()
1574 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); in ExpandIntRes_ADDSUBC()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 71 ADDC, // Add with carry enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 41 MBlaze::ADD, MBlaze::RSUB, MBlaze::ADDC, MBlaze::RSUBC, //00,01,02,03
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 39 ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout). enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 98 ADDC, // Add with carry enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 226 case ISD::ADDC: return "addc"; in getOperationName()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 477 case ISD::ADDC: in Select()
702 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC; in SelectADD_SUB_I64()
703 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64()
|