Home
last modified time | relevance | path

Searched refs:ANDI (Results 1 – 25 of 30) sorted by relevance

12

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dp8-scalar_vector_conversions.ll537 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
538 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
565 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
566 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
816 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
817 ; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
846 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
847 ; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/
Dand.ll70 ; Per PR 31345, we optimize away ANDI Rd, 0xff
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_32.c96 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst)); in emit_single_op()
115 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xffff), DR(dst)); in emit_single_op()
385 EMIT_LOGICAL(ANDI, AND); in emit_single_op()
DsljitNativeMIPS_64.c182 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst)); in emit_single_op()
197 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xffff), DR(dst)); in emit_single_op()
479 EMIT_LOGICAL(ANDI, AND); in emit_single_op()
DsljitNativePPC_32.c183 return push_inst(compiler, ANDI | S(src1) | A(dst) | compiler->imm); in emit_single_op()
DsljitNativeARM_T2_32.c106 #define ANDI 0xf0000000 macro
676 return push_inst32(compiler, ANDI | (flags & SET_FLAGS) | RD4(dst) | RN4(reg) | nimm); in emit_op_imm()
2170 FAIL_IF(push_inst32(compiler, ANDI | RN4(dst_r) | RD4(dst_r) | 1)); in sljit_emit_op_flags()
2171 FAIL_IF(push_inst32(compiler, ANDI | RN4(dst_r) | RD4(dst_r) | 0)); in sljit_emit_op_flags()
DsljitNativePPC_64.c335 return push_inst(compiler, ANDI | S(src1) | A(dst) | compiler->imm); in emit_single_op()
DsljitNativeARM_64.c74 #define ANDI 0x92000000 macro
641 return push_inst(compiler, (ANDI ^ inv_bits) | RD(dst) | RN(reg) | inst_bits); in emit_op_imm()
DsljitNativeMIPS_common.c114 #define ANDI (HI(12)) macro
1932 FAIL_IF(push_inst(compiler, ANDI | SA(dst_ar) | TA(dst_ar) | IMM(1), dst_ar)); in sljit_emit_op_flags()
DsljitNativePPC_common.c147 #define ANDI (HI(28)) macro
/external/llvm/test/CodeGen/PowerPC/
Dp8-scalar_vector_conversions.ll681 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
682 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
715 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8
716 ; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]]
1032 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
1033 ; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
1068 ; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4
1069 ; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1
/external/v8/src/mips/
Dconstants-mips.h441 ANDI = ((1U << 3) + 4) << kOpcodeShift, enumerator
1264 OpcodeToBitNumber(ANDI) | OpcodeToBitNumber(ORI) |
Ddisasm-mips.cc1887 case ANDI: in DecodeTypeImmediate()
Dassembler-mips.cc762 return GetOpcodeField(instr) == ANDI; in IsAndImmediate()
1999 GenInstrImmediate(ANDI, rs, rt, j); in andi()
/external/v8/src/mips64/
Dconstants-mips64.h411 ANDI = ((1U << 3) + 4) << kOpcodeShift, enumerator
1297 OpcodeToBitNumber(SLTIU) | OpcodeToBitNumber(ANDI) |
Ddisasm-mips64.cc2149 case ANDI: in DecodeTypeImmediate()
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Dand_ops.ll183 ; ANDI instruction generation (i32 data type):
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
DMBlazeDisassembler.cpp53 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td330 def ANDI : ALU_ri<0b111, "andi">;
591 def : PatGprSimm12<and, ANDI>;
DRISCVInstrInfoC.td609 def : CompressPat<(ANDI GPRC:$rs1, GPRC:$rs1, simm6:$imm),
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeISelLowering.cpp293 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT) in EmitCustomShift()
DMBlazeInstrInfo.td416 def ANDI : LogicI<0x29, "andi ", and>;
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td634 // ANDI Rd+1:Rd, K+1:K
1657 // Alias for `ANDI Rd, COM(K)` where COM(K) is the compliment of K.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td668 // ANDI Rd+1:Rd, K+1:K
1756 // Alias for `ANDI Rd, COM(K)` where COM(K) is the complement of K.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DP9InstrResources.td134 (instregex "ANDI(S)?o(8)?$"),

12