| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 66 unsigned MulOpc, unsigned AddSubOpc,
207 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
222 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
292 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
295 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
299 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 282 unsigned &AddSubOpc, bool &NegAcc,
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| D | ARMBaseInstrInfo.cpp | 57 unsigned AddSubOpc; // Expanded add / sub opcode member
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
2755 unsigned &AddSubOpc, in isFpMLxInstruction() argument
2763 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 69 unsigned MulOpc, unsigned AddSubOpc,
273 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
360 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
363 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
367 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 383 unsigned &AddSubOpc, bool &NegAcc,
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| D | ARMBaseInstrInfo.cpp | 58 uint16_t AddSubOpc; // Expanded add / sub opcode member
92 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
4150 unsigned &AddSubOpc, in isFpMLxInstruction() argument
4158 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 69 unsigned MulOpc, unsigned AddSubOpc,
273 unsigned MulOpc, unsigned AddSubOpc, in ExpandFPMLxInstruction() argument
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
357 unsigned MulOpc, AddSubOpc; in ExpandFPMLxInstructions() local
360 MulOpc, AddSubOpc, NegAcc, HasLane) || in ExpandFPMLxInstructions()
364 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane); in ExpandFPMLxInstructions()
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| D | ARMBaseInstrInfo.h | 414 unsigned &AddSubOpc, bool &NegAcc,
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| D | ARMBaseInstrInfo.cpp | 82 uint16_t AddSubOpc; // Expanded add / sub opcode member
116 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc); in ARMBaseInstrInfo()
4544 unsigned &AddSubOpc, in isFpMLxInstruction() argument
4552 AddSubOpc = Entry.AddSubOpc; in isFpMLxInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 8698 unsigned ShiftAmt, AddSubOpc; in performMulCombine() local
8712 AddSubOpc = ISD::ADD; in performMulCombine()
8715 AddSubOpc = ISD::SUB; in performMulCombine()
8725 AddSubOpc = ISD::SUB; in performMulCombine()
8729 AddSubOpc = ISD::ADD; in performMulCombine()
8742 SDValue Res = DAG.getNode(AddSubOpc, DL, VT, AddSubN0, AddSubN1); in performMulCombine()
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