Searched refs:ArgDescriptor (Results 1 – 8 of 8) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUArgumentUsageInfo.h | 26 struct ArgDescriptor { struct
39 ArgDescriptor(unsigned Val = 0, bool IsStack = false, bool IsSet = false) argument
42 static ArgDescriptor createRegister(unsigned Reg) { in createRegister() argument
43 return ArgDescriptor(Reg, false, true); in createRegister()
46 static ArgDescriptor createStack(unsigned Reg) { in createStack() argument
47 return ArgDescriptor(Reg, true, true); in createStack()
75 inline raw_ostream &operator<<(raw_ostream &OS, const ArgDescriptor &Arg) { argument
107 ArgDescriptor PrivateSegmentBuffer;
108 ArgDescriptor DispatchPtr;
109 ArgDescriptor QueuePtr;
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| D | SIMachineFunctionInfo.cpp | 77 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
79 ArgDescriptor::createRegister(ScratchWaveOffsetReg); in SIMachineFunctionInfo()
136 = ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
189 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
196 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
203 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
211 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
218 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
225 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
232 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addImplicitBufferPtr()
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| D | SIMachineFunctionInfo.h | 265 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR()); in addWorkGroupIDX()
271 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR()); in addWorkGroupIDY()
277 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR()); in addWorkGroupIDZ()
283 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR()); in addWorkGroupInfo()
289 void setWorkItemIDX(ArgDescriptor Arg) { in setWorkItemIDX()
293 void setWorkItemIDY(ArgDescriptor Arg) { in setWorkItemIDY()
297 void setWorkItemIDZ(ArgDescriptor Arg) { in setWorkItemIDZ()
303 = ArgDescriptor::createRegister(getNextSystemSGPR()); in addPrivateSegmentWaveByteOffset()
309 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg); in setPrivateSegmentWaveByteOffset()
384 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
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| D | AMDGPUArgumentUsageInfo.cpp | 22 void ArgDescriptor::print(raw_ostream &OS, in print()
73 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
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| D | AMDGPUISelLowering.h | 27 struct ArgDescriptor;
289 const ArgDescriptor &Arg) const;
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| D | SIISelLowering.cpp | 1196 const ArgDescriptor *InputPtrReg; in lowerKernArgParameterPtr()
1336 const ArgDescriptor *Reg; in getPreloadedValue()
1401 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1409 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1417 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1423 static ArgDescriptor allocateVGPR32Input(CCState &CCInfo) { in allocateVGPR32Input()
1431 return ArgDescriptor::createStack(Offset); in allocateVGPR32Input()
1440 return ArgDescriptor::createRegister(Reg); in allocateVGPR32Input()
1443 static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo, in allocateSGPR32InputImpl()
1457 return ArgDescriptor::createRegister(Reg); in allocateSGPR32InputImpl()
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| D | AMDGPUInstructionSelector.cpp | 198 const ArgDescriptor *InputPtrReg; in selectG_INTRINSIC()
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| D | AMDGPUISelLowering.cpp | 3961 const ArgDescriptor &Arg) const { in loadInputValue()
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