| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 86 bool Artificial; variable
157 bool Artificial; member
340 bool Artificial; variable
488 bool Artificial; member
490 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { in RegUnit()
668 RU.Artificial = R0->Artificial;
670 RU.Artificial |= R1->Artificial;
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| D | CodeGenRegisters.cpp | 54 : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) { in CodeGenSubRegIndex()
65 EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) { in CodeGenSubRegIndex()
165 Artificial = R->getValueAsBit("isArtificial"); in CodeGenRegister()
279 if (!SR->Artificial) in computeSubRegs()
280 Idx->Artificial = false; in computeSubRegs()
392 SR->Artificial) in computeSubRegs()
399 if (!I.Artificial) in computeSubRegs()
754 Artificial = true; in CodeGenRegisterClass()
759 Artificial &= Reg->Artificial; in CodeGenRegisterClass()
818 Artificial = true; in CodeGenRegisterClass()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MacroFusion.cpp | 85 DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial)); in fuseInstructionPair()
97 DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial)); in fuseInstructionPair()
105 DAG.addEdge(&FirstSU, SDep(&SU, SDep::Artificial)); in fuseInstructionPair()
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| D | ScheduleDAGInstrs.cpp | 252 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
836 SDep Dep(SU, SDep::Artificial); in buildSchedGraph()
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| D | ScheduleDAG.cpp | 96 case Artificial: OS << " Artificial"; break; in print()
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| /external/python/cpython2/Lib/email/test/data/ |
| D | msg_06.txt | 13 X-Mailer: VM 6.95 under 21.4 (patch 4) "Artificial Intelligence" XEmacs Lucid
28 X-Mailer: VM 6.95 under 21.4 (patch 4) "Artificial Intelligence" XEmacs Lucid
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| D | msg_44.txt | 13 X-Mailer: VM 6.95 under 21.4 (patch 4) "Artificial Intelligence" XEmacs Lucid
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| D | msg_04.txt | 13 X-Mailer: VM 6.95 under 21.4 (patch 4) "Artificial Intelligence" XEmacs Lucid
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| /external/python/cpython3/Lib/test/test_email/data/ |
| D | msg_06.txt | 13 X-Mailer: VM 6.95 under 21.4 (patch 4) "Artificial Intelligence" XEmacs Lucid
28 X-Mailer: VM 6.95 under 21.4 (patch 4) "Artificial Intelligence" XEmacs Lucid
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| D | msg_44.txt | 13 X-Mailer: VM 6.95 under 21.4 (patch 4) "Artificial Intelligence" XEmacs Lucid
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| D | msg_04.txt | 13 X-Mailer: VM 6.95 under 21.4 (patch 4) "Artificial Intelligence" XEmacs Lucid
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| /external/llvm/include/llvm/IR/ |
| D | DebugInfoFlags.def | 26 HANDLE_DI_FLAG((1 << 6), Artificial)
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | DebugInfoFlags.def | 28 HANDLE_DI_FLAG((1 << 6), Artificial)
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 73 Artificial, ///< Arbitrary strong DAG edge (no real dependence). enumerator
202 return getKind() == Order && Contents.OrdKind == Artificial; in isArtificial()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUSubtarget.cpp | 660 SUa->addPred(SDep(SI.getSUnit(), SDep::Artificial)); in apply()
666 SI.getSUnit()->addPred(SDep(&SU, SDep::Artificial)); in apply()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 68 Artificial, ///< Arbitrary strong DAG edge (no real dependence). enumerator
200 return getKind() == Order && Contents.OrdKind == Artificial; in isArtificial()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 605 AddPred(TrySU, SDep(Copies.front(), SDep::Artificial)); in ListScheduleBottomUp()
612 AddPred(NewDef, SDep(TrySU, SDep::Artificial)); in ListScheduleBottomUp()
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| D | ScheduleDAGRRList.cpp | 1164 AddPred(SuccSU, SDep(CopyFromSU, SDep::Artificial)); in InsertCopiesAndMoveSuccs()
1419 AddPred(TrySU, SDep(BtSU, SDep::Artificial)); in PickNodeToScheduleBottomUp()
1470 AddPred(TrySU, SDep(Copies.front(), SDep::Artificial)); in PickNodeToScheduleBottomUp()
1477 AddPred(NewDef, SDep(TrySU, SDep::Artificial)); in PickNodeToScheduleBottomUp()
2952 scheduleDAG->AddPred(&SU, SDep(SuccSU, SDep::Artificial)); in AddPseudoTwoAddrDeps()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 598 AddPred(TrySU, SDep(Copies.front(), SDep::Artificial)); in ListScheduleBottomUp()
605 AddPred(NewDef, SDep(TrySU, SDep::Artificial)); in ListScheduleBottomUp()
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| D | ScheduleDAGRRList.cpp | 1240 AddPred(SuccSU, SDep(CopyFromSU, SDep::Artificial)); in InsertCopiesAndMoveSuccs()
1509 AddPred(TrySU, SDep(BtSU, SDep::Artificial)); in PickNodeToScheduleBottomUp()
1563 AddPred(TrySU, SDep(Copies.front(), SDep::Artificial)); in PickNodeToScheduleBottomUp()
1570 AddPred(NewDef, SDep(TrySU, SDep::Artificial)); in PickNodeToScheduleBottomUp()
3080 scheduleDAG->AddPred(&SU, SDep(SuccSU, SDep::Artificial)); in AddPseudoTwoAddrDeps()
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| /external/llvm/test/Transforms/LoopVectorize/ |
| D | runtime-check-readonly-address-space.ll | 3 ; Artificial datalayout
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| D | runtime-check-address-space.ll | 19 ; Artificial datalayout
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/ |
| D | runtime-check-readonly-address-space.ll | 3 ; Artificial datalayout
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| D | runtime-check-address-space.ll | 19 ; Artificial datalayout
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 303 SDep A(&S0, SDep::Artificial); in apply()
|