Searched refs:AvailableRegs (Results 1 – 6 of 6) sorted by relevance
31 SmallVector<unsigned, 5> AvailableRegs; in CC_X86_32_RegCall_Assign2Regs() local36 AvailableRegs.push_back(Reg); in CC_X86_32_RegCall_Assign2Regs()40 if (AvailableRegs.size() < RequiredGprsUponSplit) in CC_X86_32_RegCall_Assign2Regs()47 unsigned Reg = State.AllocateReg(AvailableRegs[I]); in CC_X86_32_RegCall_Assign2Regs()
154 const TargetRegisterClass &AvailableRegs = *TRI->getGPRsForTailCall(*MF); in findDeadCallerSavedReg() local187 for (auto CS : AvailableRegs) in findDeadCallerSavedReg()
27760 SmallVector<unsigned, 3> AvailableRegs; in EmitLoweredRetpoline() local27762 AvailableRegs.push_back(X86::R11); in EmitLoweredRetpoline()27764 AvailableRegs.append({X86::EAX, X86::ECX, X86::EDX, X86::EDI}); in EmitLoweredRetpoline()27769 for (unsigned &Reg : AvailableRegs) in EmitLoweredRetpoline()27776 for (unsigned MaybeReg : AvailableRegs) { in EmitLoweredRetpoline()
507 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister() local510 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister()516 AvailableRegs.clearBitsNotInMask(J.getRegMask()); in scavengeRegister()522 AvailableRegs.reset(*AI); in scavengeRegister()526 assert(!AvailableRegs[*AI] && in scavengeRegister()536 if (!AvailableRegs[Reg]) in scavengeRegister()
1819 SmallVector<unsigned, 4> AvailableRegs; in determineCalleeSaves() local1852 AvailableRegs.push_back(Reg); in determineCalleeSaves()1867 AvailableRegs.push_back(ARM::R7); in determineCalleeSaves()1895 AvailableRegs.push_back(ARM::LR); in determineCalleeSaves()1906 for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) { in determineCalleeSaves()1907 unsigned Reg = AvailableRegs.pop_back_val(); in determineCalleeSaves()
157 const TargetRegisterClass &AvailableRegs = *TRI->getGPRsForTailCall(*MF); in findDeadCallerSavedReg() local188 for (auto CS : AvailableRegs) in findDeadCallerSavedReg()