Searched refs:BRW_ALIGN_1 (Results 1 – 11 of 11) sorted by relevance
/external/mesa3d/src/intel/compiler/ |
D | brw_vec4_generator.cpp | 67 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_math_gen6() 230 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_tex() 305 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_tex() 392 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_urb_write_allocate() 439 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_write_offset() 481 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_vertex_count() 540 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_svb_set_destination_index() 552 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_dword_2() 570 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_prepare_channel_masks() 634 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_gs_set_channel_masks() [all …]
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D | brw_eu_emit.c | 105 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_dest() 128 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_dest() 213 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src0() 221 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src0() 228 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src0() 312 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src1() 318 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_set_src1() 730 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_alu3() 990 brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1 && in ALU1() 1134 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_F32TO16() [all …]
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D | brw_clip_util.c | 96 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_clip_project_position() 211 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_clip_interp_vertex() 232 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_clip_interp_vertex()
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D | brw_disasm.c | 708 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in dest() 759 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in dest_3src() 1029 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in src0_3src() 1107 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in src1_3src() 1175 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; in src2_3src() 1303 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in src0() 1359 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in src1() 1473 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in brw_disassemble_inst()
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D | brw_eu_validate.c | 469 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 && in general_restrictions_based_on_operand_types() 1046 unsigned dst_subreg = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 ? in vector_immediate_restrictions() 1164 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 && in special_requirements_for_handling_double_precision_data_types()
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D | test_eu_compact.cpp | 297 brw_set_default_access_mode(p, BRW_ALIGN_1); in run_tests()
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D | brw_eu_defines.h | 88 #define BRW_ALIGN_1 0 macro
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D | brw_clip_unfilled.c | 86 brw_set_default_access_mode(p, BRW_ALIGN_1); in compute_tri_direction()
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D | brw_compile_sf.c | 663 brw_set_default_access_mode(p, BRW_ALIGN_1); in brw_emit_point_sprite_setup()
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D | brw_fs_generator.cpp | 1008 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_tex() 1700 brw_set_default_access_mode(p, BRW_ALIGN_1); in generate_code()
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
D | brw_ff_gs_emit.c | 451 brw_set_default_access_mode(p, BRW_ALIGN_1); in gen6_sol_program()
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