Searched refs:BUS_HCLK_HZ (Results 1 – 6 of 6) sorted by relevance
125 hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1; in rkclk_init()126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
126 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; in rkclk_init()127 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); in rkclk_init()
187 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; in rkclk_init()188 assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3); in rkclk_init()
19 #define BUS_HCLK_HZ 148500000 macro
21 #define BUS_HCLK_HZ 148500000 macro
20 #define BUS_HCLK_HZ 148500000 macro