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Searched refs:BaseMask (Results 1 – 4 of 4) sorted by relevance

/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
DSVals.h54 enum { BaseBits = 2, BaseMask = 0x3 }; enumerator
99 inline BaseKind getBaseKind() const { return (BaseKind) (Kind & BaseMask); } in getBaseKind()
100 inline unsigned getSubKind() const { return (Kind & ~BaseMask) >> BaseBits; } in getSubKind()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/
Dx86-pshufb.ll473 define <16 x i8> @demanded_elts_insertion(<16 x i8> %InVec, <16 x i8> %BaseMask, i8 %M0, i8 %M15) {
475 …TMP1:%.*]] = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> %BaseMask)
479 %1 = insertelement <16 x i8> %BaseMask, i8 %M0, i32 0
486 define <32 x i8> @demanded_elts_insertion_avx2(<32 x i8> %InVec, <32 x i8> %BaseMask, i8 %M0, i8 %M…
488 … [[TMP1:%.*]] = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> %BaseMask)
491 %1 = insertelement <32 x i8> %BaseMask, i8 %M0, i32 0
498 define <64 x i8> @demanded_elts_insertion_avx512(<64 x i8> %InVec, <64 x i8> %BaseMask, i8 %M0, i8 …
505 %1 = insertelement <64 x i8> %BaseMask, i8 %M0, i32 0
/external/libaom/libaom/aom_dsp/x86/
Dintrapred_avx2.c2929 static uint8_t BaseMask[33][32] = { variable
3086 _mm_blendv_epi8(a_mbase_x, res1, *(__m128i *)BaseMask[base_max_diff]); in dr_prediction_z1_4xN_internal_avx2()
3177 _mm_blendv_epi8(a_mbase_x, res128, *(__m128i *)BaseMask[base_max_diff]); in dr_prediction_z1_8xN_internal_avx2()
3271 *(__m128i *)BaseMask[base_max_diff]); in dr_prediction_z1_16xN_internal_avx2()
3377 *(__m256i *)BaseMask[base_max_diff]); // 32 8bit values in dr_prediction_z1_32xN_internal_avx2()
3680 resxy = _mm_blendv_epi8(resx, resy, *(__m128i *)BaseMask[base_min_diff]); in dr_prediction_z2_Nx4_avx2()
3814 resxy = _mm_blendv_epi8(resx, resy, *(__m128i *)BaseMask[base_min_diff]); in dr_prediction_z2_Nx8_avx2()
3980 resxy = _mm_blendv_epi8(resx, resy, *(__m128i *)BaseMask[base_min_diff]); in dr_prediction_z2_HxW_avx2()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp29624 ArrayRef<int> BaseMask, int Depth, in combineX86ShuffleChain() argument
29627 assert(!BaseMask.empty() && "Cannot combine an empty shuffle mask!"); in combineX86ShuffleChain()
29648 unsigned NumBaseMaskElts = BaseMask.size(); in combineX86ShuffleChain()
29650 assert(BaseMask[0] == 0 && "Invalid shuffle index found!"); in combineX86ShuffleChain()
29677 !(Subtarget.hasAVX2() && BaseMask[0] >= -1 && BaseMask[1] >= -1) && in combineX86ShuffleChain()
29678 !isSequentialOrUndefOrZeroInRange(BaseMask, 0, 2, 0)) { in combineX86ShuffleChain()
29683 PermMask |= ((BaseMask[0] < 0 ? 0x8 : (BaseMask[0] & 1)) << 0); in combineX86ShuffleChain()
29684 PermMask |= ((BaseMask[1] < 0 ? 0x8 : (BaseMask[1] & 1)) << 4); in combineX86ShuffleChain()
29699 scaleShuffleMask<int>(MaskScale, BaseMask, Mask); in combineX86ShuffleChain()
29701 Mask = SmallVector<int, 64>(BaseMask.begin(), BaseMask.end()); in combineX86ShuffleChain()