| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | madd-lohi.ll | 6 ; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2
7 ; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]]
12 ; CHECK-BE-DAG: umulh [[CARRY:x[0-9]+]], x1, x3
13 ; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | madd-lohi.ll | 6 ; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2
7 ; CHECK-DAG: madd [[PART1:x[0-9]+]], x0, x3, [[CARRY]]
12 ; CHECK-BE-DAG: umulh [[CARRY:x[0-9]+]], x1, x3
13 ; CHECK-BE-DAG: madd [[PART1:x[0-9]+]], x1, x2, [[CARRY]]
|
| D | mul-lohi.ll | 7 ; CHECK-DAG: umulh [[CARRY:x[0-9]+]], x0, x2
13 ; CHECK-BE-DAG: umulh [[CARRY:x[0-9]+]], x1, x3
|
| /external/epid-sdk/ext/ipp/sources/ippcp/ |
| D | pcpbnuimpl.h | 102 #define ADD_AB(CARRY,R, A,B) \ argument
105 (CARRY) = __s < (A); \
110 #define ADD_ABC(CARRY,R, A,B,C) \ argument
116 (CARRY) = __t1 + __t2; \
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 349 let Defs = [CARRY] in {
352 let Uses = [CARRY] in {
357 let Uses = [CARRY] in {
368 let Defs = [CARRY] in {
371 let Uses = [CARRY] in {
376 let Uses = [CARRY] in {
420 let Defs = [CARRY] in {
424 let Uses = [CARRY] in {
430 let Uses = [CARRY] in {
455 let Defs = [CARRY] in {
[all …]
|
| D | MBlazeInstrFSL.td | 127 let Defs = [CARRY] in {
166 let Defs = [CARRY] in {
197 let Defs = [CARRY] in {
220 let Defs = [CARRY] in {
|
| D | MBlazeRegisterInfo.td | 105 def CARRY : MBlazeSPRReg<0x0000, "rmsr[c]">;
146 def CRC : RegisterClass<"MBlaze", [i32], 32, (add CARRY)> {
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 73 CR0,CR1,CR5,CR6,CR7,CARRY] in {
99 CR0,CR1,CR5,CR6,CR7,CARRY] in {
330 let Defs = [CARRY] in {
346 let Defs = [CARRY] in {
361 let Uses = [CARRY], Defs = [CARRY] in {
405 let Defs = [CARRY] in {
429 let Defs = [CARRY] in {
|
| D | PPCInstrInfo.td | 440 CR0,CR1,CR5,CR6,CR7,CARRY] in {
465 CR0,CR1,CR5,CR6,CR7,CARRY] in {
856 let Defs = [CARRY] in {
875 let Defs = [CARRY] in {
952 let Defs = [CARRY] in {
960 let Defs = [CARRY] in {
1163 let Defs = [CARRY] in {
1189 let Defs = [CARRY] in {
1198 let Uses = [CARRY], Defs = [CARRY] in {
|
| D | PPCRegisterInfo.td | 264 def CARRY: SPR<1, "ca">;
324 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
|
| /external/llvm/lib/Target/SystemZ/ |
| D | README.txt | 60 ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | README.txt | 60 ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 262 CARRY, enumerator
|
| D | AMDGPUInstrInfo.td | 135 def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
|
| D | AMDGPUISelLowering.cpp | 2833 NODE_NAME_CASE(CARRY) in getTargetNodeName()
2933 case AMDGPUISD::CARRY: in computeKnownBitsForTargetNode()
2980 case AMDGPUISD::CARRY: in ComputeNumSignBitsForTargetNode()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 219 def CARRY: SPR<1, "ca">, DwarfRegNum<[76]>;
360 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> {
|
| D | PPCInstrInfo.td | 818 let Defs = [CARRY] in
822 let Defs = [CARRY, CR0] in
833 let Defs = [CARRY] in
837 let Defs = [CARRY, CR0] in
893 let Defs = [CARRY] in
897 let Defs = [CARRY, CR0] in
922 let Defs = [CARRY] in
926 let Defs = [CARRY, CR0] in
979 let Defs = [CARRY] in
983 let Defs = [CARRY, CR0] in
[all …]
|
| D | PPCInstr64Bit.td | 502 let Defs = [CARRY] in
513 let Defs = [CARRY] in {
528 let Uses = [CARRY] in {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.td | 235 def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {
385 def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
|
| D | PPCInstrInfo.td | 933 let Defs = [CARRY] in
937 let Defs = [CARRY, CR0] in
948 let Defs = [CARRY] in
952 let Defs = [CARRY, CR0] in
1008 let Defs = [CARRY] in
1012 let Defs = [CARRY, CR0] in
1037 let Defs = [CARRY] in
1041 let Defs = [CARRY, CR0] in
1094 let Defs = [CARRY] in
1098 let Defs = [CARRY, CR0] in
[all …]
|
| D | PPCInstr64Bit.td | 551 let Defs = [CARRY] in
562 let Defs = [CARRY] in {
577 let Uses = [CARRY] in {
725 let isCodeGenOnly = 1, Defs = [CARRY] in
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 391 CARRY, enumerator
|
| D | AMDGPUInstrInfo.td | 211 def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
|
| D | AMDGPUISelLowering.cpp | 4043 NODE_NAME_CASE(CARRY) in getTargetNodeName()
4184 case AMDGPUISD::CARRY: in computeKnownBitsForTargetNode()
4313 case AMDGPUISD::CARRY: in ComputeNumSignBitsForTargetNode()
|
| D | R600ISelLowering.cpp | 483 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()
|