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Searched refs:CCM_PLL5_CTRL_EN (Results 1 – 8 of 8) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/
Dclock_sun8i_a83t.c114 writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | in clock_set_pll5()
Dclock_sun6i.c203 writel(CCM_PLL5_CTRL_EN | in clock_set_pll5()
Ddram_sun8i_a83t.c399 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
Ddram_sun4i.c287 reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */ in mctl_setup_dram_clock()
Ddram_sunxi_dw.c375 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Dclock_sun8i_a83t.h173 #define CCM_PLL5_CTRL_EN (0x1 << 31) macro
Dclock_sun4i.h243 #define CCM_PLL5_CTRL_EN (0x1 << 31) macro
Dclock_sun6i.h219 #define CCM_PLL5_CTRL_EN (0x1 << 31) macro