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Searched refs:CKSEG1ADDR (Results 1 – 11 of 11) sorted by relevance

/external/u-boot/board/imgtec/malta/
Dmalta.c38 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); in malta_lcd_puts()
56 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); in malta_core_card()
128 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); in _machine_restart()
140 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); in board_early_init_f()
144 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); in board_early_init_f()
174 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), in pci_init_board()
182 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), in pci_init_board()
185 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), in pci_init_board()
Dlowlevel_init.S31 PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
65 PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
70 PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
97 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
119 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
154 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
/external/u-boot/arch/mips/mach-ath79/ar933x/
Dlowlevel_init.S81 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
110 li t0, CKSEG1ADDR(AR933X_RTC_BASE)
135 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
157 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
233 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
271 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
Dddr.c279 addr_k1 = (void *)CKSEG1ADDR(0x2000); in ddr_tap_tuning()
/external/u-boot/arch/mips/mach-ath79/qca953x/
Dlowlevel_init.S101 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
114 li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
127 li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
134 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
178 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
/external/u-boot/board/imgtec/boston/
Dboston-regs.h11 #define BOSTON_PLAT_BASE CKSEG1ADDR(0x17ffd000)
12 #define BOSTON_LCD_BASE CKSEG1ADDR(0x17fff000)
/external/u-boot/arch/mips/include/asm/
Daddrspace.h71 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) macro
78 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) macro
138 #define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
Dcm.h45 return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); in mips_cm_base()
Dio.h152 return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr); in __ioremap_mode()
/external/u-boot/arch/mips/mach-pic32/include/mach/
Dpic32.h72 return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE); in pic32_get_syscfg_base()
/external/u-boot/arch/mips/lib/
Dcache_init.S151 PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
367 li t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
409 PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)