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Searched refs:CLKID_FCLK_DIV3 (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/clk/
Dclk_meson.c115 MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28),
171 CLKID_FCLK_DIV3, in meson_clk81_get_rate()
325 case CLKID_FCLK_DIV3: in meson_clk_get_rate_by_id()
/external/u-boot/include/dt-bindings/clock/
Dgxbb-clkc.h13 #define CLKID_FCLK_DIV3 5 macro
/external/u-boot/arch/arm/dts/
Dmeson-gxbb.dtsi691 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
Dmeson-gxl.dtsi700 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,