Searched refs:CLK_CTRL_DIV0_SHIFT (Results 1 – 2 of 2) sorted by relevance
94 #define CLK_CTRL_DIV0_SHIFT 8 macro95 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)380 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_cpu_rate()403 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_ddr_rate()428 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_peripheral_rate()463 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_wdt_rate()474 div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_wdt_rate()552 clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_set_peripheral_rate()554 mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) | in zynqmp_clk_set_peripheral_rate()
32 #define CLK_CTRL_DIV0_SHIFT 8 macro33 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)176 div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_cpu_rate()231 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_dci_rate()248 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_peripheral_rate()339 clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT; in zynq_clk_set_peripheral_rate()